(0x50, 'MDER', pio_bits), (0x54, 'MDDR', pio_bits), (0x58, 'MDSR', pio_bits), (0x60, 'PUDR', pio_bits), (0x64, 'PUER', pio_bits), (0x68, 'PUSR', pio_bits), (0x70, 'ABSR', pio_bits), (0x80, 'SCIFSR', pio_bits), (0x84, 'DIFSR', pio_bits), (0x88, 'IFDGSR', pio_bits), (0x8c, 'SCDR', [ ('div', 14), ('', 18), ]), (0xa0, 'OWER', pio_bits), (0xa4, 'OWDR', pio_bits), (0xa8, 'OWSR', pio_bits), (0xb0, 'AIMER', pio_bits), (0xb4, 'AIMDR', pio_bits), (0xb8, 'AIMMR', pio_bits), (0xc0, 'ESR', pio_bits), (0xc4, 'LSR', pio_bits), (0xc8, 'ELSR', pio_bits), (0xd0, 'FELLSR', pio_bits), (0xd4, 'REHLSR', pio_bits), (0xd8, 'FRLHSR', pio_bits), (0xe0, 'LOCKSR', pio_bits), (0xe4, 'WPMR', common.wpmr(0x50494f)), (0xe8, 'WPSR', common.wpsr), ]
(0x50, 'MAN', [ ('tx_pl', 4), ('', 4), ('tx_pp', 2, [ ('ALL_ONE', 0), ('ALL_ZERO', 1), ('ZERO_ONE', 2), ('ONE_ZERO', 3), ]), ('', 2), ('tx_mpol', 1), ('', 3), ('rx_pl', 4), ('', 4), ('rx_pp', 2, [ ('ALL_ONE', 0), ('ALL_ZERO', 1), ('ZERO_ONE', 2), ('ONE_ZERO', 3), ]), ('', 2), ('rx_mpol', 1), ('stuckto1', 1), ('drift', 1), ('', 1), ]), (0xe4, 'WPMR', common.wpmr(0x555341)), (0xe8, 'WPSR', common.wpsr), ]
('arbt', 2), ('', 6), ]), ], [ 10, 4, (0x0080, 'PRAS', [ ('m0pr', 2), ('', 2), ('m1pr', 2), ('', 2), ('m2pr', 2), ('', 2), ('m3pr', 2), ('', 2), ('m4pr', 2), ('', 14), ]), ], (0x0100, 'MRCR', [ ('rcb0', 1), ('rcb1', 1), ('rcb2', 1), ('rcb3', 1), ('rcb4', 1), ('', 27), ]), (0x01e4, 'WPMR', common.wpmr(0x4d4154)), (0x01e8, 'WPSR', common.wpsr), ]
(0x14, 'IER', spi_irqs), (0x18, 'IDR', spi_irqs), (0x1c, 'IMR', spi_irqs), [ 4, 4, (0x30, 'CSR', [ ('cpol', 1), ('ncpha', 1), ('csnaat', 1), ('csaat', 1), ('bits', 4, [ ('8_BIT', 0), ('9_BIT', 1), ('10_BIT', 2), ('11_BIT', 3), ('12_BIT', 4), ('13_BIT', 5), ('14_BIT', 6), ('15_BIT', 7), ('16_BIT', 8), ]), ('scbr', 8), ('dlybs', 8), ('dlybct', 8), ]), ], (0xe4, 'WPMR', common.wpmr(0x535049)), (0xe8, 'WPSR', common.wpsr), ]
(0x54, 'MDDR', pio_bits), (0x58, 'MDSR', pio_bits), (0x60, 'PUDR', pio_bits), (0x64, 'PUER', pio_bits), (0x68, 'PUSR', pio_bits), (0x70, 'ABSR', pio_bits), (0x80, 'SCIFSR', pio_bits), (0x84, 'DIFSR', pio_bits), (0x88, 'IFDGSR', pio_bits), (0x8c, 'SCDR', [ ('div', 14), ('', 18), ]), (0xa0, 'OWER', pio_bits), (0xa4, 'OWDR', pio_bits), (0xa8, 'OWSR', pio_bits), (0xb0, 'AIMER', pio_bits), (0xb4, 'AIMDR', pio_bits), (0xb8, 'AIMMR', pio_bits), (0xc0, 'ESR', pio_bits), (0xc4, 'LSR', pio_bits), (0xc8, 'ELSR', pio_bits), (0xd0, 'FELLSR', pio_bits), (0xd4, 'REHLSR', pio_bits), (0xd8, 'FRLHSR', pio_bits), (0xe0, 'LOCKSR', pio_bits), (0xe4, 'WPMR', common.wpmr(0x50494f)), (0xe8, 'WPSR', common.wpsr), ]
(0x38, 'RC0R', [ ('cp0', 16), ('', 16), ]), (0x3c, 'RC1R', [ ('cp1', 16), ('', 16), ]), (0x40, 'SR', [ ('txrdy', 1), ('txempty', 1), ('', 2), ('rxrdy', 1), ('ovrun', 1), ('', 2), ('cp0', 1), ('cp1', 1), ('txsyn', 1), ('rxsyn', 1), ('', 4), ('txen', 1), ('rxen', 1), ('', 14), ]), (0x44, 'IER', ssc_irqs), (0x48, 'IDR', ssc_irqs), (0x4c, 'IMR', ssc_irqs), (0xe4, 'WPMR', common.wpmr(0x535343)), (0xe8, 'WPSR', common.wpsr), ]
('secen', 1), ('timen', 1), ('calen', 1), ('', 27), ]), (0x24, 'IDR', [ ('ackdis', 1), ('alrdis', 1), ('secdis', 1), ('timdis', 1), ('caldis', 1), ('', 27), ]), (0x28, 'IMR', [ ('ack', 1), ('alr', 1), ('sec', 1), ('tim', 1), ('cal', 1), ('', 27), ]), (0x2c, 'VER', [ ('nvtim', 1), ('nvcal', 1), ('nvtimalr', 1), ('nvcalalr', 1), ('', 28), ]), (0xe4, 'WPMR', common.wpmr(0x525443)), ]
('', 1), ('lpm', 1), ('', 11), ]), (0x74, 'FSPR', [ ('fstp0', 1), ('fstp1', 1), ('fstp2', 1), ('fstp3', 1), ('fstp4', 1), ('fstp5', 1), ('fstp6', 1), ('fstp7', 1), ('fstp8', 1), ('fstp9', 1), ('fstp10', 1), ('fstp11', 1), ('fstp12', 1), ('fstp13', 1), ('fstp14', 1), ('fstp15', 1), ('', 16), ]), (0x78, 'FOCR', [ ('foclr', 1), ('', 31), ]), (0xe4, 'WPMR', common.wpmr(0x504d43)), (0xe8, 'WPSR', common.wpsr), ]
]), (0x50, 'MAN', [ ('tx_pl', 4), ('', 4), ('tx_pp', 2, [ ('ALL_ONE', 0), ('ALL_ZERO', 1), ('ZERO_ONE', 2), ('ONE_ZERO', 3), ]), ('', 2), ('tx_mpol', 1), ('', 3), ('rx_pl', 4), ('', 4), ('rx_pp', 2, [ ('ALL_ONE', 0), ('ALL_ZERO', 1), ('ZERO_ONE', 2), ('ONE_ZERO', 3), ]), ('', 2), ('rx_mpol', 1), ('stuckto1', 1), ('drift', 1), ('', 1), ]), (0xe4, 'WPMR', common.wpmr(0x555341)), (0xe8, 'WPSR', common.wpsr), ]
('', 6), ]), ], [ 10, 4, (0x0080, 'PRAS', [ ('m0pr', 2), ('', 2), ('m1pr', 2), ('', 2), ('m2pr', 2), ('', 2), ('m3pr', 2), ('', 2), ('m4pr', 2), ('', 14), ]), ], (0x0100, 'MRCR', [ ('rcb0', 1), ('rcb1', 1), ('rcb2', 1), ('rcb3', 1), ('rcb4', 1), ('', 27), ]), (0x01e4, 'WPMR', common.wpmr(0x4d4154)), (0x01e8, 'WPSR', common.wpsr), ]
("", 11), ], ), ( 0x74, "FSPR", [ ("fstp0", 1), ("fstp1", 1), ("fstp2", 1), ("fstp3", 1), ("fstp4", 1), ("fstp5", 1), ("fstp6", 1), ("fstp7", 1), ("fstp8", 1), ("fstp9", 1), ("fstp10", 1), ("fstp11", 1), ("fstp12", 1), ("fstp13", 1), ("fstp14", 1), ("fstp15", 1), ("", 16), ], ), (0x78, "FOCR", [("foclr", 1), ("", 31)]), (0xE4, "WPMR", common.wpmr(0x504D43)), (0xE8, "WPSR", common.wpsr), ]
('timen', 1), ('calen', 1), ('', 27), ]), (0x24, 'IDR', [ ('ackdis', 1), ('alrdis', 1), ('secdis', 1), ('timdis', 1), ('caldis', 1), ('', 27), ]), (0x28, 'IMR', [ ('ack', 1), ('alr', 1), ('sec', 1), ('tim', 1), ('cal', 1), ('', 27), ]), (0x2c, 'VER', [ ('nvtim', 1), ('nvcal', 1), ('nvtimalr', 1), ('nvcalalr', 1), ('', 28), ]), (0xe4, 'WPMR', common.wpmr(0x525443)), ]
]), (0x14, 'IER', spi_irqs), (0x18, 'IDR', spi_irqs), (0x1c, 'IMR', spi_irqs), [ 4, 4, (0x30, 'CSR', [ ('cpol', 1), ('ncpha', 1), ('csnaat', 1), ('csaat', 1), ('bits', 4, [ ('8_BIT', 0), ('9_BIT', 1), ('10_BIT', 2), ('11_BIT', 3), ('12_BIT', 4), ('13_BIT', 5), ('14_BIT', 6), ('15_BIT', 7), ('16_BIT', 8), ]), ('scbr', 8), ('dlybs', 8), ('dlybct', 8), ]), ], (0xe4, 'WPMR', common.wpmr(0x535049)), (0xe8, 'WPSR', common.wpsr), ]
('dmaen', 1), ('', 3), ('ropt', 1), ('', 19), ]), (0x54, 'CFG', [ ('fifomode', 1), ('', 3), ('ferrctrl', 1), ('', 3), ('hsmode', 1), ('', 3), ('lsync', 1), ('', 19), ]), (0xe4, 'WPMR', common.wpmr(0x4d4349)), (0xe8, 'WPSR', [ ('wp_vs', 4, [ ('NONE', 0), ('WRITE', 1), ('RESET', 2), ('BOTH', 3), ]), ('', 4), ('wp_vsrc', 16), ('', 8), ]), [ 256, 4, (0x0200, 'FIFO0'), ], ]
('dmaen', 1), ('', 3), ('ropt', 1), ('', 19), ]), (0x54, 'CFG', [ ('fifomode', 1), ('', 3), ('ferrctrl', 1), ('', 3), ('hsmode', 1), ('', 3), ('lsync', 1), ('', 19), ]), (0xe4, 'WPMR', common.wpmr(0x4d4349)), (0xe8, 'WPSR', [ ('wp_vs', 4, [ ('NONE', 0), ('WRITE', 1), ('RESET', 2), ('BOTH', 3), ]), ('', 4), ('wp_vsrc', 16), ('', 8), ]), [ 256, 4, (0x0200, 'FIFO0'),
(0x30, "RSHR", [("rsdat", 16), ("", 16)]), (0x34, "TSHR", [("tsdat", 16), ("", 16)]), (0x38, "RC0R", [("cp0", 16), ("", 16)]), (0x3C, "RC1R", [("cp1", 16), ("", 16)]), ( 0x40, "SR", [ ("txrdy", 1), ("txempty", 1), ("", 2), ("rxrdy", 1), ("ovrun", 1), ("", 2), ("cp0", 1), ("cp1", 1), ("txsyn", 1), ("rxsyn", 1), ("", 4), ("txen", 1), ("rxen", 1), ("", 14), ], ), (0x44, "IER", ssc_irqs), (0x48, "IDR", ssc_irqs), (0x4C, "IMR", ssc_irqs), (0xE4, "WPMR", common.wpmr(0x535343)), (0xE8, "WPSR", common.wpsr), ]