def exec_000(self, inst): rd = self.op_rd(inst) rs = self.op_rs(inst) svd = sign_ext(self.reg[rd]) svs = sign_ext(self.reg[rs]) uvd = w12(self.reg[rd]) uvs = w12(self.reg[rs]) if self.opcode_2(inst) == Consts.OP2_ADD: op = Opcode.ADD self.reg[rd] = mod_word_size(svd + svs) elif self.opcode_2(inst) == Consts.OP2_SUB: op = Opcode.SUB self.reg[rd] = mod_word_size(svd - svs) elif self.opcode_2(inst) == Consts.OP2_CMP: op = Opcode.CMP self.ZERO = (uvd == uvs) self.GT_SIGNED = (svd > svs) self.GT_UNSIGNED = (uvd > uvs) elif self.opcode_2(inst) == Consts.OP2_AND: op = Opcode.AND self.reg[rd] = mod_word_size(self.reg[rd] & self.reg[rs]) elif self.opcode_2(inst) == Consts.OP2_OR: op = Opcode.OR self.reg[rd] = mod_word_size(self.reg[rd] | self.reg[rs]) elif self.opcode_2(inst) == Consts.OP2_XOR: op = Opcode.XOR self.reg[rd] = mod_word_size(self.reg[rd] ^ self.reg[rs]) else: raise InstError(inst, "illegal instruction") self.str = '{0} %r{1}, %r{2}'.format(Consts.mnemonic[op], rd, rs)
def exec_001(self, inst): rd = self.op_rd(inst) rs = self.op_rs(inst) if self.opcode_2(inst) == Consts.OP2_SRL: op = Opcode.SRL self.reg[rd] = (self.reg[rs] >> 1) & 0b0111_1111_1111 elif self.opcode_2(inst) == Consts.OP2_SRA: op = Opcode.SRA msb = self.reg[rs] & 0b1000_0000_0000 self.reg[rd] = mod_word_size(self.reg[rs] >> 1) | msb elif self.opcode_2(inst) == Consts.OP2_SLL: op = Opcode.SLL self.reg[rd] = mod_word_size(self.reg[rs] << 1) elif self.opcode_2(inst) == Consts.OP2_NOT: op = Opcode.NOT self.reg[rd] = mod_word_size(self.reg[rs] ^ 0b1111_1111_1111) elif self.opcode_2(inst) == Consts.OP2_NEG: op = Opcode.NEG self.reg[rd] = mod_word_size(0b1_0000_0000_0000 - self.reg[rs]) elif self.opcode_2(inst) == Consts.OP2_MOVE: op = Opcode.MOVE self.reg[rd] = mod_word_size(self.reg[rs]) elif self.opcode_2(inst) == Consts.OP2_SEXT: op = Opcode.SEXT upper = 0b1111_1100_0000 if (self.reg[rs] & 0b10_0000) else 0 self.reg[rd] = upper | (self.reg[rs] & 0b11_1111) else: raise InstError(inst, "illegal instruction") self.str = '{0} %r{1}, %r{2}'.format(Consts.mnemonic[op], rd, rs)
def exec_011(self, inst): rd = self.op_rd(inst) imm = self.uimm3(inst) if self.opcode_2(inst) == Consts.OP2_INCR: op = Opcode.INCR self.reg[rd] = mod_word_size(self.reg[rd] + imm) self.str = '{0} %r{1}, {2}'.format(Consts.mnemonic[op], rd, imm) elif self.opcode_2(inst) == Consts.OP2_DECR: op = Opcode.DECR self.reg[rd] = mod_word_size(self.reg[rd] - imm) self.str = '{0} %r{1}, {2}'.format(Consts.mnemonic[op], rd, imm) elif self.opcode_2_6(inst) == Consts.OP2_RDPC: op = Opcode.RDPC self.reg[rd] = self.reg[Consts.PC] self.str = '{0} %r{1}'.format(Consts.mnemonic[op], rd) elif self.opcode_2_6(inst) == Consts.OP2_RET: op = Opcode.RET self.reg[Consts.NPC] = self.reg[rd] self.str = '{0} %r{1}'.format(Consts.mnemonic[op], rd) elif self.opcode_2_6(inst) == Consts.OP2_HALT: op = Opcode.HALT self.str = '{0}'.format(Consts.mnemonic[op]) raise Halt() else: raise InstError(inst, "illegal instruction")
def exec_010(self, inst): tgt = self.op_rd(inst) idx = self.op_rs(inst) addr = None if self.opcode_2(inst) == Consts.OP2_LDA: op = Opcode.LDA addr = self.reg[idx] self.reg[tgt] = self.mem[addr] self.str = '{0} %r{1}, [%r{2}]'.format(Consts.mnemonic[op], tgt, idx) elif self.opcode_2(inst) == Consts.OP2_LDP: op = Opcode.LDP addr = mod_word_size(self.reg[Consts.PC] + self.reg[idx]) self.reg[tgt] = self.mem[addr] self.str = '{0} %r{1}, [%r{2}]'.format(Consts.mnemonic[op], tgt, idx) elif self.opcode_2(inst) == Consts.OP2_STA: op = Opcode.STA addr = self.reg[tgt] self.mem[addr] = self.reg[idx] self.str = '{0} [%r{1}], %r{2}'.format(Consts.mnemonic[op], tgt, idx) elif self.opcode_2(inst) == Consts.OP2_STP: op = Opcode.STP addr = mod_word_size(self.reg[Consts.PC] + self.reg[tgt]) self.mem[addr] = self.reg[idx] self.str = '{0} [%r{1}], %r{2}'.format(Consts.mnemonic[op], tgt, idx) else: raise InstError(inst, "illegal instruction")
def exec_101(self, inst): rd = self.op_rd(inst) rs = self.op_rs(inst) npc = self.reg[Consts.NPC] self.reg[rd] = npc # return address if self.opcode_2(inst) == Consts.OP2_JALA: op = Opcode.JALA self.reg[Consts.NPC] = self.reg[rs] elif self.opcode_2(inst) == Consts.OP2_JALP: op = Opcode.JALP self.reg[Consts.NPC] = mod_word_size(npc + self.reg[rs]) else: raise InstError(inst, "illegal instruction") self.str = '{0} %r{1}, %r{2}'.format(Consts.mnemonic[op], rd, rs)
def exec_100(self, inst): cond = self.cond(inst) imm = self.simm6(inst) npc = self.reg[Consts.NPC] taken = 'F' if cond == Consts.COND_BAL: op = Opcode.BAL taken = 'T' self.reg[Consts.NPC] = mod_word_size(npc + imm) elif cond == Consts.COND_BZ: op = Opcode.BZ if self.ZERO: taken = 'T' self.reg[Consts.NPC] = mod_word_size(npc + imm) elif cond == Consts.COND_BNZ: op = Opcode.BNZ if not self.ZERO: taken = 'T' self.reg[Consts.NPC] = mod_word_size(npc + imm) elif cond == Consts.COND_BGT: op = Opcode.BGT if self.GT_SIGNED: taken = 'T' self.reg[Consts.NPC] = mod_word_size(npc + imm) elif cond == Consts.COND_BGE: op = Opcode.BGE if self.ZERO or self.GT_SIGNED: taken = 'T' self.reg[Consts.NPC] = mod_word_size(npc + imm) elif cond == Consts.COND_BGTU: op = Opcode.BGTU if self.GT_UNSIGNED: taken = 'T' self.reg[Consts.NPC] = mod_word_size(npc + imm) elif cond == Consts.COND_BGEU: op = Opcode.BGEU if self.ZERO or self.GT_UNSIGNED: taken = 'T' self.reg[Consts.NPC] = mod_word_size(npc + imm) else: raise InstError(inst, "illegal instruction") self.str = '{0} {1:#05x}: {2}'.format(Consts.mnemonic[op], imm, taken)
def parse(self, inst): key = self.opcode_1(inst) if key == 0b000: self.exec_000(inst) elif key == 0b001: self.exec_001(inst) elif key == 0b010: self.exec_010(inst) elif key == 0b011: self.exec_011(inst) elif key == 0b100: self.exec_100(inst) elif key == 0b101: self.exec_101(inst) elif key == 0b110: self.exec_110(inst) elif key == 0b111: self.exec_111(inst) else: raise InstError(bin(key), "illegal instruction")