def au_control():
client = ali_speech.NlsClient()
# 设置输出日志信息的级别：DEBUG、INFO、WARNING、ERROR
client.set_log_level('INFO')
appkey = '8qMtpb3T6XdGvxAt'
token = 'b502dcb93b96459199a485741d195d84'
sec=1
i=0
while (sec==1):
if_control = CAM.get()
if(if_control != 1):
continue
get_audio(in_path)
sentence_result=process(client, appkey, token)
if sentence_result =='':
sentence_result='错误'
#word_list=jieba_devide(sentence_result)
#cmd=find_cmd(word_list)
elif '小车' in sentence_result:
cmd = find_cmd(sentence_result)
print('onesense:')
print(cmd)
control(cmd)
# time.sleep(1)#具体延迟看stm32的反应速度
#在此处开始调用串口传递函数传参cmd
return 0
def __mul__(self, target):
"""
Function to multiply two propagator objects. For propagators
for the same bilinear control system, i.e. their
`self.hamiltonians` entries match, multiplication involves
appending the control functions to make a larger control.
"""
def H_check( h1, h2 ):
# Cleverly uses a method in the operator class to
# determine if Hamiltonians are identical.
return h1 == h2
try:
if H_check( self.hamiltonians , target.hamiltonians ):
# Hamiltonians match, append controls together
ctrl1 = target.ideal_control.control
ctrl2 = self.ideal_control.control
ctrl0 = vstack( (ctrl1, ctrl2) )
# Adjust time vectors. The second control should
# start just as the first one finishes.
t1 = target.times
t2 = self.times
# To avoid the control function from having two values
# at the same instant in time, we add an infinitesimal
# delay.
dt_min = 1E-10 * target.timemax()
t2 = (t2 - self.timemin() ) + target.timemax() + dt_min
t = vstack( (t1, t2) )
# Stack control and time vectors.
ARR = hstack( (ctrl0, t) )
else:
raise ValueError('Hamiltonians do not match. ' +\
'Multiplication is ill-defined.')
except AttributeError:
raise TypeError('Multiplication is only defined between ' +\
'propagator objects.')
if isinstance(target, imperfect.imperfect):
# Check if target is an imperfect propagator. If it is,
# we should default to returning an imperfect propagator.
return imperfect.imperfect( control.control(ARR) , \
self.hamiltonians, target.error )
else:
# Must be a normal propagator.
return propagator( control.control(ARR) , self.hamiltonians )
def __call__(self, time = None):
"""
"""
if time == None:
return self.solve()
elif time > self.timemax() or time < self.timemin():
raise ValueError('Time is not within interval bounds' + \
' ( %.2E , %.2E ).' %(self.timemin(), self.timemax() ))
try:
t = min( self.control.times[ self.control.times - time > 0 ] )
except ValueError:
# We must be at the higher time limit
t = time
index = self.times.tolist().index( t )
# Cut controls over interval (timemin, time)
arr = self.control.control[ 0:index+1 , : ]
times = self.times[ 0:index+1 ]
ARR = hstack( (arr,times) )
# Form new propagator
U = propagator( control.control( ARR ) )
# Solve propagator
return U.solve()
def __init__(self, period, serial_port, degrees_per_trigger, stop):
gr.basic_block.__init__(self,
name="turntable",
in_sig = [], # Input signature: 1 float at a time
out_sig = []) # Output signature: 1 float at a time
#register message ports
self.message_port_register_in(pmt.string_to_symbol("in"))
self.message_port_register_out(pmt.string_to_symbol("out"))
self.set_msg_handler(pmt.string_to_symbol("in"), self.msg_handler)
self.d_period = period
self.d_serial_port = serial_port
self.d_degrees_per_trigger = degrees_per_trigger
self.d_stop = stop
#accumulated angle
self.angle=0
#count up how many messages received
self.counter=0
print "Opening serial port: " + self.d_serial_port
if self.d_serial_port != "":
self.ttctrl = control.control(self.d_serial_port)
self.ttctrl.open()
def simulation():
data_path = "/Users/test/Uni/Masterarbeit/thesis_simulations/data"
burnup = '0.5MWd'
#burnup = '2MWd'
spent_fuel_fname = "SERPENT_outputs_NatU_percentages.npy"
spent_fuel_fname = os.path.join(data_path, spent_fuel_fname)
if burnup == '0.5MWd':
spent_rep_fuel_fname = "SERPENT_outputs_RepU_05MWd_percentages.npy"
elif burnup == '2MWd':
spent_rep_fuel_fname = "SERPENT_outputs_RepU_2MWd_percentages.npy"
spent_rep_fuel_fname = os.path.join(data_path, spent_rep_fuel_fname)
arch = archetypes.archetypes()
commod = commodity.commodity()
ctrl = control.control()
fac = facility.facility(burnup)
inst = institution.institution(burnup) # not needed but it should be
# called during the consistency
# check
recipes = recipe.recipe(spent_fuel=spent_fuel_fname,
spent_rep_fuel=spent_rep_fuel_fname,
burnup=burnup)
reg = region.region(burnup)
return {"simulation": {**arch, **commod, **ctrl, **fac, **recipes, **reg}}
def calculate():
if request.method == "POST":
text = ""
shift = ""
passPhrase = ""
id = request.form["id"]
text = request.form["text"]
shift = request.form["shift"]
passPhrase = request.form["passPhrase"]
ukw = request.form["ukw"]
walze1 = request.form["walze1"]
walze2 = request.form["walze2"]
walze3 = request.form["walze3"]
walzenPos = request.form["walzenPos"]
ringPosW1 = request.form["ringPosW1"]
ringPosW2 = request.form["ringPosW2"]
ringPosW3 = request.form["ringPosW3"]
steckerbrett = request.form["steckerbrett"]
erg = control.control(id, text, shift, passPhrase, ukw, walze1, walze2,
walze3, walzenPos, ringPosW1, ringPosW2,
ringPosW3, steckerbrett)
print(erg)
return render_template("result.html", erg=erg)
def shido ():
global control, digi, change, archivos
v0 = Tk()
v0.config(bg = "white")
v0.title('IDU-UM v1.20')
v0.geometry('700x500+290+150')
lock = thread.allocate_lock()
digi = alarmas_digitales.alarmas_digitales(v0)
change = cambio_alarmas.cambio_alarmas(v0)
control = control.control(v0)
archivos = Hora_archivos.win_archivos(v0)
pines =Frame(height = 260, width= 297, bg="black")
pines.place(x = 402, y = 172)
analogas = Frame(height=100, width=297, bg= "black")
analogas.place (x=402,y=399)
#***************************************************************
boton = Button(change, text="Aceptar" ,command = lambda : cambio_de_ala() ) # El boton que lo situo en el frame de cambio de alarma y ejecuta
boton.place(x=210,y=140) # el metodo de cambio de la alarma
bguardar = Button(archivos, text = "Guardar", command = lambda : archivos.salida())
bguardar.place(x=300, y = 35)
archivos.tick ()
thread.start_new_thread(digi.checando, ()) # Un metodo que se ejecuta al mismo tiempo que el de abajo # El otro metdo que se ejecuta con el de arriba
thread.start_new_thread(archivos.guardando, (digi.dar_val1, digi.dar_val2, digi.dar_val3, digi.dar_val4, digi.dar_val5, control.dar_estado))
print control.dar_estado()
v0.mainloop()
def __init__(self):
#extract info from xml
tree = ET.parse('config.xml')
root = tree.getroot()
#create control structure
self.Controls = []
ListOfControls = root.findall('control')
for iterator in ListOfControls:
try:
self.Controls.append(
controlhandler.control(iterator.attrib['name'],
int(iterator.attrib['setValue']),
int(iterator.attrib['value']),
int(iterator.attrib['minValue']),
int(iterator.attrib['maxValue']),
iterator.attrib['unit'],
int(iterator.attrib['MsgID']),
iterator.attrib['type']))
except:
sys.exit("Config import crashed. Check config.xml")
# create measurements structure
self.Measurements = []
ListOfMeasurements = root.findall('measurement')
for iterator in ListOfMeasurements:
try:
self.Measurements.append(
meashandler.measurement(iterator.attrib['name'],
int(iterator.attrib['value']),
int(iterator.attrib['minValue']),
int(iterator.attrib['maxValue']),
iterator.attrib['unit'],
int(iterator.attrib['MsgID'])))
except:
sys.exit("Config import crashed. Check config.xml")
# misc options
self.commsMethod = root.findall('communication')[0].attrib['method']
if self.commsMethod == "loopback":
logging.info("Communication disabled, Loopback only")
self.GUIUpdate = root.findall('GUIUpdate')[0].text
#logging options
root = root.findall('logging')
tempLogging = {}
for iterator in root:
tempLogging[iterator.attrib['name']] = iterator.attrib['value']
#tempLogging['cycletime']=int(tempLogging['cycletime'])
tempLogging['objList'] = []
for object in self.Controls:
tempLogging['objList'].append(object)
for object in self.Measurements:
tempLogging['objList'].append(object)
self.logging = tempLogging
def test_init_WhenCalledWithLocalHostAddress_SetsExpectedPropertiesOnCreatedClass(
self):
cfg = self.testConfigLocalControl1
c = control('test1', cfg)
self.assertEqual(int(cfg['controlpin']), c.controlpin)
self.assertEqual(cfg['name'], c.name)
self.assertEqual(cfg['host'], c.host)
self.assertEqual(False, c.reversed)
self.assertEqual(True, c.islocal)
def simulation():
arch = archetypes.archetypes()
commod = commodity.commodity()
ctrl = control.control()
fac = facility.facility()
recipes = recipe.recipe()
reg = region.region()
return {"simulation": {**arch, **commod, **ctrl, **fac, **recipes, **reg}}
def test_set_WhenCalledWithOnAndReversedStatus_SetsGPIOPinToZero(self):
with mock.patch('storage.redisclient.set') as mocked_redis, mock.patch(
'storage.redisclient.getasstring',
return_value='on') as mocked_redis_get, mock.patch(
'RPi.GPIO.output') as mocked_rpi:
cfg = self.testConfigLocalControl3
c = control('test1', cfg)
c.set('on')
mocked_redis.assert_called_with('test1', 'on')
mocked_rpi.assert_called_with(28, 0)
def reload(self):
cfg = config().get()
# print(cfg['tempsensors'])
for ts in cfg['tempsensors']:
self.sensors[ts] = sensors.temperaturesensor(
ts, cfg['tempsensors'][ts])
for ct in cfg['controls']:
self.controls[ct] = control(ct, cfg['controls'][ct])
def test_set_WhenCalledWithOffAndNonReversedNoStatusItemRemote_SetsRedisAndCallsURL(
self):
with mock.patch(
'storage.redisclient.set') as mocked_redis_set, mock.patch(
'request.getfromurl') as mocked_request:
cfg = self.testConfigRemoteControl1
c = control('test1', cfg)
c.set('off')
mocked_redis_set.assert_called_with('test1', 'off')
mocked_request.assert_called_with('http://' + cfg['host'] +
':5000/control/test1/off')
def update_control(self):
control(self.arm, self.clock, self.control_params)
self.arm.simulate()
self.ball.simulate()
if self.render == RENDER_RATE:
self.update()
self.render = 1
self.render += 1
self.clock += DT
self.spline_log_file.write(
str(self.arm.links[1].theta) + ', ' +
str(self.arm.links[2].theta) + ', ' +
str(self.arm.links[3].theta) + ', ' +
str(self.arm.links[1].theta_dot) + ', ' +
str(self.arm.links[2].theta_dot) + ', ' +
str(self.arm.links[3].theta_dot) + ', ' +
str(self.arm.links[1].torque) + ', ' +
str(self.arm.links[2].torque) + ', ' +
str(self.arm.links[3].torque) + '\n')
self.ball_pos_log_file.write(
str(self.ball.position[X]) + ', ' + str(self.ball.position[Y]) +
'\n')
if (self.arm.release and np.abs(self.ball.position[Y]) < 0.001):
with open(SAMPLE_RESULT_PATH, 'a') as f:
while True:
try:
fcntl.flock(f, fcntl.LOCK_EX)
#print('I have lock {}'.format(self.sim_id))
f.write('{}, {}\n'.format(self.sim_id,
self.ball.position[X]))
fcntl.flock(f, fcntl.LOCK_UN)
f.close()
break
except IOError as e:
# raise on unrelated IOErrors
if e.errno != errno.EAGAIN:
raise 'couldnt open file'
else:
time.sleep(0.1)
exit(0)
def startTunnel(self, autoport=None):
from control import control
import random
if not autoport:
autoport = random.randint(20000, 60000)
self.callPerl("-tunnel %d tcp autoclose" % autoport)
self.tunnel = control(int(autoport))
self.tunnel.main()
def __init__(self,
rate=16000,
frames_size=None,
channels=None,
device_index=None):
'''
录音类初始化
:param rate:采样率
:param frames_size:数据帧大小
:param channels:通道数
:param device_index:录音设备id
'''
self.sample_rate = rate
self.frames_size = frames_size if frames_size else rate / 100
self.channels = channels if channels else 1
self.pyaudio_instance = pyaudio.PyAudio()
self.record = False
self.recorddata = []
self.ctl = control.control()
if device_index is None:
if channels:
for i in range(self.pyaudio_instance.get_device_count()):
dev = self.pyaudio_instance.get_device_info_by_index(i)
name = dev['name'].encode('utf-8')
logger.info('{}:{} with {} input channels'.format(
i, name, dev['maxInputChannels']))
if dev['maxInputChannels'] == channels:
logger.info('Use {}'.format(name))
device_index = i
break
else:
device_index = self.pyaudio_instance.get_default_input_device_info(
)['index']
if device_index is None:
raise Exception(
'Can not find an input device with {} channel(s)'.format(
channels))
self.stream = self.pyaudio_instance.open(
start=False,
format=pyaudio.paInt16,
input_device_index=device_index,
channels=self.channels,
rate=int(self.sample_rate),
frames_per_buffer=int(self.frames_size),
stream_callback=self.__callback,
input=True)
self.sinks = []
def __init__(self, node_id, channel_map):
gr.basic_block.__init__(self,
name="rrrm",
in_sig=[],
out_sig=[])
self.message_port_register_in(pmt.intern('payload_in'))
self.message_port_register_out(pmt.intern('payload_out'))
self.message_port_register_in(pmt.intern('radar_in'))
self.message_port_register_in(pmt.intern('rrrm_in'))
self.message_port_register_out(pmt.intern('rrrm_out'))
self.message_port_register_out(pmt.intern('antenna_out'))
self.set_msg_handler(pmt.intern('payload_in'), self.handle_payload_message)
self.set_msg_handler(pmt.intern('rrrm_in'), self.handle_rrrm_message)
self.set_msg_handler(pmt.intern('radar_in'), self.handle_radar_message)
self.channel_map = channel_map
self.node_id = node_id
self.state = self.STATE_FORWARD_PAYLOAD
self.curr_channel_id = 0
self.next_channel_id = 0
self.next_channel_pos = 0
self.thread_lock = threading.Lock()
self.switch_ack_thread = None
self.switch_ack_received = False
self.last_ping_time = 0
self.last_message_tx_time = 0
self.log_file = open('/home/inets/Documents/Log/rrrm_log.txt','w+')
self.ping_frequency = 100 #10ms between PINGs
self.max_message_timeout = 0.05
if HAS_TURNTABLE:
try:
self.antenna_control = control.control("/dev/ttyACM0")
self.antenna_control.open()
self.antenna_control.move_to(self.channel_map[0])
except:
self.antenna_control = None
print 'could not open serial port'
self.run_threads = True
self.ping_thread = threading.Thread(target=self.do_send_ping)
self.ping_thread.daemon = True
self.ping_thread.start()
self.ping_monitor_thread = threading.Thread(target=self.do_check_ping)
self.ping_monitor_thread.daemon = True
self.ping_monitor_thread.start()
def test_set_WhenCalledWithOffAndNonReversedNoStatusItem_SetsGPIOPinToZeroAndStatusPinToZero(
self):
with mock.patch(
'storage.redisclient.set') as mocked_redis_set, mock.patch(
'storage.redisclient.getasstring',
return_value='off') as mocked_redis_get, mock.patch(
'RPi.GPIO.output') as mocked_rpi:
cfg = self.testConfigLocalControl2
c = control('test1', cfg)
c.set('off')
mocked_redis_set.assert_called_with('test1', 'off')
mocked_rpi.assert_any_call(28, 0)
mocked_rpi.assert_any_call(14, 0)
def startTunnel(self, autoport=None):
from control import control
import random
if not autoport:
autoport = random.randint(20000,60000)
self.callPerl("-tunnel %d tcp autoclose" % autoport)
self.tunnel = control(int(autoport))
self.tunnel.main()
def fuse(self, gyro_q, mag_normal, acc):
self.mag_acc_fusion_obj.fuse(mag_normal, acc)
if self.q is None:
self.gyro_init_q = gyro_q
self.adjust_q = self.mag_acc_fusion_obj.q
self.gyro_diff_q = quaternion.diff(self.gyro_init_q, gyro_q)
new_q = quaternion.multiply(self.adjust_q, self.gyro_diff_q)
diff_q = quaternion.diff(new_q, self.mag_acc_fusion_obj.q)
diff_q = quaternion.standardize(diff_q)
step_adj_q = quaternion.scale(diff_q,
self.mag_acc_fusion_obj.quality / 20.0)
self.adjust_q = quaternion.multiply(step_adj_q, self.adjust_q)
self.q = quaternion.multiply(self.adjust_q, self.gyro_diff_q)
control.control(self.q)
def rf(self):
self.stage = self.get_stage()
self.stage.set_size(WIDTH,HEIGHT)
self.stage.set_color(BLACK_BG)
self.stage.connect('key-press-event', self.parseKeyPress)
self.index_cover_selected = 2
self.cover = cover.cover(self)
self.fx = fx_default.fx(self)
self.fx.init_fx(self, self.get_covers(), self.get_index_cover_selected())
self.scrollbar = scrollbar.scrollbar(self)
self.scrollbar.init_scrollbar(self, self.get_index_cover_selected(), self.get_size_covers())
self.control = control.control(self)
self.show()
def setMaze(self):
self.maze = mz.Maze(self.rowMax, self.colMax)
self.maze.Run()
# self.maze.Display()
while True:
self.row, self.col = self.generateNode()
self.rowDest, self.colDest = self.generateNode()
if self.row != self.rowDest or self.col != self.colDest:
break
self.cl = ctrl.control(self.row, self.col, self.maze.map)
self.isGoal = False
def __init__(self, node_id, channel_map):
gr.basic_block.__init__(self, name="rrrm", in_sig=[], out_sig=[])
self.message_port_register_in(pmt.intern('payload_in'))
self.message_port_register_out(pmt.intern('payload_out'))
self.message_port_register_in(pmt.intern('radar_in'))
self.message_port_register_in(pmt.intern('rrrm_in'))
self.message_port_register_out(pmt.intern('rrrm_out'))
self.message_port_register_out(pmt.intern('antenna_out'))
self.set_msg_handler(pmt.intern('payload_in'),
self.handle_payload_message)
self.set_msg_handler(pmt.intern('rrrm_in'), self.handle_rrrm_message)
self.set_msg_handler(pmt.intern('radar_in'), self.handle_radar_message)
self.channel_map = channel_map
self.node_id = node_id
self.state = self.STATE_FORWARD_PAYLOAD
self.curr_channel_id = 0
self.next_channel_id = 0
self.next_channel_pos = 0
self.thread_lock = threading.Lock()
self.switch_ack_thread = None
self.switch_ack_received = False
self.last_ping_time = 0
self.last_message_tx_time = 0
self.log_file = open('/home/inets/Documents/Log/rrrm_log.txt', 'w+')
self.ping_frequency = 100 #10ms between PINGs
self.max_message_timeout = 0.05
if HAS_TURNTABLE:
try:
self.antenna_control = control.control("/dev/ttyACM0")
self.antenna_control.open()
self.antenna_control.move_to(self.channel_map[0])
except:
self.antenna_control = None
print 'could not open serial port'
self.run_threads = True
self.ping_thread = threading.Thread(target=self.do_send_ping)
self.ping_thread.daemon = True
self.ping_thread.start()
self.ping_monitor_thread = threading.Thread(target=self.do_check_ping)
self.ping_monitor_thread.daemon = True
self.ping_monitor_thread.start()
def __init__(self, cb=None):
self.RANGE = range(8)
self.EGNAR = range(7,-1,-1)
self.RANGE3 = range(3)
self.RANGE16 = range(16)
self.EGNAR16 = range(15,-1,-1)
self.PAUSE = True
self.NOSTEP = False
self.RUN = True
self.ALU = alu()
self.REGISTER = register()
self.CONTROL = control()
self.DATABUS = [0,0,0,0,0,0,0,0]
self.ADDRESSBUS = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
self.MEMORY = memory()
self.CALLBACK = cb
self.CONTROLREGISTER = [0,0,0] # Cy, Z, S
self.Inst = [0,0,0,0,0,0,0,0]
self.regLoadMap = { (0,0,0) : self.loadA, \
(0,0,1) : self.loadB, \
(0,1,0) : self.loadC, \
(0,1,1) : self.loadD, \
(1,0,0) : self.loadM1, \
(1,0,1) : self.loadM2, \
(1,1,0) : self.loadX, \
(1,1,1) : self.loadY }
self.regSelectMap = { (0,0,0) : self.selectA, \
(0,0,1) : self.selectB, \
(0,1,0) : self.selectC, \
(0,1,1) : self.selectD, \
(1,0,0) : self.selectM1, \
(1,0,1) : self.selectM2, \
(1,1,0) : self.selectX, \
(1,1,1) : self.selectY }
self.start = time()
self.H = ""
self.M = ""
self.S = ""
self.ENCODER = encodercore()
def __init__(self):
APP = "vista_ipm"
DIR = "locale"
gettext.textdomain(APP)
gettext.bindtextdomain(APP, DIR)
locale.textdomain(APP)
locale.bindtextdomain(APP, DIR)
locale.setlocale(locale.LC_ALL, '')
_ = gettext.gettext
builder = Gtk.Builder()
builder.add_from_file("interfaz3.glade")
builder.connect_signals(self)
self.mod = modelo.modelo()
self.cont = control.control(builder)
self.cont.init_builder()
self.cont.init_app(self)
def __init__(self, node_id, channel_map):
gr.basic_block.__init__(self, name="rrrm", in_sig=[], out_sig=[])
self.message_port_register_in(pmt.intern("payload_in"))
self.message_port_register_out(pmt.intern("payload_out"))
self.message_port_register_in(pmt.intern("radar_in"))
self.message_port_register_in(pmt.intern("rrrm_in"))
self.message_port_register_out(pmt.intern("rrrm_out"))
self.message_port_register_out(pmt.intern("antenna_out"))
self.set_msg_handler(pmt.intern("payload_in"), self.handle_payload_message)
self.set_msg_handler(pmt.intern("rrrm_in"), self.handle_rrrm_message)
self.set_msg_handler(pmt.intern("radar_in"), self.handle_radar_message)
self.channel_map = channel_map
self.node_id = node_id
self.state = self.STATE_FORWARD_PAYLOAD
self.curr_channel_id = 0
self.next_channel_id = 0
self.next_channel_pos = 0
self.thread_lock = threading.Lock()
self.switch_ack_thread = None
self.switch_ack_received = False
self.last_ping_time = 0
self.last_message_tx_time = 0
self.log_file = open("rrrm_log.txt", "w")
self.ping_frequency = 100
self.max_message_timeout = 0.05
if HAS_TURNTABLE:
try:
self.antenna_control = control.control("/dev/ttyACM0")
self.antenna_control.open()
except:
self.antenna_control = None
print "could not open serial port"
self.ping_thread = threading.Thread(target=self.do_send_ping)
# self.ping_thread.daemon = True
self.ping_thread.start()
self.ping_monitor_thread = threading.Thread(target=self.do_check_ping)
# self.ping_monitor_thread.daemon = True
self.ping_monitor_thread.start()
def __init__(self,logDir = '',SIL=True,port='COM4',Kp=0.0,Kd=0.0,Ki=0.0,dw_interface=False,dw_radius=0.0,dw_angle=0.0,turnThrottle=0.3,cruiseThrottle=0.6):
# make log folder based on date/time
foldername=logDir
## state object from xbee_bridge_state
self.state = xbee_bridge_state(logDir=foldername)
## start time - used to reduce all times to something more convenient for floats
self.tStart = time.time()
## time at which to trigger 1Hz loop
self.time_1Hz = 0.0
## time at which to trigger 10 Hz loop
self.time_10Hz = 0.0
## time at which to trigger 50 Hz loop
self.time_50Hz = 0.0
## dw_interface: boolean, set to True to enable the debugging interface
self.dw_interface = dw_interface
## dw_radius: range at which to create synthetic waypoints as float in meters
self.dw_radius = dw_radius
## dw_angle: relative angle to synthetic waypoints as a float in radians, positive is to the right
self.dw_angle = dw_angle
## synthetic waypoint object used in debugging
self.syntheticWaypoint = synthetic_waypoint(logDir=foldername)
## joystick interface class
self.joy = joystick.joystick(dw_interface)
## hardware_interface class object with default SIL arguments
self.xbee = hardware_interface.hardware_interface(port=port,SIL=SIL,groundstation=True)
self.xbee.start()
## (boolean) set to True when we get a new GPS message
self.new_data = False
## buffer of bytes to write to XBee; clear whenever written
self.txBuffer = bytes()
## Object for interprocess communications
self.ipc = ipcPacker.nanomsgTalker()
## control object for computing control
self.control = control.control(logDir=foldername,Kp=Kp,Kd=Kd,Ki=Ki,turnThrottle=turnThrottle,cruiseThrottle=cruiseThrottle)
## parser object for the serial protocol. Pass the log folder to create message logs
self.espParser = esp.espParser(logdir=foldername)
## GPS log file
self.gpsLog = open(foldername+'gpslog.csv','w')
self.gpsLog.write('systime,t,lon,lat,v,hdg,status\n')
## Control (received) log file
self.controlLog = open(foldername+'controlLog.csv','w')
self.controlLog.write('systime,rudd,thro\n')
## Control (transmitted) log file
self.controlOutLog = open(foldername+'controlOutLog.csv','w')
self.controlOutLog.write('systime,rudd,thro\n')
def run(time_out=10., epochs=1):
random.seed()
tau = 0.001
#if os.path.isfile('q_tab.dat'): Q = get_q_tab()
#else:
#Q = monte.init_Q(time_out/tau)
for ep in range(epochs):
if ep % 1000 == 0: print "episodes:", ep
## initial conditions
x = 0.
dx = 0.
a = random.uniform(-0.1, 0.1)
#da = random.uniform(-0.1, 0.1)
da = 0.
ia = 0.
t = 0.
log = []
print "C:", C
while t < time_out:
t += tau
v = v_target(t)
u = control.control(dx, a, da, ia, v)
#u = monte.get_policy(state,Q)
x, dx, a, da = get_next_values(x, dx, a, da, u, tau)
ia += a * tau
print "x:", x
log.append((t, dx, a, v, u))
#next_state = monte.get_state(dx,a,da) #,v_target)
if abs(a) > 0.7:
reward = -100.
#Q = monte.learn(state,u,next_state,reward,Q)
break
else:
#reward = rl.get_reward(state,next_state,u)
#Q = rl.learn(state,u,next_state,reward,Q)
#state = next_state
pass
show(log)
def __init__(self):
# builder.add_from_file('cgsi/add_obj_window.glade')
# builder.add_from_file('cgsi/obj_right_click_menu.glade')
# builder.add_from_file('cgsi/modification_dialog.glade')
self.builder = Gtk.Builder()
self.builder.add_from_file('cgsi/cgsi_1.glade')
self.add_object_window = self.builder.get_object('add_obj_window')
self.modification_dialog = self.builder.get_object('modification_dialog')
self.main_window = self.builder.get_object('application_window')
self.warning_dialog = self.builder.get_object('warning_dialog')
self.step_item = self.builder.get_object('step_item')
self.drawing_area = self.builder.get_object('viewport')
self.list = self.builder.get_object('object_list')
self.tree_view = self.builder.get_object('tree_view_object_list')
self.file_chooser_window = self.builder.get_object('file_chooser')
self.import_file_chooser_window = self.builder.get_object('import_file_chooser')
self.builder.connect_signals(self)
self.main_window.connect('destroy', Gtk.main_quit)
# init do controle
# self.control = control.control(drawing_area, context)
self.control = ct.control()
self.control.calculate_ppc()
self.control.create_shape("start 1", "Poligono", [ [200, 200],[300, 200], [300, 300], [200,300]])
self.list.append(["start 1", "Poligono"])
self.control.create_shape("start 2", "Poligono", [ [100, 200],[150, 200], [150, 250], [100,250]])
self.list.append(["start 2", "Poligono"])
self.control.create_shape("start 3", "Linha", [ [10, 10],[50, 50] ])
self.list.append(["start 3", "Linha"])
self.control.scale_object("start 1", 2, 1)
self.control.rotate_object("start 1", 90, trans.ROTATE_AROUND_SELF)
# self.control.rotate_window(-45)
self.main_window.show()
def dlx(clk_period=1, Reset=Signal(intbv(0)[1:]), Zero=Signal(intbv(0)[1:])):
"""
5级流水线DLX处理器
=======================================
Stages
------
+------------------+
| +------- Hazard
| | +-> Detect <-----+
| | | | |
| | | | |
v v | v |
[IF] -> IF/ID -> [ID] -> ID/EX -> [EX] -> EX/MEM -> [MEM] -> MEM/WB __
^ | ^ | | |
| | | <_____________| | |
| +> FORW <___________________________| |
| |
|_______________________________________________________|
约定:
------------
* 信号用驼峰命名法
* 实例用匈牙利命名法
* 为区分在两个及以上阶段使用的信号，增加了后缀。
例如：'PcAdderO_if' 在 IF阶段，PcAdderO_id 在ID阶段
"""
##############################
# clock settings
##############################
# 时钟信号
Clk = Signal(intbv(0)[1:])
ClkPc = Signal(intbv(0)[1:])
clk_driver = clock_driver(Clk, clk_period)
clk_driver_pc = clock_driver(ClkPc, clk_period * 4)
####################
#feedback Signals
######################
# signals from and advanced stage which feeds a previous component
BranchAdderO_mem = Signal(intbv(0, min=MIN, max=MAX)[32:])
# IF级中控制PC的多路选择器的信号（branch or immediate）
PCSrc_mem = Signal(intbv(0)[1:])
# 当分支指令时为1
FlushOnBranch = PCSrc_mem
# MuxMemO_wb 数据的寄存器写入指针
WrRegDest_wb = Signal(intbv(0)[32:])
# WB输出的数据
MuxMemO_wb = Signal(intbv(0, min=MIN, max=MAX))
RegWrite_wb = Signal(intbv(0)[1:])
# Forwarding 单元中生成的信号，控制输入至ALU的多路选择器
ForwardA, ForwardB = [Signal(intbv(0)[2:]) for i in range(2)]
AluResult_mem = Signal(intbv(0, min=MIN, max=MAX))
# 判断流水线是否阻塞，该信号会使PC冻结，并把所有控制信号置零
Stall = Signal(intbv(0)[1:])
##############################
# IF
##############################
#instruction memory
# 连接PC 和 Instruction Memory
Ip = Signal(intbv(0)[32:])
Instruction_if = Signal(intbv(0)[32:])
im = instruction_memory(Ip, Instruction_if)
#PC
# 输出至branch多路选择器，pc的输入
NextIp = Signal(intbv(0)[32:])
pc = program_counter(Clk, NextIp, Ip, Stall)
#pc_adder
# 这里的1代表1条指令，即4字节
INCREMENT = 1
# pc_addr 的输出，branch_adder and mux_branch的输入
PcAdderOut_if = Signal(intbv(0)[32:])
#复用ALU实现PC + 4
pc_adder = ALU(Signal(0b0010), Ip, Signal(INCREMENT), PcAdderOut_if,
Signal(0))
#控制下条指令还是分支指令
mux_pc_source = mux2(PCSrc_mem, NextIp, PcAdderOut_if, BranchAdderO_mem)
##############################
# IF/ID
##############################
PcAdderOut_id = Signal(intbv(0)[32:])
Instruction_id = Signal(intbv(0)[32:])
latch_if_id_ = latch_if_id(Clk, FlushOnBranch, Instruction_if,
PcAdderOut_if, Instruction_id, PcAdderOut_id,
Stall)
##############################
# ID
##############################
#DECODER
Opcode_id = Signal(intbv(0)[6:]) #instruction 31:26
Rs_id = Signal(intbv(0)[5:]) #instruction 25:21
Rt_id = Signal(intbv(0)[5:]) #instruction 20:16
Rd_id = Signal(intbv(0)[5:]) #instruction 15:11
Shamt_id = Signal(intbv(0)[5:]) #instruction 10:6
Func_id = Signal(intbv(0)[6:]) #instruction 5:0
Address16_id = Signal(intbv(0, min=-(2**15),
max=2**15 - 1)) #instruction 15:0
NopSignal = Signal(intbv(0)[1:])
instruction_decoder_ = instruction_dec(Instruction_id, Opcode_id, Rs_id,
Rt_id, Rd_id, Shamt_id, Func_id,
Address16_id, NopSignal)
#sign extend
Address32_id = Signal(intbv(0, min=MIN, max=MAX))
sign_extend_ = sign_extend(Address16_id, Address32_id)
#CONTROL
signals_1bit = [Signal(intbv(0)[1:]) for i in range(7)]
RegDst_id, ALUSrc_id, MemtoReg_id, RegWrite_id, MemRead_id, MemWrite_id, Branch_id = signals_1bit
ALUop_id = Signal(intbv(0)[2:])
control_ = control(Opcode_id, RegDst_id, Branch_id, MemRead_id,
MemtoReg_id, ALUop_id, MemWrite_id, ALUSrc_id,
RegWrite_id, NopSignal, Stall)
#REGISTER FILE
Data1_id = Signal(intbv(0, min=MIN, max=MAX))
Data2_id = Signal(intbv(0, min=MIN, max=MAX))
register_file_i = register_file(Clk,
Rs_id,
Rt_id,
WrRegDest_wb,
MuxMemO_wb,
RegWrite_wb,
Data1_id,
Data2_id,
depth=32)
##############################
# ID/EX
##############################
PcAdderOut_ex = Signal(intbv(0)[32:])
signals_1bit = [Signal(intbv(0)[1:]) for i in range(7)]
RegDst_ex, ALUSrc_ex, MemtoReg_ex, RegWrite_ex, MemRead_ex, MemWrite_ex, Branch_ex = signals_1bit
ALUop_ex = Signal(intbv(0)[2:])
Data1_ex = Signal(intbv(0, min=MIN, max=MAX))
Data2_ex = Signal(intbv(0, min=MIN, max=MAX))
Rs_ex = Signal(intbv(0)[5:]) #instruction 25:21
Rt_ex = Signal(intbv(0)[5:]) #instruction 20:16
Rd_ex = Signal(intbv(0)[5:]) #instruction 15:11
#Shamt_ex = Signal(intbv(0)[5:]) #instruction 10:6
Func_ex = Signal(intbv(0)[6:]) #instruction 5:0
Address32_ex = Signal(intbv(0, min=MIN, max=MAX))
latch_id_ex_ = latch_id_ex(
Clk,
FlushOnBranch,
PcAdderOut_id,
Data1_id,
Data2_id,
Address32_id,
Rs_id,
Rt_id,
Rd_id,
Func_id,
RegDst_id,
ALUop_id,
ALUSrc_id, #去到 EX 的信号
Branch_id,
MemRead_id,
MemWrite_id, #去到 MEM 的信号
RegWrite_id,
MemtoReg_id, #去到 WB 的信号
PcAdderOut_ex,
Data1_ex,
Data2_ex,
Address32_ex,
Rs_ex,
Rt_ex,
Rd_ex,
Func_ex,
RegDst_ex,
ALUop_ex,
ALUSrc_ex, #去到 EX 的信号
Branch_ex,
MemRead_ex,
MemWrite_ex, #去到 MEM 的信号
RegWrite_ex,
MemtoReg_ex #去到 WB 的信号
)
##############################
# EX
##############################
BranchAdderO_ex = Signal(intbv(0, min=MIN, max=MAX)[32:])
Zero_ex = Signal(intbv(0)[1:])
AluResult_ex = Signal(intbv(0, min=MIN, max=MAX))
ForwMux1Out, ForwMux2Out = [
Signal(intbv(0, min=MIN, max=MAX)) for i in range(2)
]
MuxAluDataSrc_ex = Signal(intbv(0, min=MIN, max=MAX))
WrRegDest_ex = Signal(intbv(0)[32:])
forw_mux1_ = mux4(ForwardA, ForwMux1Out, Data1_ex, MuxMemO_wb,
AluResult_mem)
forw_mux2_ = mux4(ForwardB, ForwMux2Out, Data2_ex, MuxMemO_wb,
AluResult_mem)
mux_alu_src = mux2(ALUSrc_ex, MuxAluDataSrc_ex, ForwMux2Out, Address32_ex)
#Branch adder
branch_adder_ = ALU(Signal(0b0010), PcAdderOut_ex, Address32_ex,
BranchAdderO_ex, Signal(0))
#ALU Control
AluControl = Signal(intbv('1111')[4:]) #control signal to alu
alu_control_ = alu_control(ALUop_ex, Func_ex, AluControl)
#ALU
alu_ = ALU(AluControl, ForwMux1Out, MuxAluDataSrc_ex, AluResult_ex,
Zero_ex)
#控制写入寄存器是rt或rd
mux_wreg = mux2(RegDst_ex, WrRegDest_ex, Rt_ex, Rd_ex)
##############################
# EX/MEM
##############################
BranchAdderO_mem = Signal(intbv(0, min=MIN, max=MAX))
Zero_mem = Signal(intbv(0)[1:])
Data2_mem = Signal(intbv(0, min=MIN, max=MAX))
WrRegDest_mem = Signal(intbv(0)[32:])
#control signals
signals_1bit = [Signal(intbv(0)[1:]) for i in range(5)]
MemtoReg_mem, RegWrite_mem, MemRead_mem, MemWrite_mem, Branch_mem = signals_1bit
latch_ex_mem_ = latch_ex_mem(
Clk,
Reset,
BranchAdderO_ex,
AluResult_ex,
Zero_ex,
Data2_ex,
WrRegDest_ex,
Branch_ex,
MemRead_ex,
MemWrite_ex, #去到 MEM 的信号
RegWrite_ex,
MemtoReg_ex, #去到 WB 的信号
BranchAdderO_mem,
AluResult_mem,
Zero_mem,
Data2_mem,
WrRegDest_mem,
Branch_mem,
MemRead_mem,
MemWrite_mem, #去到 MEM 的信号
RegWrite_mem,
MemtoReg_mem, #去到 WB 的信号
)
##############################
# MEM
##############################
DataMemOut_mem = Signal(intbv(0, min=MIN, max=MAX))
#branch AND gate
branch_and_gate = and_gate(Branch_mem, Zero_mem, PCSrc_mem)
#data memory
data_memory_ = data_memory(Clk, AluResult_mem, Data2_mem, DataMemOut_mem,
MemRead_mem, MemWrite_mem)
##############################
# EX/WB
##############################
#RegWrite_wb, on feedback signals section
MemtoReg_wb = Signal(intbv(0)[1:])
DataMemOut_wb = Signal(intbv(0, min=MIN, max=MAX))
AluResult_wb = Signal(intbv(0, min=MIN, max=MAX))
#WrRegDest_wb on feedback signals sections.
latch_mem_wb_ = latch_mem_wb(
Clk,
Reset,
DataMemOut_mem,
AluResult_mem,
WrRegDest_mem,
RegWrite_mem,
MemtoReg_mem, #去到 WB 的信号
DataMemOut_wb,
AluResult_wb,
WrRegDest_wb,
RegWrite_wb,
MemtoReg_wb, #去到 WB 的信号
)
##############################
# WB
##############################
#mux2(sel, mux_out, chan1, chan2):
mux_mem2reg_ = mux2(MemtoReg_wb, MuxMemO_wb, AluResult_wb, DataMemOut_wb)
##############################
# Forwarding unit
##############################
forwarding_ = forwarding(
RegWrite_mem,
WrRegDest_mem,
Rs_ex,
Rt_ex, #inputs of EX hazards
RegWrite_wb,
WrRegDest_wb, #left inputs of MEM hazards
ForwardA,
ForwardB)
##############################
# hazard detection unit
##############################
hazard_detector_ = hazard_detector(MemRead_ex, Rt_ex, Rs_id, Rt_id, Stall)
if DEBUG:
@always(Clk.posedge)
def debug_internals():
sep = "\n" + "=" * 31 + " cycle %i (%ins)" + "=" * 31
print(sep % (int(now() / 2.0 + 0.5), now()))
#IF
print("\n" + "." * 35 + " IF " + "." * 35 + "\n")
print(
"PcAdderOut_if %i | BranchAdderO_mem %i | PCSrc_mem %i | NextIp %i | Ip %i"
% (PcAdderOut_if, BranchAdderO_mem, PCSrc_mem, NextIp, Ip))
print('Instruction_if %s (%i)' %
(bin(Instruction_if, 32), Instruction_if))
if True: # now () > 2:
#ID
print("\n" + "." * 35 + " ID " + "." * 35 + "\n")
print("PcAdderO_id %i | Instruction_id %s (%i) | Nop %i" %
(PcAdderOut_id, bin(Instruction_id,
32), Instruction_id, NopSignal))
print( 'Op %s | Rs %i | Rt %i | Rd %i | Func %i | Addr16 %i | Addr32 %i' % \
(bin(Opcode_id, 6), Rs_id, Rt_id, Rd_id, Func_id, Address16_id, Address32_id ))
print('Data1 %i | Data2 %i' % (Data1_id, Data2_id))
print('-->CONTROL')
print( 'RegDst %i ALUop %s ALUSrc %i | Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
( RegDst_id , bin(ALUop_id, 2), ALUSrc_id, Branch_id, MemRead_id, MemWrite_id, RegWrite_id, MemtoReg_id))
print('Stall --> %i' % Stall)
if True: #if now () > 4:
#EX
print("\n" + "." * 35 + " EX " + "." * 35 + "\n")
print("PcAdderO_ex %i | BranchAdderO_ex %i " %
(PcAdderOut_ex, BranchAdderO_ex))
print("Rs %i | Rt %i | Rd %i | Func %i | Addr32 %i" %
(Rs_ex, Rt_ex, Rd_ex, Func_ex, Address32_ex))
print('Data1_ex %i | Data2_ex %i' % (Data1_ex, Data2_ex))
print('ForwardA %i | ForwardB %i' % (ForwardA, ForwardB))
print('ForwMux1Out %i | ForwMux2Out %i' %
(ForwMux1Out, ForwMux2Out))
print('-->CONTROL')
print( 'RegDst %i ALUop %s ALUSrc %i | Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
( RegDst_ex , bin(ALUop_ex, 2), ALUSrc_ex, Branch_ex, MemRead_ex, MemWrite_ex, RegWrite_ex, MemtoReg_ex))
print('--> ALU')
print(
'MuxAluDataSrc %i | AluCtrl %s | AluResult_ex %i | Zero_ex %i'
% (MuxAluDataSrc_ex, bin(AluControl,
4), AluResult_ex, Zero_ex))
print('WrRegDest_ex %i' % WrRegDest_ex)
if True: #if now () > 6:
#MEM
print("\n" + "." * 35 + "MEM " + "." * 35 + "\n")
print("BranchAdderO_mem %i " % (BranchAdderO_mem))
print('-->CONTROL')
print( 'Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
( Branch_mem, MemRead_mem, MemWrite_mem, RegWrite_mem, MemtoReg_mem))
print('--> Branch')
print('Branch_mem %i Zero %i | PCSrc_mem %i' %
(Branch_mem, Zero_mem, PCSrc_mem))
print('--> Data mem')
print( 'AluResult_mem %i | Data2_mem %i | DataMemOut_mem %i | MemW %i MemR %i' \
% (AluResult_mem, Data2_mem, DataMemOut_mem, MemWrite_mem, MemRead_mem))
print('WrRegDest_mem %i' % WrRegDest_mem)
if True: #if now() > 8:
#WB
print("\n" + "." * 35 + "WB" + "." * 35 + "\n")
print('CONTROL --> RegW %i Mem2Reg %i ' %
(RegWrite_mem, MemtoReg_mem))
print('DataMemOut_wb %i | AluResult_wb %i | MuxMemO_wb %i ' %
(DataMemOut_wb, AluResult_wb, MuxMemO_wb))
print('WrRegDest_wb %i | MuxMemO_wb %i' %
(WrRegDest_wb, MuxMemO_wb))
return instances()
def smooth(y, box_pts):
return gaussian_filter1d(y, box_pts)
if len(y) < box_pts:
return np.nan
box = np.ones(box_pts) / box_pts
y_smooth = np.convolve(y, box, mode='same')
return y_smooth
if __name__ == "__main__":
# import matplotlib
# matplotlib.use('Agg')
# matplotlib.get_backend()
minerva = control.control('control.ini', '/home/minerva/minerva-control')
plotweather(minerva)
sys.exit()
ipdb.set_trace()
today = 'n' + datetime.datetime.utcnow().strftime('%Y%m%d')
parser = argparse.ArgumentParser(
description=
'Plot the temperatures, pressures, or exposure meter data for a given night'
)
parser.add_argument('--night',
dest='night',
action='store',
type=str,
att_file = open(newpath + "/att.dat", "w")
mag_file = open(newpath + "/mag.dat", "w")
bmp_file = open(newpath + "/BMP.dat", "w")
gps_file = open(newpath + "/GPS.dat", "w")
cont_file = open(newpath + "/cont.dat", "w")
console_file = open(newpath + "/console.dat", "w")
#Sensor Initializations
l3g = L3G.L3G4200D()
l3g.enableDefault()
lsm = LSM.LSM303DLM()
lsm.enableDefault()
ser = serial.Serial('/dev/ttyAMA0', 4800, timeout=0.1)
att = attitude.attitude()
dac = MCP4725.MCP4725(0x60)
con = control.control(dac)
#GPIO Pin Initializations
GPIO.setmode(GPIO.BCM)
GPIO.setup(beeper_pin, GPIO.OUT)
GPIO.setup(fuser_pin, GPIO.OUT)
GPIO.setup(motor_pin, GPIO.OUT)
GPIO.setup(enable_pin, GPIO.OUT)
GPIO.output(beeper_pin, GPIO.LOW)
GPIO.output(fuser_pin, GPIO.LOW)
GPIO.output(motor_pin, GPIO.LOW)
GPIO.output(enable_pin, GPIO.HIGH)
#Sampling Frequencies
bmp_fs = 2.0
# Make a class we can use to capture stdout and sterr in the log
class MyLogger(object):
def __init__(self, logger, level):
self.logger = logger
self.level = level
def write(self, message):
# Only log if there is a message (not just a new line)
if message.rstrip() != "":
self.logger.log(self.level, message.rstrip())
# Replace stdout with logging to file at INFO level
sys.stdout = MyLogger(logger, logging.INFO)
# Replace stderr with logging to file at ERROR level
sys.stderr = MyLogger(logger, logging.ERROR)
pi = control()
def signal_handler(self, signal, frame):
global pi
print "SIGTERM received"
pi.shutdown()
sys.exit(0)
signal.signal(signal.SIGTERM, signal_handler)
pi.process()
from PIL import Image, ImageTk # 导入图像处理函数库
import tkinter as tk # 导入GUI界面函数库
import tkinter.filedialog
from control import control
# 创建窗口 设定大小并命名
window = tk.Tk()
window.title('图像显示界面')
window.geometry('600x500')
global img_png # 定义全局变量 图像的
global filename
global gt_png
global res_png
var = tk.StringVar() # 这时文字变量储存器
con = control()
# 创建打开图像和显示图像函数
def Open_Img():
global img_png
global filename
global gt_png
global res_png
var.set('Have choosed!')
Img = Image.open(filename)
img_png = ImageTk.PhotoImage(Img)
label_img = tk.Label(window, image=img_png)
label_img.pack(side='left')
name = filename.split('/')[-1].split('.')[0]
gt_path = '/home/zhangcb/Desktop/VOCpreprocessed/PASCALContourData/groundTruth_val/' + name + '.png'
#import interface
import control
#key map with a few things predefined
keymap = {"exit": "q", "kill": "Q"}
#appearance and stuff
look = {}
#read config and stuff
config_file = "./config" #the temp test file
if os.path.isfile(config_file):
config = configparser.ConfigParser()
try:
config.read(config_file)
except configparser.ParsingError:
print("config parse error, invalid config file syntax")
exit()
keymap = config['keys']
look = config['look']
else:
print("no config file")
exit()
ctrl = control.control(keymap, look)
ctrl.start()
xyd_f=np.matrix((0,0))
#Straight line trajectory
traj=line(xy0[0,0],xy0[1,0],xy_f[0,0],xy_f[0,1],tf,nstep)
x=traj[0]
y=traj[1]
xd=traj[2]
yd=traj[3]
#First iteration
PD=eq.PD(Kp,Kd,1)
PD.setKp(0.1)
PD.setKd(0.001)
ctl=ct.control(Kp,Kd)
qi=q0
qdi=qd0
xyi=xy0
xyd_des=np.matrix([0.01,0.01,0])
xydi=np.matrix([0,0,0])
xyddi=np.matrix([0,0,0])
O_des=np.matrix(np.cumsum(q_f))
Od_des=np.matrix(qd0)
T0=np.matrix([0,0,0]).T
error=1
count=0
for i in range(1,x.size-1):
#while (error>0.01):
#Parameter update
xy_des=np.matrix([x[0,i-1],y[0,i-1]])
if config.uid.isdigit():
config.uid = int(config.uid)
else:
import pwd
config.uid = pwd.getpwnam(config.uid)[2]
if config.gid.isdigit():
config.gid = int(config.gid)
else:
import grp
config.gid = grp.getgrnam(config.gid)[2]
#load all our components
import device
scanners = device.scanners(config)
import control
notify = control.control(config, scanners)
import http
webserver = http.http(config, scanners)
#drop our privileges n stuff
os.umask(0077)
os.setgid(config.gid)
os.setuid(config.uid)
#let's spawn everything we need
t = threading.Thread(target = notify.serve_forever, name = 'Control')
t.setDaemon(True)
t.start()
t = threading.Thread(target = webserver.serve_forever, name = 'Webserver')
t.setDaemon(True)
t.start()
att_file = open(newpath + "/att.dat", "w")
mag_file = open(newpath + "/mag.dat", "w")
bmp_file = open(newpath + "/BMP.dat", "w")
gps_file = open(newpath + "/GPS.dat", "w")
cont_file = open(newpath + "/cont.dat", "w")
console_file = open(newpath + "/console.dat", "w")
# Sensor Initializations
l3g = L3G.L3G4200D()
l3g.enableDefault()
lsm = LSM.LSM303DLM()
lsm.enableDefault()
ser = serial.Serial("/dev/ttyAMA0", 4800, timeout=0.1)
att = attitude.attitude()
dac = MCP4725.MCP4725(0x60)
con = control.control(dac)
# GPIO Pin Initializations
GPIO.setmode(GPIO.BCM)
GPIO.setup(beeper_pin, GPIO.OUT)
GPIO.setup(fuser_pin, GPIO.OUT)
GPIO.setup(motor_pin, GPIO.OUT)
GPIO.setup(enable_pin, GPIO.OUT)
GPIO.output(beeper_pin, GPIO.LOW)
GPIO.output(fuser_pin, GPIO.LOW)
GPIO.output(motor_pin, GPIO.LOW)
GPIO.output(enable_pin, GPIO.HIGH)
# Sampling Frequencies
bmp_fs = 2.0
inicio = (
offset -
1) * 3 #leo hasta el pixel anterior del offset donde quiero empezar
cuerpo = fd_image.read(inicio)
pixels = [i for i in cuerpo]
pixels = array.array('B', pixels)
#para que el hilo main siga haciendo sus cosas hasta que necesito los valores
mensaje_str, longitud = hilo_lector.join()
#una vez que tengo el encabezado y el largo del mensaje controlo que no sea mas grande
control(encabezado, interleave, longitud, offset)
#agrego el comentario de la UM
comentario = "#UMCOMPU2 {} {} {}\n".format(offset, interleave, longitud)
#Como tiene que arrancar siempre con PX
encabezado = encabezado[0:2] + "\n" + comentario + encabezado[2:]
#Guardo hasta ahi en el nuevo archivo
with open(output, 'wb') as f:
f.write(bytearray(encabezado, 'ascii'))
pixels.tofile(f)
#Comienza en el cuerpo
comienzo_rojo = 0
if form.getvalue('v1'):
v1= form.getvalue('v1')
else:
v1= "Not entered"
if form.getvalue('v2'):
v2= form.getvalue('v2')
else:
v2= "Not entered"
if form.getvalue('v3'):
v3= form.getvalue('v3')
else:
v3= "Not entered"
combined.take_user_variables(v1, v2, v3)
grade_type1=control.control('type1')
grade_type2=control.control('type2')
print('''
<html>
<head>
<title>Data Visualization</title>
</head>
<body>
This is the result for grade the data form user to a specific type of chart.<br>
<a href="type1/out.html">type1</a> grade:{0}
<br>
<a href="type2/out.html">type2</a> grade:{1}
</body>
</html>
'''.format(grade_type1,grade_type2))
#controlFile = "102-Studies/pencilValidation/TLPiFlash.dict"
#controlFile = "102-Studies/pencilValidation/PSMuDcy.dict"
# muons from transfer line
StudyDir = os.getenv('StudyDir')
StudyName = os.getenv('StudyName')
controlFile = os.path.join(StudyDir, "PSPiFLash.dict")
#controlFile = "StudyDir/StudyName/TLmuonDecay.dict"
##controlFile = "101-Studies/bdSimBeam01/PSPiFlash.dict"
##controlFile = "101-Studies/bdSimBeam01/PSMuDcyCF.dict"
##controlFile = "101-Studies/pencilValidation/PSMuDcyControlFile.dict"
## control file shared with the normalisation code
ctrlInst = control.control(controlFile)
# logfile initialisation
logging.basicConfig(filename=ctrlInst.logFile(),
encoding='utf-8',
level=logging.INFO)
print("======== analysing the eventHistory start ========")
logging.info("\n\n")
logging.info(
"======== analysing the eventHistory: start ======== Version %s",
aHVersion)
logging.info("Control file %s", controlFile)
objRd = eventHistory.eventHistory()
# Get the nuSIM path name and use it to set names for the inputfile and the outputFile
nuSIMPATH = os.getenv('nuSIMPATH')
def autoDrive(self, elapse = 0.1):
print("autoDrive activated")
# initialize control
myCtl = control()
# initialize obws
myObws = obws()
# enable radar
vars.shutdown = False
# start up radar
t_obws = threading.Thread(target = myObws.safedriving, args = ())
print("started")
t_obws.start()
for i in range(0, 5):
img = self.myCamera.capture()
self.myCamera.trunc()
time.sleep(0.2)
# start going forward
if self.debug == "False":
self.myCar.setSpeed(40, 40)
rightSpd, leftSpd = 40, 40
while True:
try:
# get the image from camera
img = self.myCamera.capture()
# init rawImage
raw = rawImage(img)
# init lightDetection
ld = lightDetection(img)
# truncate stream
self.myCamera.trunc()
# init thread to find deviation
t1 = threading.Thread(target = raw.findDeviation, args = ())
# init thread to find blue line
t2 = threading.Thread(target = raw.find_b, args = ())
# init thread to find traffic light
# t3 = threading.Thread(target = ld.find_light, args = ())
# start thread, get the deviation
t1.start()
# start thread, get blue lines
t2.start()
# start thread, get traffic light
# t3.start()
# wait elapsed time
time.sleep(elapse)
# join deviation thread
t1.join()
# join blue line thread
t2.join()
# join traffic light thread
# t3.join()
print("================================")
if vars.blue == True:
print("Blue line found")
self.myCar.setSpeed(0, 0)
break
"""
# check traffic light
if vars.light == "green":
# safe to go
print("green light")
elif vars.light == "red":
# stop the car
print("red light, stop")
self.myCar.setSpeed(0, 0)
else:
# no light found
print("no traffic light found, error")
"""
if vars.line_type == "b":
# both lines found
print("both lines found")
print("deviation = {}".format(vars.deviation))
elif vars.line_type == "y":
# only found yellow line
print("yellow line found")
print("y_theta = {}, y_offset = {}".format(vars.theta, vars.deviation))
elif vars.line_type == "w":
# only found white line
print("white line found")
print("w_theta = {}, w_offset = {}".format(vars.theta, vars.deviation))
# get current speed
if self.debug == "False":
rightSpd, leftSpd = self.myCar.getSpeed()
print("current rightSpd = {}".format(rightSpd))
print("current leftSpd = {}".format(leftSpd))
# running into obstacles
if vars.message == 0:
# stop
print("Running into obstacles, stop")
rightSpd, leftSpd = 0, 0
else:
# calculate new rightSpd and leftSpd to fix the deviation
rightSpd, leftSpd = myCtl.adaptive_control(rightSpd, leftSpd, vars.deviation, vars.theta, vars.line_type)
print("new rightSpd = {}".format(rightSpd))
print("new leftSpd = {}".format(leftSpd))
# pass speed arguments to myCar
if self.debug == "False":
self.myCar.setSpeed(rightSpd, leftSpd)
time.sleep(elapse)
except KeyboardInterrupt:
print("keyboard interrupt signal caught, exit")
vars.shutdown = True
self.myCar.turnoff()
self.myCamera.exit()
t_obws.join()
break
return
def rotation( *args, **keyword_args ):
"""
A function to form propagators that represent rotations in SU(2).
These may be multiplied to produce a pulse sequence.
**Forms:**
* ``rotation( axis )``
* ``rotation( theta, phi )``
* ``rotation( theta, axis )``
**Args:**
* *axis* : A three-element list, tuple or array representing
components of a Bloch vector. If axis is the sole input,
then the rotation angle is interpreted to be the length of
the axis vector.
* *theta* : A rotation angle.
* *phi* : A field phase. The interaction frame Hamiltonian for
this phase is proportional to :math:`H = \\cos \\phi X +
\\sin \\phi Y`.
**Optional keywords:**
See the propagator class for keywords.
**Returns:**
* :math:`U = R(\\theta,\\phi)`,
"""
# Check input arguments
if len( args ) == 1:
# Single argument, so must have been the rotation axis. Check
# if argument is a 3-vector.
arg = args[0]
try:
if arg.__len__() == 3:
theta = sqrt( arg[0]**2 + arg[1]**2 + arg[2]**2 )
vec = array([ arg[0], arg[1], arg[2] ]) / theta
else:
raise SyntaxError("Axis must be a 3-vector.")
except AttributeError:
raise SyntaxError("Axis must be a 3-vector.")
elif len( args ) == 2:
# Either an angle and an axis or an angle and a phase.
# Distinguish between the two and construct a 3-vector.
theta = args[0]
arg = args[1]
try:
if arg.__len__() == 3:
# Normalize the axis
norm = sqrt( arg[0]**2 + arg[1]**2 + arg[2]**2 )
if norm == 0:
raise ValueError("Axis must not be a null vector.")
vec = array([ arg[0], arg[1], arg[2] ]) / (norm)
else:
raise SyntaxError("Axis must be a 3-vector.")
except AttributeError:
# Must have specified a phase instead of an axis. Produce
# one for the user.
phi = arg
vec = array([cos(phi), sin(phi), 0])
else:
raise SyntaxError("Improper number of arguments.")
# Construct the control function and the propagator. We assume
# square pulse propagators (i.e. constant controls over the
# interval).
# Check for negative rotation angles.
if theta < 0:
vec = - vec
theta = - theta
ctrl = array([[vec[0], vec[1], vec[2], 0 ],
[vec[0], vec[1], vec[2], theta]])
u = control.control(ctrl)
return propagator( u, [Hx,Hy,Hz], **keyword_args )
thread.join()
if __name__ == '__main__':
parser = argparse.ArgumentParser(description='Observe with MINERVA')
parser.add_argument('--red',
dest='red',
action='store_true',
default=False,
help='run with MINERVA red configuration')
parser.add_argument('--south',
dest='south',
action='store_true',
default=False,
help='run with MINERVA Australis configuration')
opt = parser.parse_args()
# python bug work around -- strptime not thread safe. Must call this once before starting threads
junk = datetime.datetime.strptime('2000-01-01 00:00:00',
'%Y-%m-%d %H:%M:%S')
base_directory = '/home/minerva/minerva-control'
if socket.gethostname() == 'Kiwispec-PC':
base_directory = 'C:/minerva-control'
minerva = control.control('control.ini',
base_directory,
red=opt.red,
south=opt.south)
domeControlThread(minerva)
def __init__(self, oscillframe):
threading.Thread.__init__(self)
self.oscillframe = oscillframe
self.controller = control.control()
'''
Created on 24/09/2012
@author: sebastien
'''
import sys
from PySide import QtGui, QtCore
import bassic, control
if __name__ == "__main__":
control = control.control()
bassic.new(control)
import wx import initLayout import control app = wx.PySimpleApp() frame = initLayout.initLayout() controller = control.control(frame) app.MainLoop()
def make_control(self, options):
return control(options)
def datapath(clk_period=1, reset=Signal(intbv(0)[1:]), zero=Signal(intbv(0)[1:])):
##############################
#
# clock settings
#
##############################
clk = Signal(intbv(0)[1:]) # internal clock
clk_pc = Signal(intbv(0)[1:]) # frec should be almost 1/4 clk internal
clk_driver = clock_driver(clk, clk_period)
clk_driver_pc = clock_driver(clk_pc, clk_period * 4)
##############################
#
# internal signals
#
##############################
#program counter and branch signals
ip = Signal(intbv(0)[32:]) # connect PC with intruction_memory
pc_adder_out = Signal(intbv(0)[32:]) # output of pc_adder - input0 branch_adder and mux_branch
next_ip = Signal(intbv(0)[32:]) # output of mux_branch - input of pc
branch_adder_out = Signal(intbv(0)[32:])
branchZ = Signal(intbv(0)[1:]) # control of mux_branch
instruction = Signal(intbv(0)[32:]) # 32 bits instruction line.
#control signals
signals_1bit = [Signal(intbv(0)[1:]) for i in range(7)]
RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch = signals_1bit
#ALUop connect Control with ALUcontrol
ALUop = Signal(intbv(0)[2:])
#intruction memory output connectors
opcode = Signal(intbv(0)[6:]) # instruction 31:26 - to Control
rs = Signal(intbv(0)[5:]) # instruction 25:21 - to read_reg_1
rt = Signal(intbv(0)[5:]) # instruction 20:16 - to read_reg_2 and mux controlled by RegDst
rd = Signal(intbv(0)[5:]) # instruction 15:11 - to the mux controlled by RegDst
shamt = Signal(intbv(0)[5:]) # instruction 10:6 -
func = Signal(intbv(0)[6:]) # instruction 5:0 - to ALUCtrl
address = Signal(intbv(0, min=-(2 ** 15), max=2 ** 15 - 1)) # instruction 15:0 - to Sign Extend
wr_reg_in = Signal(intbv(0)[5:]) # output of mux_wreg (it's rt or rd depends on RegDst)
address32 = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1)) # output of signextend
#register file data vectors (input and outputs)
data_in, data1, data2 = [Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1)) for i in range(3)]
mux_alu_out = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1)) # output of mux_alu_src
#(data2 or address32 depends on ALUSrc)
#ALU signals
alu_control_out = Signal(intbv('1111')[4:])
alu_out = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))
zero = Signal(intbv(0)[1:])
#data memory signal
ram_out = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))
mux_ram_out = Signal(intbv(0, min=-(2 ** 31), max=2 ** 31 - 1))
##############################
#
# component instances
#
##############################
#program counter
pc = program_counter(clk_pc, next_ip, ip)
increment = 1 # it's 4 in the book, but my memory it's organized in 32bits words, not bytes
pc_adder = ALU(Signal(0b0010), ip, Signal(increment), pc_adder_out, Signal(0)) # hardwire an ALU to works as an adder
branch_adder = ALU(Signal(0b0010), pc_adder_out, address32, branch_adder_out, Signal(0))
branch_and_gate = and_gate(Branch, zero, branchZ)
mux_branch = mux2(branchZ, next_ip, pc_adder_out, branch_adder_out)
im = instruction_memory(ip, instruction)
id = instruction_dec(instruction, opcode, rs, rt, rd, shamt, func, address)
control_i = control(opcode, RegDst, Branch, MemRead, MemtoReg, ALUop, MemWrite, ALUSrc, RegWrite)
mux_wreg = mux2(RegDst, wr_reg_in, rt, rd)
register_file_i = register_file(clk, rs, rt, wr_reg_in, mux_ram_out, RegWrite, data1, data2, depth=32)
sign_extend_i = sign_extend(address, address32)
alu_control_i = alu_control(ALUop, func, alu_control_out)
mux_alu_src = mux2(ALUSrc, mux_alu_out, data2, address32)
alu_i = ALU(alu_control_out, data1, mux_alu_out, alu_out, zero)
data_memory_i = data_memory(clk, alu_out, data2, ram_out, MemRead, MemWrite)
mux_mem2reg = mux2(MemtoReg, mux_ram_out, alu_out, ram_out)
if DEBUG:
@always(clk.posedge)
def debug_internals():
print "-" * 78
print "time %s | clk %i | clk_pc %i | ip %i " % (now(), clk, clk_pc, ip)
print 'pc_add_o %i | branch_add_o %i | BranchZ %i | next_ip %i' % (pc_adder_out, branch_adder_out, branchZ, next_ip)
print 'instruction', bin(instruction, 32)
print 'opcode %s | rs %i | rt %i | rd %i | shamt %i | func %i | address %i' % \
(bin(opcode, 6), rs, rt, rd, shamt, func, address)
print 'wr_reg_in %i | dat1 %i | dat2 %i | muxALUo %i ' % \
(wr_reg_in, data1, data2, mux_alu_out)
print 'RegDst %i | ALUSrc %i | Mem2Reg %i | RegW %i | MemR %i | MemW %i | Branch %i | ALUop %s' % (RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, bin(ALUop, 2))
print 'func: %s | aluop: %s | alu_c_out: %s' % (bin(func, 5),
bin(ALUop, 2),
bin(alu_control_out, 4))
print 'ALU_out: %i | Zero: %i' % (alu_out, zero)
print 'ram_out %i | mux_ram_out %i ' % (ram_out, mux_ram_out)
return instances()
def pipeline(clk_period=1, Reset=Signal(intbv(0)[1:]), Zero=Signal(intbv(0)[1:])):
"""
A DLX processor with 5 pipeline stages.
=======================================
Stages
------
[IF] -> IF/ID -> [ID] -> ID/EX -> [EX] -> EX/MEM -> [MEM] -> MEM/WB __
^ |
|_______________________________________________________|
Conventions:
------------
* Signals are in ``CamelCase``
* Instances are with ``under_score``
* The signals shared two or more stage are suffixed with the pipeline stage to which it belongs.
For example: ``PcAdderO_if`` before IF/ID latch is the same signal than
``PcAdderO_id`` after it.
"""
##############################
# clock settings
##############################
Clk = Signal(intbv(0)[1:]) # internal clock
ClkPc = Signal(intbv(0)[1:]) # frec should be almost 1/4 clk internal
clk_driver = clock_driver(Clk, clk_period)
clk_driver_pc = clock_driver(ClkPc, clk_period * 4)
####################
# feedback Signals
######################
# signals from and advanced stage which feeds a previous component
BranchAdderO_mem = Signal(intbv(0, min=MIN, max=MAX)[32:])
PCSrc_mem = Signal(intbv(0)[1:]) # control of mux for program_counter on IF stage - (branch or inmediante_next)
WrRegDest_wb = Signal(intbv(0)[32:]) # register pointer where MuxMemO_wb data will be stored.
MuxMemO_wb = Signal(
intbv(0, min=MIN, max=MAX)
) # data output from WB mux connected as Write Data input on Register File (ID stage)
RegWrite_wb = Signal(intbv(0)[1:])
##############################
# IF
##############################
# instruction memory
Ip = Signal(intbv(0)[32:]) # connect PC with intruction_memory
Instruction_if = Signal(intbv(0)[32:]) # 32 bits instruction line.
im = instruction_memory(Ip, Instruction_if)
# PC
NextIp = Signal(intbv(0)[32:]) # output of mux_branch - input of pc
pc = program_counter(Clk, NextIp, Ip)
# pc_adder
INCREMENT = 1 # it's 4 in the book, but my memory it's organized in 32bits words, not bytes
PcAdderOut_if = Signal(intbv(0)[32:]) # output of pc_adder - input0 branch_adder and mux_branch
pc_adder = ALU(
Signal(0b0010), Ip, Signal(INCREMENT), PcAdderOut_if, Signal(0)
) # hardwire an ALU to works as an adder
# mux controlling next ip branches.
mux_pc_source = mux2(PCSrc_mem, NextIp, PcAdderOut_if, BranchAdderO_mem)
##############################
# IF/ID
##############################
PcAdderOut_id = Signal(intbv(0)[32:])
Instruction_id = Signal(intbv(0)[32:])
latch_if_id_ = latch_if_id(Clk, Reset, Instruction_if, PcAdderOut_if, Instruction_id, PcAdderOut_id)
##############################
# ID
##############################
# DECODER
Opcode_id = Signal(intbv(0)[6:]) # instruction 31:26 - to Control
Rs_id = Signal(intbv(0)[5:]) # instruction 25:21 - to read_reg_1
Rt_id = Signal(intbv(0)[5:]) # instruction 20:16 - to read_reg_2 and mux controlled by RegDst
Rd_id = Signal(intbv(0)[5:]) # instruction 15:11 - to the mux controlled by RegDst
Shamt_id = Signal(intbv(0)[5:]) # instruction 10:6 -
Func_id = Signal(intbv(0)[6:]) # instruction 5:0 - to ALUCtrl
Address16_id = Signal(intbv(0, min=-(2 ** 15), max=2 ** 15 - 1)) # instruction 15:0 - to Sign Extend
NopSignal = Signal(intbv(0)[1:])
instruction_decoder_ = instruction_dec(
Instruction_id, Opcode_id, Rs_id, Rt_id, Rd_id, Shamt_id, Func_id, Address16_id, NopSignal
)
# sign extend
Address32_id = Signal(intbv(0, min=MIN, max=MAX))
sign_extend_ = sign_extend(Address16_id, Address32_id)
# CONTROL
signals_1bit = [Signal(intbv(0)[1:]) for i in range(7)]
RegDst_id, ALUSrc_id, MemtoReg_id, RegWrite_id, MemRead_id, MemWrite_id, Branch_id = signals_1bit
ALUop_id = Signal(intbv(0)[2:])
control_ = control(
Opcode_id,
RegDst_id,
Branch_id,
MemRead_id,
MemtoReg_id,
ALUop_id,
MemWrite_id,
ALUSrc_id,
RegWrite_id,
NopSignal,
)
# REGISTER FILE
Data1_id = Signal(intbv(0, min=MIN, max=MAX))
Data2_id = Signal(intbv(0, min=MIN, max=MAX))
register_file_i = register_file(
Clk, Rs_id, Rt_id, WrRegDest_wb, MuxMemO_wb, RegWrite_wb, Data1_id, Data2_id, depth=32
)
##############################
# ID/EX
##############################
PcAdderOut_ex = Signal(intbv(0)[32:])
signals_1bit = [Signal(intbv(0)[1:]) for i in range(7)]
RegDst_ex, ALUSrc_ex, MemtoReg_ex, RegWrite_ex, MemRead_ex, MemWrite_ex, Branch_ex = signals_1bit
ALUop_ex = Signal(intbv(0)[2:])
Data1_ex = Signal(intbv(0, min=MIN, max=MAX))
Data2_ex = Signal(intbv(0, min=MIN, max=MAX))
Rs_ex = Signal(intbv(0)[5:]) # instruction 25:21 - to read_reg_1
Rt_ex = Signal(intbv(0)[5:]) # instruction 20:16 - to read_reg_2 and mux controlled by RegDst
Rd_ex = Signal(intbv(0)[5:]) # instruction 15:11 - to the mux controlled by RegDst
# Shamt_ex = Signal(intbv(0)[5:]) #instruction 10:6 -
Func_ex = Signal(intbv(0)[6:]) # instruction 5:0 - to ALUCtrl
Address32_ex = Signal(intbv(0, min=MIN, max=MAX))
latch_id_ex_ = latch_id_ex(
Clk,
Reset,
PcAdderOut_id,
Data1_id,
Data2_id,
Address32_id,
Rd_id,
Rt_id,
Func_id,
RegDst_id,
ALUop_id,
ALUSrc_id, # signals to EX pipeline stage
Branch_id,
MemRead_id,
MemWrite_id, # signals to MEM pipeline stage
RegWrite_id,
MemtoReg_id, # signals to WB pipeline stage
PcAdderOut_ex,
Data1_ex,
Data2_ex,
Address32_ex,
Rd_ex,
Rt_ex,
Func_ex,
RegDst_ex,
ALUop_ex,
ALUSrc_ex, # signals to EX pipeline stage
Branch_ex,
MemRead_ex,
MemWrite_ex, # signals to MEM pipeline stage
RegWrite_ex,
MemtoReg_ex, # signals to WB pipeline stage
)
##############################
# EX
##############################
BranchAdderO_ex = Signal(intbv(0, min=MIN, max=MAX)[32:])
Zero_ex = Signal(intbv(0)[1:])
AluResult_ex = Signal(intbv(0, min=MIN, max=MAX))
MuxAluDataSrc_ex = Signal(intbv(0, min=MIN, max=MAX))
WrRegDest_ex = Signal(intbv(0)[32:])
# muxer 2nd operand in ALU
mux_alu_src = mux2(ALUSrc_ex, MuxAluDataSrc_ex, Data2_ex, Address32_ex)
# Branch adder
branch_adder_ = ALU(Signal(0b0010), PcAdderOut_ex, Address32_ex, BranchAdderO_ex, Signal(0))
# ALU Control
AluControl = Signal(intbv("1111")[4:]) # control signal to alu
alu_control_ = alu_control(ALUop_ex, Func_ex, AluControl)
# ALU
alu_ = ALU(AluControl, Data1_ex, MuxAluDataSrc_ex, AluResult_ex, Zero_ex)
# Mux RegDestiny Control Write register between rt and rd.
mux_wreg = mux2(RegDst_ex, WrRegDest_ex, Rt_ex, Rd_ex)
##############################
# EX/MEM
##############################
BranchAdderO_mem = Signal(intbv(0, min=MIN, max=MAX))
Zero_mem = Signal(intbv(0)[1:])
AluResult_mem = Signal(intbv(0, min=MIN, max=MAX))
Data2_mem = Signal(intbv(0, min=MIN, max=MAX))
WrRegDest_mem = Signal(intbv(0)[32:])
# control signals
signals_1bit = [Signal(intbv(0)[1:]) for i in range(5)]
MemtoReg_mem, RegWrite_mem, MemRead_mem, MemWrite_mem, Branch_mem = signals_1bit
latch_ex_mem_ = latch_ex_mem(
Clk,
Reset,
BranchAdderO_ex,
AluResult_ex,
Zero_ex,
Data2_ex,
WrRegDest_ex,
Branch_ex,
MemRead_ex,
MemWrite_ex, # signals to MEM pipeline stage
RegWrite_ex,
MemtoReg_ex, # signals to WB pipeline stage
BranchAdderO_mem,
AluResult_mem,
Zero_mem,
Data2_mem,
WrRegDest_mem,
Branch_mem,
MemRead_mem,
MemWrite_mem, # signals to MEM pipeline stage
RegWrite_mem,
MemtoReg_mem, # signals to WB pipeline stage
)
##############################
# MEM
##############################
DataMemOut_mem = Signal(intbv(0, min=MIN, max=MAX))
# branch AND gate
branch_and_gate = and_gate(Branch_mem, Zero_mem, PCSrc_mem)
# data memory
data_memory_ = data_memory(Clk, AluResult_mem, Data2_mem, DataMemOut_mem, MemRead_mem, MemWrite_mem)
##############################
# EX/WB
##############################
# RegWrite_wb, on feedback signals section
MemtoReg_wb = Signal(intbv(0)[1:])
DataMemOut_wb = Signal(intbv(0, min=MIN, max=MAX))
AluResult_wb = Signal(intbv(0, min=MIN, max=MAX))
# WrRegDest_wb on feedback signals sections.
latch_mem_wb_ = latch_mem_wb(
Clk,
Reset,
DataMemOut_mem,
AluResult_mem,
WrRegDest_mem,
RegWrite_mem,
MemtoReg_mem, # signals to WB pipeline stage
DataMemOut_wb,
AluResult_wb,
WrRegDest_wb,
RegWrite_wb,
MemtoReg_wb, # signals to WB pipeline stage
)
##############################
# WB
##############################
# mux2(sel, mux_out, chan1, chan2):
mux_mem2reg_ = mux2(MemtoReg_wb, MuxMemO_wb, AluResult_wb, DataMemOut_wb)
##############################
# Forwarding unit
##############################
##############################
# hazard detection unit
##############################
if DEBUG:
@always(Clk.posedge)
def debug_internals():
sep = "\n" + "=" * 34 + " time %s " + "=" * 34
print sep % now()
# IF
print "\n" + "." * 35 + " IF " + "." * 35 + "\n"
print "PcAdderOut_if %i | BranchAdderO_mem %i | PCSrc_mem %i | NextIp %i | Ip %i" % (
PcAdderOut_if,
BranchAdderO_mem,
PCSrc_mem,
NextIp,
Ip,
)
print "Instruction_if %s (%i)" % (bin(Instruction_if, 32), Instruction_if)
if True: # now () > 2:
# ID
print "\n" + "." * 35 + " ID " + "." * 35 + "\n"
print "PcAdderO_id %i | Instruction_id %s (%i) | Nop %i" % (
PcAdderOut_id,
bin(Instruction_id, 32),
Instruction_id,
NopSignal,
)
print "Op %s | Rs %i | Rt %i | Rd %i | Func %i | Addr16 %i | Addr32 %i" % (
bin(Opcode_id, 6),
Rs_id,
Rt_id,
Rd_id,
Func_id,
Address16_id,
Address32_id,
)
print "Data1 %i | Data2 %i" % (Data1_id, Data2_id)
print "-->CONTROL"
print "RegDst %i ALUop %s ALUSrc %i | Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i " % (
RegDst_id,
bin(ALUop_id, 2),
ALUSrc_id,
Branch_id,
MemRead_id,
MemWrite_id,
RegWrite_id,
MemtoReg_id,
)
if True: # if now () > 4:
# EX
print "\n" + "." * 35 + " EX " + "." * 35 + "\n"
print "PcAdderO_ex %i | BranchAdderO_ex %i " % (PcAdderOut_ex, BranchAdderO_ex)
print "Rs %i | Rt %i | Rd %i | Func %i | Addr32 %i" % (Rs_ex, Rt_ex, Rd_ex, Func_ex, Address32_ex)
print "Data1_ex %i | Data2_ex %i" % (Data1_ex, Data2_ex)
print "-->CONTROL"
print "RegDst %i ALUop %s ALUSrc %i | Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i " % (
RegDst_ex,
bin(ALUop_ex, 2),
ALUSrc_ex,
Branch_ex,
MemRead_ex,
MemWrite_ex,
RegWrite_ex,
MemtoReg_ex,
)
print "--> ALU"
print "MuxAluDataSrc %i | AluCtrl %s | AluResult_ex %i | Zero_ex %i" % (
MuxAluDataSrc_ex,
bin(AluControl, 4),
AluResult_ex,
Zero_ex,
)
print "WrRegDest_ex %i" % WrRegDest_ex
if True: # if now () > 6:
# MEM
print "\n" + "." * 35 + "MEM " + "." * 35 + "\n"
print "BranchAdderO_mem %i " % (BranchAdderO_mem)
print "-->CONTROL"
print "Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i " % (
Branch_mem,
MemRead_mem,
MemWrite_mem,
RegWrite_mem,
MemtoReg_mem,
)
print "--> Branch"
print "Branch_mem %i Zero %i | PCSrc_mem %i" % (Branch_mem, Zero_mem, PCSrc_mem)
print "--> Data mem"
print "AluResult_mem %i | Data2_mem %i | DataMemOut_mem %i | MemW %i MemR %i" % (
AluResult_mem,
Data2_mem,
DataMemOut_mem,
MemWrite_mem,
MemRead_mem,
)
print "WrRegDest_mem %i" % WrRegDest_mem
if True: # if now() > 8:
# WB
print "\n" + "." * 35 + "WB" + "." * 35 + "\n"
print "CONTROL --> RegW %i Mem2Reg %i " % (RegWrite_mem, MemtoReg_mem)
print "DataMemOut_wb %i | AluResult_wb %i | MuxMemO_wb %i " % (DataMemOut_wb, AluResult_wb, MuxMemO_wb)
print "WrRegDest_wb %i | MuxMemO_wb %i" % (WrRegDest_wb, MuxMemO_wb)
return instances()
def dlx(clk_period=1, Reset=Signal(intbv(0)[1:]), Zero=Signal(intbv(0)[1:])):
"""
A DLX processor with 5 pipeline stages.
=======================================
Stages
------
+------------------+
| +------- Hazard
| | +-> Detect <-----+
| | | | |
| | | | |
v v | v |
[IF] -> IF/ID -> [ID] -> ID/EX -> [EX] -> EX/MEM -> [MEM] -> MEM/WB __
^ | ^ | | |
| | | <_____________| | |
| +> FORW <___________________________| |
| |
|_______________________________________________________|
Conventions:
------------
* Signals are in ``CamelCase``
* Instances are with ``under_score_`` (with a last ``_``)
* The signals shared two or more stage are suffixed with the pipeline stage to which it belongs.
For example: ``PcAdderO_if`` before IF/ID latch is the same signal than
``PcAdderO_id`` after it.
"""
##############################
# clock settings
##############################
Clk = Signal(intbv(0)[1:]) #internal clock
ClkPc = Signal(intbv(0)[1:]) #frec should be almost 1/4 clk internal
clk_driver = clock_driver(Clk, clk_period)
clk_driver_pc = clock_driver(ClkPc, clk_period * 4)
####################
#feedback Signals
######################
# signals from and advanced stage which feeds a previous component
BranchAdderO_mem = Signal(intbv(0, min=MIN, max=MAX)[32:])
PCSrc_mem = Signal(intbv(0)[1:]) #control of mux for program_counter on IF stage - (branch or inmediante_next)
FlushOnBranch = PCSrc_mem # 1 when beq condition is asserted => flush IF / ID / EX to discard
# instructions chargued wrongly
WrRegDest_wb = Signal(intbv(0)[32:]) #register pointer where MuxMemO_wb data will be stored.
MuxMemO_wb = Signal(intbv(0, min=MIN, max=MAX)) #data output from WB mux connected as Write Data input on Register File (ID stage)
RegWrite_wb = Signal(intbv(0)[1:])
ForwardA, ForwardB = [ Signal(intbv(0)[2:]) for i in range(2) ] #Signals Generated in Forwarding units to control ALU's input muxers
AluResult_mem = Signal(intbv(0, min=MIN, max=MAX))
Stall = Signal(intbv(0)[1:]) #when asserted the pipeline is stalled. It 'freezes' PC count
#and put all Control Signals to 0's
##############################
# IF
##############################
#instruction memory
Ip = Signal(intbv(0)[32:] ) #connect PC with intruction_memory
Instruction_if = Signal(intbv(0)[32:]) #32 bits instruction line.
im = instruction_memory (Ip, Instruction_if)
#PC
NextIp = Signal(intbv(0)[32:] ) #output of mux_branch - input of pc
pc = program_counter(Clk, NextIp, Ip, Stall)
#pc_adder
INCREMENT = 1 #it's 4 in the book, but my instruction memory is organized in 32bits words, not in bytes
PcAdderOut_if = Signal(intbv(0)[32:] ) #output of pc_adder - input0 branch_adder and mux_branch
pc_adder = ALU(Signal(0b0010), Ip, Signal(INCREMENT), PcAdderOut_if, Signal(0)) #hardwiring an ALU to works as an adder
#mux controlling next ip branches.
mux_pc_source = mux2(PCSrc_mem, NextIp, PcAdderOut_if, BranchAdderO_mem)
##############################
# IF/ID
##############################
PcAdderOut_id = Signal(intbv(0)[32:])
Instruction_id = Signal(intbv(0)[32:])
latch_if_id_ = latch_if_id(Clk, FlushOnBranch, Instruction_if, PcAdderOut_if, Instruction_id, PcAdderOut_id, Stall)
##############################
# ID
##############################
#DECODER
Opcode_id = Signal(intbv(0)[6:]) #instruction 31:26 - to Control
Rs_id = Signal(intbv(0)[5:]) #instruction 25:21 - to read_reg_1
Rt_id = Signal(intbv(0)[5:]) #instruction 20:16 - to read_reg_2 and mux controlled by RegDst
Rd_id = Signal(intbv(0)[5:]) #instruction 15:11 - to the mux controlled by RegDst
Shamt_id = Signal(intbv(0)[5:]) #instruction 10:6 -
Func_id = Signal(intbv(0)[6:]) #instruction 5:0 - to ALUCtrl
Address16_id = Signal(intbv(0, min=-(2**15), max=2**15 - 1)) #instruction 15:0 - to Sign Extend
NopSignal = Signal(intbv(0)[1:])
instruction_decoder_ = instruction_dec(Instruction_id, Opcode_id, Rs_id, Rt_id, Rd_id, Shamt_id, Func_id, Address16_id, NopSignal)
#sign extend
Address32_id = Signal(intbv(0, min=MIN, max=MAX))
sign_extend_ = sign_extend(Address16_id, Address32_id)
#CONTROL
signals_1bit = [Signal(intbv(0)[1:]) for i in range(7)]
RegDst_id, ALUSrc_id, MemtoReg_id, RegWrite_id, MemRead_id, MemWrite_id, Branch_id = signals_1bit
ALUop_id = Signal(intbv(0)[2:])
control_ = control(Opcode_id, RegDst_id, Branch_id, MemRead_id,
MemtoReg_id, ALUop_id, MemWrite_id, ALUSrc_id, RegWrite_id, NopSignal, Stall)
#REGISTER FILE
Data1_id = Signal(intbv(0, min=MIN, max=MAX))
Data2_id = Signal(intbv(0, min=MIN, max=MAX))
register_file_i = register_file(Clk, Rs_id, Rt_id, WrRegDest_wb, MuxMemO_wb, RegWrite_wb, Data1_id, Data2_id, depth=32)
##############################
# ID/EX
##############################
PcAdderOut_ex = Signal(intbv(0)[32:])
signals_1bit = [Signal(intbv(0)[1:]) for i in range(7)]
RegDst_ex, ALUSrc_ex, MemtoReg_ex, RegWrite_ex, MemRead_ex, MemWrite_ex, Branch_ex = signals_1bit
ALUop_ex = Signal(intbv(0)[2:])
Data1_ex = Signal(intbv(0, min=MIN, max=MAX))
Data2_ex = Signal(intbv(0, min=MIN, max=MAX))
Rs_ex = Signal(intbv(0)[5:]) #instruction 25:21 - to read_reg_1
Rt_ex = Signal(intbv(0)[5:]) #instruction 20:16 - to read_reg_2 and mux controlled by RegDst
Rd_ex = Signal(intbv(0)[5:]) #instruction 15:11 - to the mux controlled by RegDst
#Shamt_ex = Signal(intbv(0)[5:]) #instruction 10:6 -
Func_ex = Signal(intbv(0)[6:]) #instruction 5:0 - to ALUCtrl
Address32_ex = Signal(intbv(0, min=MIN, max=MAX))
latch_id_ex_ = latch_id_ex(Clk, FlushOnBranch,
PcAdderOut_id,
Data1_id, Data2_id, Address32_id,
Rs_id, Rt_id, Rd_id, Func_id,
RegDst_id, ALUop_id, ALUSrc_id, #signals to EX pipeline stage
Branch_id, MemRead_id, MemWrite_id, #signals to MEM pipeline stage
RegWrite_id, MemtoReg_id, #signals to WB pipeline stage
PcAdderOut_ex,
Data1_ex, Data2_ex, Address32_ex,
Rs_ex, Rt_ex, Rd_ex, Func_ex,
RegDst_ex, ALUop_ex, ALUSrc_ex, #signals to EX pipeline stage
Branch_ex, MemRead_ex, MemWrite_ex, #signals to MEM pipeline stage
RegWrite_ex, MemtoReg_ex #signals to WB pipeline stage
)
##############################
# EX
##############################
BranchAdderO_ex = Signal(intbv(0, min=MIN, max=MAX)[32:])
Zero_ex = Signal(intbv(0)[1:])
AluResult_ex = Signal(intbv(0, min=MIN, max=MAX))
ForwMux1Out, ForwMux2Out = [ Signal(intbv(0, min=MIN, max=MAX)) for i in range(2) ] #Output of forw_mux1 and forw_mux2
MuxAluDataSrc_ex = Signal(intbv(0, min=MIN, max=MAX))
WrRegDest_ex = Signal(intbv(0)[32:])
forw_mux1_ = mux4(ForwardA, ForwMux1Out, Data1_ex, MuxMemO_wb, AluResult_mem)
forw_mux2_ = mux4(ForwardB, ForwMux2Out, Data2_ex, MuxMemO_wb, AluResult_mem)
#2nd muxer of 2nd operand in ALU
mux_alu_src = mux2(ALUSrc_ex, MuxAluDataSrc_ex, ForwMux2Out, Address32_ex)
#Branch adder
branch_adder_ = ALU(Signal(0b0010), PcAdderOut_ex, Address32_ex, BranchAdderO_ex, Signal(0))
#ALU Control
AluControl = Signal(intbv('1111')[4:]) #control signal to alu
alu_control_ = alu_control(ALUop_ex, Func_ex, AluControl)
#ALU
alu_ = ALU(AluControl, ForwMux1Out, MuxAluDataSrc_ex, AluResult_ex, Zero_ex)
#Mux RegDestiny Control Write register between rt and rd.
mux_wreg = mux2(RegDst_ex, WrRegDest_ex, Rt_ex, Rd_ex)
##############################
# EX/MEM
##############################
BranchAdderO_mem = Signal(intbv(0, min=MIN, max=MAX))
Zero_mem = Signal(intbv(0)[1:])
Data2_mem = Signal(intbv(0, min=MIN, max=MAX))
WrRegDest_mem = Signal(intbv(0)[32:])
#control signals
signals_1bit = [Signal(intbv(0)[1:]) for i in range(5)]
MemtoReg_mem, RegWrite_mem, MemRead_mem, MemWrite_mem, Branch_mem = signals_1bit
latch_ex_mem_ = latch_ex_mem(Clk, Reset,
BranchAdderO_ex,
AluResult_ex, Zero_ex,
Data2_ex, WrRegDest_ex,
Branch_ex, MemRead_ex, MemWrite_ex, #signals to MEM pipeline stage
RegWrite_ex, MemtoReg_ex, #signals to WB pipeline stage
BranchAdderO_mem,
AluResult_mem, Zero_mem,
Data2_mem, WrRegDest_mem,
Branch_mem, MemRead_mem, MemWrite_mem, #signals to MEM pipeline stage
RegWrite_mem, MemtoReg_mem, #signals to WB pipeline stage
)
##############################
# MEM
##############################
DataMemOut_mem = Signal(intbv(0, min=MIN, max=MAX))
#branch AND gate
branch_and_gate = and_gate(Branch_mem, Zero_mem, PCSrc_mem)
#data memory
data_memory_ = data_memory(Clk, AluResult_mem, Data2_mem, DataMemOut_mem, MemRead_mem, MemWrite_mem)
##############################
# EX/WB
##############################
#RegWrite_wb, on feedback signals section
MemtoReg_wb = Signal(intbv(0)[1:])
DataMemOut_wb = Signal(intbv(0, min=MIN, max=MAX))
AluResult_wb = Signal(intbv(0, min=MIN, max=MAX))
#WrRegDest_wb on feedback signals sections.
latch_mem_wb_ = latch_mem_wb(Clk, Reset,
DataMemOut_mem,
AluResult_mem,
WrRegDest_mem,
RegWrite_mem, MemtoReg_mem, #signals to WB pipeline stage
DataMemOut_wb,
AluResult_wb,
WrRegDest_wb,
RegWrite_wb, MemtoReg_wb, #signals to WB pipeline stage
)
##############################
# WB
##############################
#mux2(sel, mux_out, chan1, chan2):
mux_mem2reg_ = mux2(MemtoReg_wb, MuxMemO_wb, AluResult_wb, DataMemOut_wb)
##############################
# Forwarding unit
##############################
forwarding_ = forwarding(RegWrite_mem, WrRegDest_mem, Rs_ex, Rt_ex, #inputs of EX hazards
RegWrite_wb, WrRegDest_wb, #left inputs of MEM hazards
ForwardA, ForwardB
)
##############################
# hazard detection unit
##############################
hazard_detector_ = hazard_detector(MemRead_ex, Rt_ex,
Rs_id, Rt_id,
Stall)
if DEBUG:
@always(Clk.posedge)
def debug_internals():
sep = "\n" + "=" * 31 + " cycle %i (%ins)" + "=" * 31
print sep % ( int(now()/2.0 + 0.5), now() )
#IF
print "\n" + "." * 35 + " IF " + "." * 35 + "\n"
print "PcAdderOut_if %i | BranchAdderO_mem %i | PCSrc_mem %i | NextIp %i | Ip %i" % (PcAdderOut_if, BranchAdderO_mem, PCSrc_mem, NextIp, Ip)
print 'Instruction_if %s (%i)' % (bin(Instruction_if, 32), Instruction_if)
if True: # now () > 2:
#ID
print "\n" + "." * 35 + " ID " + "." * 35 + "\n"
print "PcAdderO_id %i | Instruction_id %s (%i) | Nop %i" % (PcAdderOut_id, bin(Instruction_id, 32), Instruction_id, NopSignal )
print 'Op %s | Rs %i | Rt %i | Rd %i | Func %i | Addr16 %i | Addr32 %i' % \
(bin(Opcode_id, 6), Rs_id, Rt_id, Rd_id, Func_id, Address16_id, Address32_id )
print 'Data1 %i | Data2 %i' % (Data1_id, Data2_id)
print '-->CONTROL'
print 'RegDst %i ALUop %s ALUSrc %i | Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
( RegDst_id , bin(ALUop_id, 2), ALUSrc_id, Branch_id, MemRead_id, MemWrite_id, RegWrite_id, MemtoReg_id)
print 'Stall --> %i' % Stall
if True: #if now () > 4:
#EX
print "\n" + "." * 35 + " EX " + "." * 35 + "\n"
print "PcAdderO_ex %i | BranchAdderO_ex %i " % (PcAdderOut_ex, BranchAdderO_ex)
print "Rs %i | Rt %i | Rd %i | Func %i | Addr32 %i" % (Rs_ex, Rt_ex, Rd_ex, Func_ex, Address32_ex )
print 'Data1_ex %i | Data2_ex %i' % (Data1_ex, Data2_ex)
print 'ForwardA %i | ForwardB %i' % (ForwardA, ForwardB)
print 'ForwMux1Out %i | ForwMux2Out %i' % (ForwMux1Out, ForwMux2Out)
print '-->CONTROL'
print 'RegDst %i ALUop %s ALUSrc %i | Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
( RegDst_ex , bin(ALUop_ex, 2), ALUSrc_ex, Branch_ex, MemRead_ex, MemWrite_ex, RegWrite_ex, MemtoReg_ex)
print '--> ALU'
print 'MuxAluDataSrc %i | AluCtrl %s | AluResult_ex %i | Zero_ex %i' % (MuxAluDataSrc_ex, bin(AluControl, 4), AluResult_ex, Zero_ex)
print 'WrRegDest_ex %i' % WrRegDest_ex
if True: #if now () > 6:
#MEM
print "\n" + "." * 35 + "MEM " + "." * 35 + "\n"
print "BranchAdderO_mem %i " % (BranchAdderO_mem)
print '-->CONTROL'
print 'Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
( Branch_mem, MemRead_mem, MemWrite_mem, RegWrite_mem, MemtoReg_mem)
print '--> Branch'
print 'Branch_mem %i Zero %i | PCSrc_mem %i' % (Branch_mem, Zero_mem, PCSrc_mem)
print '--> Data mem'
print 'AluResult_mem %i | Data2_mem %i | DataMemOut_mem %i | MemW %i MemR %i' \
% (AluResult_mem, Data2_mem, DataMemOut_mem, MemWrite_mem, MemRead_mem)
print 'WrRegDest_mem %i' % WrRegDest_mem
if True: #if now() > 8:
#WB
print "\n" + "." * 35 + "WB" + "." * 35 + "\n"
print 'CONTROL --> RegW %i Mem2Reg %i ' % ( RegWrite_mem, MemtoReg_mem)
print 'DataMemOut_wb %i | AluResult_wb %i | MuxMemO_wb %i ' % (DataMemOut_wb, AluResult_wb, MuxMemO_wb)
print 'WrRegDest_wb %i | MuxMemO_wb %i' % (WrRegDest_wb, MuxMemO_wb)
return instances()
import control
from multiprocessing import Queue
from webserver import webserver
from subprocess import check_output
def server_stats():
uptime_result = str(check_output("uptime -p", shell=1).rstrip())
uptime_result = uptime_result[2:len(uptime_result) - 1]
stats = {
"uptime": uptime_result,
"led power": int(not con.safe_control.is_off),
"brightness": con.safe_control.current_brightness,
"current animation": con.animation.animation_instructions[0]
}
return stats
q = Queue()
con = control.control(q)
webserv = webserver(con.safe_control, server_stats)
print(server_stats())
con.thread.join()
webserv.thread.join()
def pipeline(clk_period=1,
Reset=Signal(intbv(0)[1:]),
Zero=Signal(intbv(0)[1:])):
"""
A DLX processor with 5 pipeline stages.
=======================================
Stages
------
[IF] -> IF/ID -> [ID] -> ID/EX -> [EX] -> EX/MEM -> [MEM] -> MEM/WB __
^ |
|_______________________________________________________|
Conventions:
------------
* Signals are in ``CamelCase``
* Instances are with ``under_score``
* The signals shared two or more stage are suffixed with the pipeline stage to which it belongs.
For example: ``PcAdderO_if`` before IF/ID latch is the same signal than
``PcAdderO_id`` after it.
"""
##############################
# clock settings
##############################
Clk = Signal(intbv(0)[1:]) # internal clock
ClkPc = Signal(intbv(0)[1:]) # frec should be almost 1/4 clk internal
clk_driver = clock_driver(Clk, clk_period)
clk_driver_pc = clock_driver(ClkPc, clk_period * 4)
####################
#feedback Signals
######################
# signals from and advanced stage which feeds a previous component
BranchAdderO_mem = Signal(intbv(0, min=MIN, max=MAX)[32:])
PCSrc_mem = Signal(
intbv(0)[1:]
) # control of mux for program_counter on IF stage - (branch or inmediante_next)
WrRegDest_wb = Signal(intbv(
0)[32:]) # register pointer where MuxMemO_wb data will be stored.
MuxMemO_wb = Signal(
intbv(0, min=MIN, max=MAX)
) # data output from WB mux connected as Write Data input on Register File (ID stage)
RegWrite_wb = Signal(intbv(0)[1:])
##############################
# IF
##############################
#instruction memory
Ip = Signal(intbv(0)[32:]) # connect PC with intruction_memory
Instruction_if = Signal(intbv(0)[32:]) # 32 bits instruction line.
im = instruction_memory(Ip, Instruction_if)
#PC
NextIp = Signal(intbv(0)[32:]) # output of mux_branch - input of pc
pc = program_counter(Clk, NextIp, Ip)
#pc_adder
INCREMENT = 1 # it's 4 in the book, but my memory it's organized in 32bits words, not bytes
PcAdderOut_if = Signal(intbv(
0)[32:]) # output of pc_adder - input0 branch_adder and mux_branch
pc_adder = ALU(Signal(0b0010), Ip, Signal(INCREMENT), PcAdderOut_if,
Signal(0)) # hardwire an ALU to works as an adder
#mux controlling next ip branches.
mux_pc_source = mux2(PCSrc_mem, NextIp, PcAdderOut_if, BranchAdderO_mem)
##############################
# IF/ID
##############################
PcAdderOut_id = Signal(intbv(0)[32:])
Instruction_id = Signal(intbv(0)[32:])
latch_if_id_ = latch_if_id(Clk, Reset, Instruction_if, PcAdderOut_if,
Instruction_id, PcAdderOut_id)
##############################
# ID
##############################
#DECODER
Opcode_id = Signal(intbv(0)[6:]) # instruction 31:26 - to Control
Rs_id = Signal(intbv(0)[5:]) # instruction 25:21 - to read_reg_1
Rt_id = Signal(
intbv(0)[5:]
) # instruction 20:16 - to read_reg_2 and mux controlled by RegDst
Rd_id = Signal(
intbv(0)[5:]) # instruction 15:11 - to the mux controlled by RegDst
Shamt_id = Signal(intbv(0)[5:]) # instruction 10:6 -
Func_id = Signal(intbv(0)[6:]) # instruction 5:0 - to ALUCtrl
Address16_id = Signal(intbv(0, min=-(2**15), max=2**15 -
1)) # instruction 15:0 - to Sign Extend
NopSignal = Signal(intbv(0)[1:])
instruction_decoder_ = instruction_dec(Instruction_id, Opcode_id, Rs_id,
Rt_id, Rd_id, Shamt_id, Func_id,
Address16_id, NopSignal)
#sign extend
Address32_id = Signal(intbv(0, min=MIN, max=MAX))
sign_extend_ = sign_extend(Address16_id, Address32_id)
#CONTROL
signals_1bit = [Signal(intbv(0)[1:]) for i in range(7)]
RegDst_id, ALUSrc_id, MemtoReg_id, RegWrite_id, MemRead_id, MemWrite_id, Branch_id = signals_1bit
ALUop_id = Signal(intbv(0)[2:])
control_ = control(Opcode_id, RegDst_id, Branch_id, MemRead_id,
MemtoReg_id, ALUop_id, MemWrite_id, ALUSrc_id,
RegWrite_id, NopSignal)
#REGISTER FILE
Data1_id = Signal(intbv(0, min=MIN, max=MAX))
Data2_id = Signal(intbv(0, min=MIN, max=MAX))
register_file_i = register_file(Clk,
Rs_id,
Rt_id,
WrRegDest_wb,
MuxMemO_wb,
RegWrite_wb,
Data1_id,
Data2_id,
depth=32)
##############################
# ID/EX
##############################
PcAdderOut_ex = Signal(intbv(0)[32:])
signals_1bit = [Signal(intbv(0)[1:]) for i in range(7)]
RegDst_ex, ALUSrc_ex, MemtoReg_ex, RegWrite_ex, MemRead_ex, MemWrite_ex, Branch_ex = signals_1bit
ALUop_ex = Signal(intbv(0)[2:])
Data1_ex = Signal(intbv(0, min=MIN, max=MAX))
Data2_ex = Signal(intbv(0, min=MIN, max=MAX))
Rs_ex = Signal(intbv(0)[5:]) # instruction 25:21 - to read_reg_1
Rt_ex = Signal(
intbv(0)[5:]
) # instruction 20:16 - to read_reg_2 and mux controlled by RegDst
Rd_ex = Signal(
intbv(0)[5:]) # instruction 15:11 - to the mux controlled by RegDst
#Shamt_ex = Signal(intbv(0)[5:]) #instruction 10:6 -
Func_ex = Signal(intbv(0)[6:]) # instruction 5:0 - to ALUCtrl
Address32_ex = Signal(intbv(0, min=MIN, max=MAX))
latch_id_ex_ = latch_id_ex(
Clk,
Reset,
PcAdderOut_id,
Data1_id,
Data2_id,
Address32_id,
Rd_id,
Rt_id,
Func_id,
RegDst_id,
ALUop_id,
ALUSrc_id, # signals to EX pipeline stage
Branch_id,
MemRead_id,
MemWrite_id, # signals to MEM pipeline stage
RegWrite_id,
MemtoReg_id, # signals to WB pipeline stage
PcAdderOut_ex,
Data1_ex,
Data2_ex,
Address32_ex,
Rd_ex,
Rt_ex,
Func_ex,
RegDst_ex,
ALUop_ex,
ALUSrc_ex, # signals to EX pipeline stage
Branch_ex,
MemRead_ex,
MemWrite_ex, # signals to MEM pipeline stage
RegWrite_ex,
MemtoReg_ex # signals to WB pipeline stage
)
##############################
# EX
##############################
BranchAdderO_ex = Signal(intbv(0, min=MIN, max=MAX)[32:])
Zero_ex = Signal(intbv(0)[1:])
AluResult_ex = Signal(intbv(0, min=MIN, max=MAX))
MuxAluDataSrc_ex = Signal(intbv(0, min=MIN, max=MAX))
WrRegDest_ex = Signal(intbv(0)[32:])
#muxer 2nd operand in ALU
mux_alu_src = mux2(ALUSrc_ex, MuxAluDataSrc_ex, Data2_ex, Address32_ex)
#Branch adder
branch_adder_ = ALU(Signal(0b0010), PcAdderOut_ex, Address32_ex,
BranchAdderO_ex, Signal(0))
#ALU Control
AluControl = Signal(intbv('1111')[4:]) # control signal to alu
alu_control_ = alu_control(ALUop_ex, Func_ex, AluControl)
#ALU
alu_ = ALU(AluControl, Data1_ex, MuxAluDataSrc_ex, AluResult_ex, Zero_ex)
#Mux RegDestiny Control Write register between rt and rd.
mux_wreg = mux2(RegDst_ex, WrRegDest_ex, Rt_ex, Rd_ex)
##############################
# EX/MEM
##############################
BranchAdderO_mem = Signal(intbv(0, min=MIN, max=MAX))
Zero_mem = Signal(intbv(0)[1:])
AluResult_mem = Signal(intbv(0, min=MIN, max=MAX))
Data2_mem = Signal(intbv(0, min=MIN, max=MAX))
WrRegDest_mem = Signal(intbv(0)[32:])
#control signals
signals_1bit = [Signal(intbv(0)[1:]) for i in range(5)]
MemtoReg_mem, RegWrite_mem, MemRead_mem, MemWrite_mem, Branch_mem = signals_1bit
latch_ex_mem_ = latch_ex_mem(
Clk,
Reset,
BranchAdderO_ex,
AluResult_ex,
Zero_ex,
Data2_ex,
WrRegDest_ex,
Branch_ex,
MemRead_ex,
MemWrite_ex, # signals to MEM pipeline stage
RegWrite_ex,
MemtoReg_ex, # signals to WB pipeline stage
BranchAdderO_mem,
AluResult_mem,
Zero_mem,
Data2_mem,
WrRegDest_mem,
Branch_mem,
MemRead_mem,
MemWrite_mem, # signals to MEM pipeline stage
RegWrite_mem,
MemtoReg_mem, # signals to WB pipeline stage
)
##############################
# MEM
##############################
DataMemOut_mem = Signal(intbv(0, min=MIN, max=MAX))
#branch AND gate
branch_and_gate = and_gate(Branch_mem, Zero_mem, PCSrc_mem)
#data memory
data_memory_ = data_memory(Clk, AluResult_mem, Data2_mem, DataMemOut_mem,
MemRead_mem, MemWrite_mem)
##############################
# EX/WB
##############################
#RegWrite_wb, on feedback signals section
MemtoReg_wb = Signal(intbv(0)[1:])
DataMemOut_wb = Signal(intbv(0, min=MIN, max=MAX))
AluResult_wb = Signal(intbv(0, min=MIN, max=MAX))
#WrRegDest_wb on feedback signals sections.
latch_mem_wb_ = latch_mem_wb(
Clk,
Reset,
DataMemOut_mem,
AluResult_mem,
WrRegDest_mem,
RegWrite_mem,
MemtoReg_mem, # signals to WB pipeline stage
DataMemOut_wb,
AluResult_wb,
WrRegDest_wb,
RegWrite_wb,
MemtoReg_wb, # signals to WB pipeline stage
)
##############################
# WB
##############################
#mux2(sel, mux_out, chan1, chan2):
mux_mem2reg_ = mux2(MemtoReg_wb, MuxMemO_wb, AluResult_wb, DataMemOut_wb)
##############################
# Forwarding unit
##############################
##############################
# hazard detection unit
##############################
if DEBUG:
@always(Clk.posedge)
def debug_internals():
sep = "\n" + "=" * 34 + " time %s " + "=" * 34
print sep % now()
#IF
print "\n" + "." * 35 + " IF " + "." * 35 + "\n"
print "PcAdderOut_if %i | BranchAdderO_mem %i | PCSrc_mem %i | NextIp %i | Ip %i" % (
PcAdderOut_if, BranchAdderO_mem, PCSrc_mem, NextIp, Ip)
print 'Instruction_if %s (%i)' % (bin(Instruction_if,
32), Instruction_if)
if True: # now () > 2:
#ID
print "\n" + "." * 35 + " ID " + "." * 35 + "\n"
print "PcAdderO_id %i | Instruction_id %s (%i) | Nop %i" % (
PcAdderOut_id, bin(Instruction_id,
32), Instruction_id, NopSignal)
print 'Op %s | Rs %i | Rt %i | Rd %i | Func %i | Addr16 %i | Addr32 %i' % \
(bin(Opcode_id, 6), Rs_id, Rt_id, Rd_id, Func_id, Address16_id, Address32_id)
print 'Data1 %i | Data2 %i' % (Data1_id, Data2_id)
print '-->CONTROL'
print 'RegDst %i ALUop %s ALUSrc %i | Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
(RegDst_id, bin(ALUop_id, 2), ALUSrc_id, Branch_id, MemRead_id, MemWrite_id, RegWrite_id, MemtoReg_id)
if True: # if now () > 4:
#EX
print "\n" + "." * 35 + " EX " + "." * 35 + "\n"
print "PcAdderO_ex %i | BranchAdderO_ex %i " % (
PcAdderOut_ex, BranchAdderO_ex)
print "Rs %i | Rt %i | Rd %i | Func %i | Addr32 %i" % (
Rs_ex, Rt_ex, Rd_ex, Func_ex, Address32_ex)
print 'Data1_ex %i | Data2_ex %i' % (Data1_ex, Data2_ex)
print '-->CONTROL'
print 'RegDst %i ALUop %s ALUSrc %i | Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
(RegDst_ex, bin(ALUop_ex, 2), ALUSrc_ex, Branch_ex, MemRead_ex, MemWrite_ex, RegWrite_ex, MemtoReg_ex)
print '--> ALU'
print 'MuxAluDataSrc %i | AluCtrl %s | AluResult_ex %i | Zero_ex %i' % (
MuxAluDataSrc_ex, bin(AluControl,
4), AluResult_ex, Zero_ex)
print 'WrRegDest_ex %i' % WrRegDest_ex
if True: # if now () > 6:
#MEM
print "\n" + "." * 35 + "MEM " + "." * 35 + "\n"
print "BranchAdderO_mem %i " % (BranchAdderO_mem)
print '-->CONTROL'
print 'Branch %i MemR %i MemW %i | RegW %i Mem2Reg %i ' % \
(Branch_mem, MemRead_mem, MemWrite_mem, RegWrite_mem, MemtoReg_mem)
print '--> Branch'
print 'Branch_mem %i Zero %i | PCSrc_mem %i' % (
Branch_mem, Zero_mem, PCSrc_mem)
print '--> Data mem'
print 'AluResult_mem %i | Data2_mem %i | DataMemOut_mem %i | MemW %i MemR %i' \
% (AluResult_mem, Data2_mem, DataMemOut_mem, MemWrite_mem, MemRead_mem)
print 'WrRegDest_mem %i' % WrRegDest_mem
if True: # if now() > 8:
#WB
print "\n" + "." * 35 + "WB" + "." * 35 + "\n"
print 'CONTROL --> RegW %i Mem2Reg %i ' % (RegWrite_mem,
MemtoReg_mem)
print 'DataMemOut_wb %i | AluResult_wb %i | MuxMemO_wb %i ' % (
DataMemOut_wb, AluResult_wb, MuxMemO_wb)
print 'WrRegDest_wb %i | MuxMemO_wb %i' % (WrRegDest_wb,
MuxMemO_wb)
return instances()
