def block(self, d, a, b): # Based on example on p133 of SPU ISA manual code = self.get_active_code() temp = code.prgm.acquire_register() spu.sfi(temp, b, 0) spu.rotm(d, a, temp) code.prgm.release_register(temp) return
def TestInt2(i0 = 0, i1 = 1):
i2 = i0 + i1
i3 = i1 + i2
code = InstructionStream()
proc = Processor()
r_loop = 4
r_address = 5
r0 = 6
r1 = 7
r2 = 8
r3 = 9
# Load arguments into a quadword
#################
# Pack quadword #
#################
def load_value_int32(code, reg, value, clear = False):
# obviously, value should be 32 bit integer
code.add(spu.ilhu(reg, value / pow(2, 16))) # immediate load halfword upper
code.add(spu.iohl(reg, value % pow(2, 16))) # immediate or halfword lower
if clear:
code.add(spu.shlqbyi(reg, reg, 12)) # shift left qw by bytes, clears right bytes
return
load_value_int32(code, r0, i0, True)
load_value_int32(code, r1, i1, True)
code.add(spu.rotqbyi(r1, r1, 12)) # rotate qw by bytes
load_value_int32(code, r2, i2, True)
code.add(spu.rotqbyi(r2, r2, 8))
load_value_int32(code, r3, i3, True)
code.add(spu.rotqbyi(r3, r3, 4))
code.add(spu.a(r0, r0, r1))
code.add(spu.a(r0, r0, r2))
code.add(spu.a(r0, r0, r3))
##########
# Main loop to calculate Fibnoccai sequence
load_value_int32(code, r_address, pow(2, 16), clear_bits = False) # start at 64K
load_value_int32(code, r_loop, 0, clear_bits = False)
start_label = code.size() + 1
code.add(spu.sfi(r_loop, r_loop, 1))
code.add(spu.brnz(r_loop, (-(next - start_label) * spu.WORD_SIZE)))
code.add(spu.stop(0x2005))
r = proc.execute(code)
# assert(r == 12)
# print 'int result:', r
return
def TestInt2(i0 = 0, i1 = 1):
i2 = i0 + i1
i3 = i1 + i2
code = InstructionStream()
proc = Processor()
r_loop = 4
r_address = 5
r0 = 6
r1 = 7
r2 = 8
r3 = 9
# Load arguments into a quadword
#################
# Pack quadword #
#################
def load_value_int32(code, reg, value, clear = False):
# obviously, value should be 32 bit integer
code.add(spu.ilhu(reg, value / pow(2, 16))) # immediate load halfword upper
code.add(spu.iohl(reg, value % pow(2, 16))) # immediate or halfword lower
if clear:
code.add(spu.shlqbyi(reg, reg, 12)) # shift left qw by bytes, clears right bytes
return
load_value_int32(code, r0, i0, True)
load_value_int32(code, r1, i1, True)
code.add(spu.rotqbyi(r1, r1, 12)) # rotate qw by bytes
load_value_int32(code, r2, i2, True)
code.add(spu.rotqbyi(r2, r2, 8))
load_value_int32(code, r3, i3, True)
code.add(spu.rotqbyi(r3, r3, 4))
code.add(spu.a(r0, r0, r1))
code.add(spu.a(r0, r0, r2))
code.add(spu.a(r0, r0, r3))
##########
# Main loop to calculate Fibnoccai sequence
load_value_int32(code, r_address, pow(2, 16), clear_bits = False) # start at 64K
load_value_int32(code, r_loop, 0, clear_bits = False)
start_label = code.size() + 1
code.add(spu.sfi(r_loop, r_loop, 1))
code.add(spu.brnz(r_loop, (-(next - start_label) * spu.WORD_SIZE)))
code.add(spu.stop(0x2005))
r = proc.execute(code)
# assert(r == 12)
# print 'int result:', r
return
