def parse_file(self, strfile, config, flags=None):
if flags is None:
Logger.error("Top module not provided")
topmodule = flags[0]
absstrfile = os.path.abspath(strfile)
directory = "/".join(absstrfile.split("/")[:-1])
filename = absstrfile.split("/")[-1]
if self.single_file:
files = [absstrfile]
else:
if self.files_from_dir:
files = [
"%s/%s" % (directory, f) for f in os.listdir(directory)
if self._get_extension(f) in self.extensions
]
else:
files = [
"%s/%s" % (directory, f) for f in list(
set(self._collect_dependencies(directory, filename)))
]
files.append(absstrfile)
command = "%s -p \"%s\"" % (CMD, "; ".join(COMMANDS))
command = command.format(FILES=" ".join(files), \
TARGET=topmodule, \
PASSES="; ".join(PASSES), \
BTORFILE=TMPFILE)
Logger.log("Command: %s" % command, 2)
print_level = 3
if not Logger.level(print_level):
saved_stdout = suppress_output()
retval = os.system(command)
if not Logger.level(print_level):
restore_output(saved_stdout)
if retval != 0:
Logger.error("Error in Verilog conversion")
parser = BTOR2Parser()
ret = parser.parse_file(TMPFILE, config)
if not Logger.level(1):
os.remove(TMPFILE)
return ret
def init_parsers():
from cosa.encoders.btor2 import BTOR2Parser
from cosa.encoders.coreir import CoreIRParser
from cosa.encoders.explicit_transition_system import ExplicitTSParser
from cosa.encoders.symbolic_transition_system import SymbolicTSParser, SymbolicSimpleTSParser
from cosa.encoders.verilog_yosys import VerilogYosysBtorParser
ModelParsersFactory.register_parser(BTOR2Parser())
ModelParsersFactory.register_parser(CoreIRParser())
ModelParsersFactory.register_parser(ExplicitTSParser())
ModelParsersFactory.register_parser(SymbolicTSParser())
ModelParsersFactory.register_parser(SymbolicSimpleTSParser())
if ModelParsersFactory.verilog_encoder == VerilogEncoder.INTERNAL:
Logger.error("Internal verilog parser support is deprecated.")
if ModelParsersFactory.verilog_encoder == VerilogEncoder.YOSYS_BTOR:
ModelParsersFactory.register_parser(VerilogYosysBtorParser())
if ModelParsersFactory.verilog_encoder == VerilogEncoder.YOSYS_COREIR:
Logger.error("Not supported")
def parse_file(self,
filepath: Path,
config: NamedTuple,
flags: str = None) -> Tuple[HTS, List[FNode], List[FNode]]:
# create copy of yosys commands (will be modified below)
# Note: This class is only instantiated once per python environment
# but we don't want subsequent calls to parse_file to be coupled
COPY_PASSES = PASSES.copy()
COPY_OPT_PASSES = OPT_PASSES.copy()
COPY_COMMANDS = COMMANDS.copy()
if flags is None:
Logger.error("Top module not provided")
if config.verific:
COPY_COMMANDS[
0] = "verific -sv2009 {FILES}; verific -import -extnets {TARGET};"
topmodule = flags[0]
abspath = filepath.absolute()
directory = filepath.parent
filename = filepath.name
if abspath.is_dir():
# TODO: Test this feature
self.files_from_dir = True
else:
self.single_file = filename.split(".")[-1] != MULTI_FILE_EXT
if config.no_arrays:
COPY_PASSES.append("memory")
else:
COPY_PASSES.append("memory -nomap")
if config.synchronize:
COPY_PASSES.append("async2sync")
if config.opt_circuit:
for op in COPY_OPT_PASSES:
COPY_PASSES.append(op)
else:
COPY_PASSES.append("flatten;")
if not config.abstract_clock:
COPY_PASSES.append("clk2fflogic;")
if config.opt_circuit:
COPY_PASSES.append("opt;;")
if self.single_file:
files = [str(abspath)]
else:
if self.files_from_dir:
files = [
str(f) for f in directory.iterdir()
if f.suffix[1:] in self.extensions
]
else:
files = []
with abspath.open("r") as source_list:
Logger.msg(
"Reading source files from \"%s\"... " % (filename), 0)
for source in source_list.read().split("\n"):
source = source.strip()
if source:
files.append(source)
command = "%s -p \"%s\"" % (CMD, "; ".join(COPY_COMMANDS))
command = command.format(FILES=" ".join(files), \
TARGET=topmodule, \
PASSES="; ".join(COPY_PASSES), \
BTORFILE=TMPFILE)
Logger.log("Command: %s" % command, 2)
print_level = 3
if not Logger.level(print_level):
saved_status = suppress_output(redirect_error=True)
retval = os.system(command)
if not Logger.level(print_level):
restore_output(saved_status)
if retval != 0:
os.system("mv %s %s" % (saved_status[0].name, YOSYSERRLOG))
Logger.error(
"Error in Verilog conversion.\nSee %s for more info." %
YOSYSERRLOG)
parser = BTOR2Parser()
ret = parser.parse_file(Path(TMPFILE), config)
if not Logger.level(1):
os.remove(TMPFILE)
return ret
def parse_model(self, \
relative_path, \
model_files, \
abstract_clock, \
symbolic_init, \
name=None, \
deterministic=False, \
boolean=False, \
no_clock=False, \
run_passes=True):
hts = HTS("System 1")
invar_props = []
ltl_props = []
models = model_files.split(MODEL_SP)
for strfile in models:
(strfile, flags) = self.get_file_flags(strfile)
filetype = strfile.split(".")[-1]
strfile = strfile.replace("~", os.path.expanduser("~"))
if strfile[0] != "/":
strfile = relative_path + strfile
parser = None
if filetype in CoreIRParser.get_extensions():
parser = CoreIRParser(abstract_clock, symbolic_init, no_clock,
run_passes)
parser.boolean = boolean
parser.deterministic = deterministic
self.parser = parser
if filetype in ExplicitTSParser.get_extensions():
parser = ExplicitTSParser()
if not self.parser:
self.parser = parser
if filetype in SymbolicTSParser.get_extensions():
parser = SymbolicTSParser()
if not self.parser:
self.parser = parser
if filetype in SymbolicSimpleTSParser.get_extensions():
parser = SymbolicSimpleTSParser()
if not self.parser:
self.parser = parser
if filetype in BTOR2Parser.get_extensions():
parser = BTOR2Parser()
if not self.parser:
self.parser = parser
if parser is not None:
if not os.path.isfile(strfile):
Logger.error("File \"%s\" does not exist" % strfile)
Logger.msg("Parsing file \"%s\"... " % (strfile), 0)
(hts_a, inv_a, ltl_a) = parser.parse_file(strfile, flags)
hts.combine(hts_a)
invar_props += inv_a
ltl_props += ltl_a
Logger.log("DONE", 0)
continue
Logger.error("Filetype \"%s\" unsupported" % filetype)
if Logger.level(1):
print(hts.print_statistics(name, Logger.level(2)))
return (hts, invar_props, ltl_props)