def __update_existing_quartus_project(self):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
fileset = solver.solve(fileset)
fileset.add(non_dependable)
prj = QuartusProject(top_mod.syn_project)
prj.read()
prj.preflow = None
prj.postflow = None
prj.add_files(fileset)
prj.emit()
def __update_existing_quartus_project(self):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
fileset = solver.solve(fileset)
fileset.add(non_dependable)
prj = QuartusProject(top_mod.syn_project)
prj.read()
prj.preflow = None
prj.postflow = None
prj.add_files(fileset)
prj.emit()
def __update_existing_ise_project(self, ise):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
dependable = solver.solve(fileset)
all_files = SourceFileSet()
all_files.add(non_dependable)
all_files.add(dependable)
prj = ISEProject(ise=ise, top_mod=self.modules_pool.get_top_module())
prj.add_files(all_files)
prj.add_libs(all_files.get_libs())
prj.load_xml(top_mod.syn_project)
prj.emit_xml(top_mod.syn_project)
def __update_existing_ise_project(self, ise):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
dependable = solver.solve(fileset)
all_files = SourceFileSet()
all_files.add(non_dependable)
all_files.add(dependable)
prj = ISEProject(ise=ise, top_mod=self.modules_pool.get_top_module())
prj.add_files(all_files)
prj.add_libs(all_files.get_libs())
prj.load_xml(top_mod.syn_project)
prj.emit_xml(top_mod.syn_project)
def generate_isim_makefile(self):
# p.info("Generating makefile for simulation.")
p.info("Generating ISE Simulation (ISim) makefile for simulation.")
solver = DependencySolver()
pool = self.modules_pool
if not pool.is_everything_fetched():
p.echo("A module remains unfetched. "
"Fetching must be done prior to makefile generation. Try issuing \"hdlmake2 --fetch\"")
p.echo(str([str(m) for m in self.modules_pool.modules if not m.isfetched]))
quit()
top_module = pool.get_top_module()
flist = pool.build_global_file_list();
flist_sorted = solver.solve(flist);
self.make_writer.generate_isim_makefile(flist_sorted, top_module)
def __create_new_quartus_project(self):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
fileset = solver.solve(fileset)
fileset.add(non_dependable)
prj = QuartusProject(top_mod.syn_project)
prj.add_files(fileset)
prj.add_initial_properties(top_mod.syn_device, top_mod.syn_grade,
top_mod.syn_package, top_mod.syn_top)
prj.preflow = None
prj.postflow = None
prj.emit()
def __create_new_ise_project(self, ise):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
fileset = solver.solve(fileset)
fileset.add(non_dependable)
prj = ISEProject(ise=ise, top_mod=self.modules_pool.get_top_module())
prj.add_files(fileset)
prj.add_libs(fileset.get_libs())
prj.add_initial_properties(syn_device=top_mod.syn_device,
syn_grade=top_mod.syn_grade,
syn_package=top_mod.syn_package,
syn_top=top_mod.syn_top)
prj.emit_xml(top_mod.syn_project)
def __create_new_ise_project(self, ise):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
fileset = solver.solve(fileset)
fileset.add(non_dependable)
prj = ISEProject(ise=ise, top_mod=self.modules_pool.get_top_module())
prj.add_files(fileset)
prj.add_libs(fileset.get_libs())
prj.add_initial_properties(syn_device=top_mod.syn_device,
syn_grade = top_mod.syn_grade,
syn_package = top_mod.syn_package,
syn_top = top_mod.syn_top)
prj.emit_xml(top_mod.syn_project)
def __create_new_quartus_project(self):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
fileset = solver.solve(fileset)
fileset.add(non_dependable)
prj = QuartusProject(top_mod.syn_project)
prj.add_files(fileset)
prj.add_initial_properties( top_mod.syn_device,
top_mod.syn_grade,
top_mod.syn_package,
top_mod.syn_top)
prj.preflow = None
prj.postflow = None
prj.emit()
def generate_vsim_makefile(self):
# p.info("Generating makefile for simulation.")
p.info("Generating ModelSim makefile for simulation.")
solver = DependencySolver()
pool = self.modules_pool
if not pool.is_everything_fetched():
p.echo("A module remains unfetched. "
"Fetching must be done prior to makefile generation")
p.echo(
str([
str(m) for m in self.modules_pool.modules
if not m.isfetched
]))
quit()
top_module = pool.get_top_module()
flist = pool.build_global_file_list()
flist_sorted = solver.solve(flist)
#self.make_writer.generate_vsim_makefile(flist_sorted, top_module)
self.make_writer.generate_vsim_makefile(flist_sorted, top_module)
def merge_cores(self):
from srcfile import VerilogFile, VHDLFile, SVFile, NGCFile
from vlog_parser import VerilogPreprocessor
solver = DependencySolver()
pool = self.modules_pool
if not pool.is_everything_fetched():
p.echo(
"A module remains unfetched. Fetching must be done prior to makefile generation"
)
p.echo(
str([
str(m) for m in self.modules_pool.modules
if not m.isfetched
]))
quit()
flist = pool.build_global_file_list()
flist_sorted = solver.solve(flist)
# if not os.path.exists(self.options.merge_cores):
# os.makedirs(self.options.merge_cores)
base = self.options.merge_cores
f_out = open(base + ".vhd", "w")
f_out.write("\n\n\n\n")
f_out.write(
"------------------------------ WARNING -------------------------------\n"
)
f_out.write(
"-- This code has been generated by hdlmake --merge-cores option --\n"
)
f_out.write(
"-- It is provided for your convenience, to spare you from adding --\n"
)
f_out.write(
"-- lots of individual source files to ISE/Modelsim/Quartus projects --\n"
)
f_out.write(
"-- mainly for Windows users. Please DO NOT MODIFY this file. If you --\n"
)
f_out.write(
"-- need to change something inside, edit the original source file --\n"
)
f_out.write(
"-- and re-genrate the merged version! --\n"
)
f_out.write(
"----------------------------------------------------------------------\n"
)
f_out.write("\n\n\n\n")
for vhdl in flist_sorted.filter(VHDLFile):
f_out.write("\n\n--- File: %s ----\n\n" % vhdl.rel_path())
f_out.write(open(vhdl.rel_path(), "r").read() + "\n\n")
#print("VHDL: %s" % vhdl.rel_path())
f_out.close()
f_out = open(base + ".v", "w")
f_out.write("\n\n\n\n")
f_out.write(
"////////////////////////////// WARNING ///////////////////////////////\n"
)
f_out.write(
"// This code has been generated by hdlmake --merge-cores option //\n"
)
f_out.write(
"// It is provided for your convenience, to spare you from adding //\n"
)
f_out.write(
"// lots of individual source files to ISE/Modelsim/Quartus projects //\n"
)
f_out.write(
"// mainly for Windows users. Please DO NOT MODIFY this file. If you //\n"
)
f_out.write(
"// need to change something inside, edit the original source file //\n"
)
f_out.write(
"// and re-genrate the merged version! //\n"
)
f_out.write(
"//////////////////////////////////////////////////////////////////////\n"
)
f_out.write("\n\n\n\n")
for vlog in flist_sorted.filter(VerilogFile):
f_out.write("\n\n// File: %s \n\n" % vlog.rel_path())
vpp = VerilogPreprocessor()
vpp.add_path(vlog.dirname)
f_out.write(vpp.preprocess(vlog.rel_path()))
f_out.close()
for ngc in flist_sorted.filter(NGCFile):
import shutil
print("NGC:%s " % ngc.rel_path())
shutil.copy(ngc.rel_path(), self.options.merge_cores + "/")
def merge_cores(self):
from srcfile import VerilogFile, VHDLFile, SVFile, NGCFile
from vlog_parser import VerilogPreprocessor
solver = DependencySolver()
pool = self.modules_pool
if not pool.is_everything_fetched():
p.echo("A module remains unfetched. Fetching must be done prior to makefile generation")
p.echo(str([str(m) for m in self.modules_pool.modules if not m.isfetched]))
quit()
flist = pool.build_global_file_list();
flist_sorted = solver.solve(flist);
# if not os.path.exists(self.options.merge_cores):
# os.makedirs(self.options.merge_cores)
base = self.options.merge_cores
f_out = open(base+".vhd", "w")
f_out.write("\n\n\n\n");
f_out.write("------------------------------ WARNING -------------------------------\n");
f_out.write("-- This code has been generated by hdlmake --merge-cores option --\n");
f_out.write("-- It is provided for your convenience, to spare you from adding --\n");
f_out.write("-- lots of individual source files to ISE/Modelsim/Quartus projects --\n");
f_out.write("-- mainly for Windows users. Please DO NOT MODIFY this file. If you --\n");
f_out.write("-- need to change something inside, edit the original source file --\n");
f_out.write("-- and re-genrate the merged version! --\n");
f_out.write("----------------------------------------------------------------------\n");
f_out.write("\n\n\n\n");
for vhdl in flist_sorted.filter(VHDLFile):
f_out.write("\n\n--- File: %s ----\n\n" % vhdl.rel_path())
f_out.write(open(vhdl.rel_path(),"r").read()+"\n\n")
#print("VHDL: %s" % vhdl.rel_path())
f_out.close()
f_out = open(base+".v", "w")
f_out.write("\n\n\n\n");
f_out.write("////////////////////////////// WARNING ///////////////////////////////\n");
f_out.write("// This code has been generated by hdlmake --merge-cores option //\n");
f_out.write("// It is provided for your convenience, to spare you from adding //\n");
f_out.write("// lots of individual source files to ISE/Modelsim/Quartus projects //\n");
f_out.write("// mainly for Windows users. Please DO NOT MODIFY this file. If you //\n");
f_out.write("// need to change something inside, edit the original source file //\n");
f_out.write("// and re-genrate the merged version! //\n");
f_out.write("//////////////////////////////////////////////////////////////////////\n");
f_out.write("\n\n\n\n");
for vlog in flist_sorted.filter(VerilogFile):
f_out.write("\n\n// File: %s \n\n" % vlog.rel_path())
vpp = VerilogPreprocessor()
vpp.add_path(vlog.dirname)
f_out.write(vpp.preprocess(vlog.rel_path()))
f_out.close()
for ngc in flist_sorted.filter(NGCFile):
import shutil
print("NGC:%s " % ngc.rel_path())
shutil.copy(ngc.rel_path(), self.options.merge_cores+"/")
