def __init__(self,d=None):
self.dev = dev_mem.dev_mem(FPGA_BASE,FPGA_SIZE)
self.api = {
'ver':self.apiversion
, 'rreg':self.apiread
, 'wreg':self.apiwrite
}
self.status(d)
self.cnt = {}
def __init__(self):
if c_system=='Linux':
self.dev = dev_mem.dev_mem(AD9360_SPI_BASE,AD9361_SPI_SIZE)
self.ref = 25e6
self.api = {
'arreg':self.apiread
, 'awreg':self.apiwrite
}
self.webapi = {
"tx":{ "set":{"freq":self.Set_Tx_freq,"gain":self.Set_Tx_Gain}
, "get":{"freq":self.Get_Tx_freq,"gain":self.Get_Tx_Gain}
}
, "rx":{ "set":{"freq":self.Set_Rx_freq,"gain":self.Set_Rx_Gain}
, "get":{"freq":self.Get_Rx_freq,"gain":self.Get_Rx_Gain}
}
};
self.order = {
'SPIWrite' : self.API_SPIWrite
, 'SPIRead' : self.API_SPIRead
, 'RESET_DUT' : self.API_RESET_DUT
, 'WAIT' : self.API_WAIT
, 'WAIT_CALDONE' : self.API_WAIT_CALDONE
}
"""
Reg 0x16
D7 D6 D5 D4 D3 D2 D1 D0
RXBB TXBB RXQuad TXQuad RXGain TXMonitor RFDC Baseband
WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 552.960 us (Done when 0x05E[7]==1)
WAIT_CALDONE RXCP,100 // Wait for CP cal to complete, Max RXCP Cal time: 737.280 (us)(Done when 0x244[7]==1)
WAIT_CALDONE TXCP,100 // Wait for CP cal to complete, Max TXCP Cal time: 737.280 (us)(Done when 0x284[7]==1)
WAIT_CALDONE RXFILTER,2000 // Wait for RX filter to tune, Max Cal Time: 89.355 us (Done when 0x016[7]==0)
WAIT_CALDONE TXFILTER,2000 // Wait for TX filter to tune, Max Cal Time: 45.502 us (Done when 0x016[6]==0)
WAIT_CALDONE BBDC,2000 // BBDC Max Cal Time: 40400.000 us. Cal done when 0x016[0]==0
WAIT_CALDONE RFDC,2000 // RFDC Max Cal Time: 549654.000 us Cal done when 0x016[1]==0
WAIT_CALDONE TXQUAD,2000 // Wait for cal to complete (Done when 0x016[4]==0)
"""
self.cal_db = {
'BBPLL' :{'reg':0x05e,'mask':0x80,'done':0x80},
'RXCP' :{'reg':0x244,'mask':0x80,'done':0x80},
'TXCP' :{'reg':0x284,'mask':0x80,'done':0x80},
'RXFILTER' :{'reg':0x016,'mask':0x80,'done':0x00},
'TXFILTER' :{'reg':0x016,'mask':0x40,'done':0x00},
'RXQUAD' :{'reg':0x016,'mask':0x20,'done':0x00},
'TXQUAD' :{'reg':0x016,'mask':0x10,'done':0x00},
'RXGAIN' :{'reg':0x016,'mask':0x08,'done':0x00},
'TXMON' :{'reg':0x016,'mask':0x04,'done':0x00},
'RFDC' :{'reg':0x016,'mask':0x02,'done':0x00},
'BBDC' :{'reg':0x016,'mask':0x01,'done':0x00}
}
self.ensm_db = ['SLEEP/WAIT','CALIBRATION','CALIBRATION', 'CALIBRATION', 'WAIT to ALERT delay', 'ALERT', 'TX', 'TX FLUSH', 'RX', 'RX FLUSH', 'FDD', 'FDD FLUSH']
self.cntr = axi2s_c.axi2s_c()
self.pll = ad9361PLL.ad9361PLL(25e6)
def __init__(self): self.dev = dev_mem.dev_mem(FPGA_BASE,FPGA_SIZE)
def __init__(self,base=OCM_BASE,size=OCM_SIZE): self.dev = dev_mem.dev_mem(base,size)
def __init__(self):
self.dev = dev_mem.dev_mem(AXIC_BASE, AXIC_SIZE)
def __init__(self):
if c_system == 'Linux':
self.dev = dev_mem.dev_mem(AD9360_SPI_BASE, AD9361_SPI_SIZE)
self.ref = 25e6
self.api = {'arreg': self.apiread, 'awreg': self.apiwrite}
self.webapi = {
"tx": {
"set": {
"freq": self.Set_Tx_freq,
"gain": self.Set_Tx_Gain
},
"get": {
"freq": self.Get_Tx_freq,
"gain": self.Get_Tx_Gain
}
},
"rx": {
"set": {
"freq": self.Set_Rx_freq,
"gain": self.Set_Rx_Gain
},
"get": {
"freq": self.Get_Rx_freq,
"gain": self.Get_Rx_Gain
}
}
}
self.order = {
'SPIWrite': self.API_SPIWrite,
'SPIRead': self.API_SPIRead,
'RESET_DUT': self.API_RESET_DUT,
'WAIT': self.API_WAIT,
'WAIT_CALDONE': self.API_WAIT_CALDONE
}
"""
Reg 0x16
D7 D6 D5 D4 D3 D2 D1 D0
RXBB TXBB RXQuad TXQuad RXGain TXMonitor RFDC Baseband
WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 552.960 us (Done when 0x05E[7]==1)
WAIT_CALDONE RXCP,100 // Wait for CP cal to complete, Max RXCP Cal time: 737.280 (us)(Done when 0x244[7]==1)
WAIT_CALDONE TXCP,100 // Wait for CP cal to complete, Max TXCP Cal time: 737.280 (us)(Done when 0x284[7]==1)
WAIT_CALDONE RXFILTER,2000 // Wait for RX filter to tune, Max Cal Time: 89.355 us (Done when 0x016[7]==0)
WAIT_CALDONE TXFILTER,2000 // Wait for TX filter to tune, Max Cal Time: 45.502 us (Done when 0x016[6]==0)
WAIT_CALDONE BBDC,2000 // BBDC Max Cal Time: 40400.000 us. Cal done when 0x016[0]==0
WAIT_CALDONE RFDC,2000 // RFDC Max Cal Time: 549654.000 us Cal done when 0x016[1]==0
WAIT_CALDONE TXQUAD,2000 // Wait for cal to complete (Done when 0x016[4]==0)
"""
self.cal_db = {
'BBPLL': {
'reg': 0x05e,
'mask': 0x80,
'done': 0x80
},
'RXCP': {
'reg': 0x244,
'mask': 0x80,
'done': 0x80
},
'TXCP': {
'reg': 0x284,
'mask': 0x80,
'done': 0x80
},
'RXFILTER': {
'reg': 0x016,
'mask': 0x80,
'done': 0x00
},
'TXFILTER': {
'reg': 0x016,
'mask': 0x40,
'done': 0x00
},
'RXQUAD': {
'reg': 0x016,
'mask': 0x20,
'done': 0x00
},
'TXQUAD': {
'reg': 0x016,
'mask': 0x10,
'done': 0x00
},
'RXGAIN': {
'reg': 0x016,
'mask': 0x08,
'done': 0x00
},
'TXMON': {
'reg': 0x016,
'mask': 0x04,
'done': 0x00
},
'RFDC': {
'reg': 0x016,
'mask': 0x02,
'done': 0x00
},
'BBDC': {
'reg': 0x016,
'mask': 0x01,
'done': 0x00
}
}
self.ensm_db = [
'SLEEP/WAIT', 'CALIBRATION', 'CALIBRATION', 'CALIBRATION',
'WAIT to ALERT delay', 'ALERT', 'TX', 'TX FLUSH', 'RX', 'RX FLUSH',
'FDD', 'FDD FLUSH'
]
self.cntr = axi2s_c.axi2s_c()
self.pll = ad9361PLL.ad9361PLL(25e6)
def __init__(self): self.dev = dev_mem.dev_mem(OCM_BASE,OCM_SIZE)
def __init__(self,base=OCM_BASE,size=OCM_SIZE): self.dev = dev_mem.dev_mem(base,size)
def __init__(self): self.dev = dev_mem.dev_mem(AXIC_BASE,AXIC_SIZE)