예제 #1
0
 def disassemble(self, address, instructions=16):
     code = []
     for n in range(address, address + instructions * 4):
         code.append(self.gameboy.cpu.memory[n])
     try:
         return disassemble(code, start=address, instructions=instructions)
     except IndexError:
         log("...")
예제 #2
0
def main():
    opt = parse_command_line_args()

    if opt.disassemble is not None:
        if opt.disassemble == "boot":
            opt.disassemble = opt.boot_rom

        binary = load_binary(opt.disassemble)
        print("Disassembly of %s\n" % os.path.relpath(opt.disassemble))
        disassemble(binary, opt.start_address)
        sys.exit(0)

    if opt.cartridge is not None:
        log("Loading boot ROM from %s" % os.path.relpath(opt.boot_rom))
        boot = load_binary(opt.boot_rom)

        log("Loading cartridge from %s" % os.path.relpath(opt.cartridge))
        binary = load_binary(opt.cartridge)
        cartridge = Cartridge(binary)
        log(cartridge)

        log("Booting Gameboy")
        gameboy = Gameboy(cartridge,
                          boot,
                          no_display=opt.no_display,
                          zoom=opt.zoom)

        if opt.skip_boot:
            set_boot(gameboy)
            gameboy.memory.boot_rom_active = False

        if opt.debug:
            Debugger(gameboy).run()
            sys.exit(0)
        else:
            try:
                gameboy.cpu.run()
            except EmulatorError as e:
                log("\n** Exception: %s" % str(e).strip())
                Debugger(gameboy).run()
            except Exception as e:
                log("\n** Exception: %s" % str(e).strip())
                gameboy.cpu.print_registers()
                log("")
                raise
예제 #3
0
def execute_test(fname, success_check, debug=0):
    # copied from https://github.com/begoon/i8080-core/blob/master/i8080_test.c
    success = 0
    # load test program
    with open(fname, 'rb+') as f:
        data = f.read()
    # init i8080 state for testing purposes
    state = cpu.State(data)
    state.memory = bytearray(0x100) + state.memory
    # inject the rom with RET at position 5 to properly handle CALL 5
    state.memory[5] = 0xC9
    state.pc = 0x100
    print(" Test suite: %s" % fname)

    # start testing
    while 1:
        if debug:
            disassembler.disassemble(state.memory, state.pc)
        if debug > 1:
            print("\tC=%d, P=%d, S=%d, Z=%d, AC=%d\n" % (state.cc.cy, state.cc.p, state.cc.s, state.cc.z, state.cc.ac))
            print("\tA %02x B %02x C %02x D %02x E %02x H %02x L %02x SP %04x\n" % (
                state.a, state.b, state.c, state.d, state.e, state.h, state.l, state.sp
            ))
        pc = state.pc
        if state.memory[state.pc] == 0x76:
            print("HLT at %04x" % pc)
            sys.exit(1)
        if pc == 5:
            if state.c == 9:
                i = state.de
                while state.memory[i] != ord('$'):
                    print(chr(state.memory[i]), end='', flush=True)
                    i += 1
                success = 1
            if state.c == 2:
                print(chr(state.e), end='', flush=True)
        cpu.emulate(state)
        if state.pc == 0:
            print("\n Jump to 0000 from %04x" % pc)
            if success_check and not success:
                # failed
                sys.exit(1)
            return
예제 #4
0
def main(obj_file: str):
    """Main function of myDisassembler

    Parameters
    ----------
    obj_file : str
        path to object file to disassemble
    """
    # load object file
    obj_instructions = read_obj(obj_file)

    # disassemble object file
    disassembled_instructions = disassemble(obj_instructions)

    # save disassembled instructions to file
    save_asm(disassembled_instructions, obj_file)
예제 #5
0
import by7efile
import disassembler
from readorc import orc

o = orc.Orc("chall2.exe")

info = o.to_dict()

text = info["segment_table"]["segments"][1]

exe = o.o.contents[text["offset"]:text["offset"] + text["size"]]

disassembler.disassemble(exe)

# read disassembly for the flag

예제 #6
0
import disassembler

def factorial(n):
    if n==0:
        return 1
    
    return n*factorial(n-1)

def main():
	print(factorial(5))

#main()
disassembler.disassemble(factorial)
disassembler.disassemble(main)
예제 #7
0
def emulate(state, debug=0, opcode=None):

    # XXX: You *really* don't wanna reach the end of the memory
    if not opcode:
        opcode = state.memory[state.pc]
        arg1 = None if (state.pc +
                        1) >= len(state.memory) else state.memory[state.pc + 1]
        arg2 = None if (state.pc +
                        2) >= len(state.memory) else state.memory[state.pc + 2]
        if debug:
            disassemble(state.memory, state.pc)
        if debug > 1:
            print("\tC=%d, P=%d, S=%d, Z=%d\n" %
                  (state.cc.cy, state.cc.p, state.cc.s, state.cc.z))
            print(
                "\tA %02x B %02x C %02x D %02x E %02x H %02x L %02x SP %04x\n"
                % (state.a, state.b, state.c, state.d, state.e, state.h,
                   state.l, state.sp))

    if opcode == 0x00:
        # NOP
        state.nop()
    elif opcode == 0x01:
        # LXI B, D16
        state.lxi('bc', arg2, arg1)
    elif opcode == 0x02:
        # STAX B
        state.stax('bc')
    elif opcode == 0x03:
        # INX B
        state.inx('bc')
    elif opcode == 0x04:
        # INR B
        state.inr('b')
    elif opcode == 0x05:
        # DCR B
        state.dcr('b')
    elif opcode == 0x06:
        # MVI B, D8
        state.mvi('b', arg1)
    elif opcode == 0x07:
        # RLC
        h = state.a >> 7
        state.cc.cy = h
        state.a = ((state.a << 1) & 0xff) | h
        state.cycles += 4
    elif opcode == 0x08:
        # NOP*
        state.nop()
    elif opcode == 0x09:
        # DAD B
        state.dad('bc')
    elif opcode == 0x0a:
        # LDAX B
        state.a = state.memory[state.bc]
        state.cycles += 7
    elif opcode == 0x0b:
        # DCX B
        state.dcx('bc')
    elif opcode == 0x0c:
        # INR C
        state.inr('c')
    elif opcode == 0x0d:
        # DCR C
        state.dcr('c')
    elif opcode == 0x0e:
        # MVI C, D8
        state.mvi('c', arg1)
    elif opcode == 0x0f:
        # RRC
        x = state.a
        state.a = ((x & 1) << 7) | (x >> 1)
        state.cc.cy = (x & 1) == 1
        state.cycles += 4
    elif opcode == 0x10:
        # NOP*
        state.nop()
    elif opcode == 0x11:
        # LXI D, D16
        state.lxi('de', arg2, arg1)
    elif opcode == 0x12:
        # STAX D
        state.stax('de')
    elif opcode == 0x13:
        # INX D
        state.inx('de')
    elif opcode == 0x14:
        # INR D
        state.inr('d')
    elif opcode == 0x15:
        # DCR D
        state.dcr('d')
    elif opcode == 0x16:
        # MVI D, D8
        state.mvi('d', arg1)
    elif opcode == 0x17:
        # RAL
        x = state.a
        state.a = ((x << 1) & 0xff) | state.cc.cy
        state.cc.cy = (x & 0x80) != 0
        state.cycles += 4
    elif opcode == 0x18:
        # NOP*
        state.nop()
    elif opcode == 0x19:
        # DAD D
        state.dad('de')
    elif opcode == 0x1a:
        # LDAX D
        state.a = state.memory[state.de]
        state.cycles += 7
    elif opcode == 0x1b:
        # DCX D
        state.dcx('de')
    elif opcode == 0x1c:
        # INR E
        state.inr('e')
    elif opcode == 0x1d:
        # DCR E
        state.dcr('e')
    elif opcode == 0x1e:
        # MVI E, D8
        state.mvi('e', arg1)
    elif opcode == 0x1f:
        # RAR
        x = state.a
        state.a = (state.cc.cy << 7) | (x >> 1)
        state.cc.cy = (x & 1) == 1
        state.cycles += 4
    elif opcode == 0x20:
        # NOP*
        state.nop()
    elif opcode == 0x21:
        # LXI H, D16
        state.lxi('hl', arg2, arg1)
    elif opcode == 0x22:
        # SHLD, adr
        adr = merge_bytes(arg2, arg1)
        state.memory[adr] = state.l
        state.memory[adr + 1] = state.h
        state.cycles += 16
        state.pc += 2
    elif opcode == 0x23:
        # INX H
        state.inx('hl')
    elif opcode == 0x24:
        # INR H
        state.inr('h')
    elif opcode == 0x25:
        # DCR H
        state.dcr('h')
    elif opcode == 0x26:
        # MVI H, D8
        state.mvi('h', arg1)
    elif opcode == 0x27:
        # DAA
        lsb = state.a & 0x0f
        if lsb > 9 or state.cc.ac:
            state.a = (state.a + 0x06) & 0xff
            state.cc.ac = (lsb + 0x06) > 0x0f
        msb = state.a >> 4
        if msb > 9 or state.cc.cy:
            state.a = (state.a + 0x60) & 0xff
            state.cc.cy = (msb + 0x06) > 0x0f
        else:
            state.cc.cy = 0
        state.cc.p = parity(state.a)
        state.cc.z = state.a == 0
        state.cc.s = (state.a & 0x80) != 0
        state.cycles += 4
    elif opcode == 0x28:
        # NOP*
        state.nop()
    elif opcode == 0x29:
        # DAD H
        state.dad('hl')
    elif opcode == 0x2a:
        # LHLD adr
        adr = merge_bytes(arg2, arg1)
        state.l = state.memory[adr]
        state.h = state.memory[adr + 1]
        state.cycles += 16
        state.pc += 2
    elif opcode == 0x2b:
        # DCX H
        state.dcx('hl')
    elif opcode == 0x2c:
        # INR L
        state.inr('l')
    elif opcode == 0x2d:
        # DCR L
        state.dcr('l')
    elif opcode == 0x2e:
        # MVI L, D8
        state.mvi('l', arg1)
    elif opcode == 0x2f:
        # CMA
        # python's ~ operator uses signed not, we want unsigned not
        state.a ^= 0xff
        state.cycles += 4
    elif opcode == 0x30:
        # NOP*
        state.nop()
    elif opcode == 0x31:
        # LXI SP, D16
        state.lxi('sp', arg2, arg1)
    elif opcode == 0x32:
        # STA adr
        adr = merge_bytes(arg2, arg1)
        state.memory[adr] = state.a
        state.pc += 2
        state.cycles += 13
    elif opcode == 0x33:
        # INX SP
        state.inx('sp')
    elif opcode == 0x34:
        # INR M
        state.inr('m')
    elif opcode == 0x35:
        # DCR M
        state.dcr('m')
    elif opcode == 0x36:
        # MVI M, D8
        state.mvi('m', arg1)
    elif opcode == 0x37:
        # STC
        state.cc.cy = 1
        state.cycles += 4
    elif opcode == 0x38:
        # NOP*
        state.nop()
    elif opcode == 0x39:
        # DAD SP
        state.dad('sp')
    elif opcode == 0x3a:
        # LDA adr
        adr = merge_bytes(arg2, arg1)
        state.a = state.memory[adr]
        state.pc += 2
        state.cycles += 13
    elif opcode == 0x3b:
        # DCX SP
        state.dcx('sp')
    elif opcode == 0x3c:
        # INR A
        state.inr('a')
    elif opcode == 0x3d:
        # DCR A
        state.dcr('a')
    elif opcode == 0x3e:
        # MVI A, D8
        state.mvi('a', arg1)
    elif opcode == 0x3f:
        # CMC
        state.cc.cy ^= 0x01
    elif opcode == 0x40:
        # MOV B, B
        state.cycles += 5
    elif opcode == 0x41:
        # MOV B, C
        state.b = state.c
        state.cycles += 5
    elif opcode == 0x42:
        # MOV B, D
        state.b = state.d
        state.cycles += 5
    elif opcode == 0x43:
        # MOV, B, E
        state.b = state.e
        state.cycles += 5
    elif opcode == 0x44:
        # MOV B, H
        state.b = state.h
        state.cycles += 5
    elif opcode == 0x45:
        # MOV B, L
        state.b = state.l
        state.cycles += 5
    elif opcode == 0x46:
        # MOV B, M
        state.b = state.memory[state.hl]
        state.cycles += 7
    elif opcode == 0x47:
        # MOV B, A
        state.b = state.a
        state.cycles += 5
    elif opcode == 0x48:
        # MOV C, B
        state.c = state.b
        state.cycles += 5
    elif opcode == 0x49:
        # MOV C, C
        state.cycles += 5
    elif opcode == 0x4a:
        # MOV C, D
        state.c = state.d
        state.cycles += 5
    elif opcode == 0x4b:
        # MOV C, E
        state.c = state.e
        state.cycles += 5
    elif opcode == 0x4c:
        # MOV C, H
        state.c = state.h
        state.cycles += 5
    elif opcode == 0x4d:
        # MOV C, L
        state.c = state.l
        state.cycles += 5
    elif opcode == 0x4e:
        # MOV C, M
        state.c = state.memory[state.hl]
        state.cycles += 7
    elif opcode == 0x4f:
        # MOV C, A
        state.c = state.a
        state.cycles += 5
    elif opcode == 0x50:
        # MOV D, B
        state.d = state.b
        state.cycles += 5
    elif opcode == 0x51:
        # MOV D, C
        state.d = state.c
        state.cycles += 5
    elif opcode == 0x52:
        # MOV D, D
        state.cycles += 5
    elif opcode == 0x53:
        # MOV D, E
        state.d = state.e
        state.cycles += 5
    elif opcode == 0x54:
        # MOV D, H
        state.d = state.h
        state.cycles += 5
    elif opcode == 0x55:
        # MOV D, L
        state.d = state.l
        state.cycles += 5
    elif opcode == 0x56:
        # MOV D, M
        state.d = state.memory[state.hl]
        state.cycles += 7
    elif opcode == 0x57:
        # MOV D, A
        state.d = state.a
        state.cycles += 5
    elif opcode == 0x58:
        # MOV E, B
        state.e = state.b
        state.cycles += 5
    elif opcode == 0x59:
        # MOV E, C
        state.e = state.c
        state.cycles += 5
    elif opcode == 0x5a:
        # MOV E, D
        state.e = state.d
        state.cycles += 5
    elif opcode == 0x5b:
        # MOV E, E
        state.cycles += 5
    elif opcode == 0x5c:
        # MOV E, H
        state.e = state.h
        state.cycles += 5
    elif opcode == 0x5d:
        # MOV E, L
        state.e = state.l
        state.cycles += 5
    elif opcode == 0x5e:
        # MOV E, M
        state.e = state.memory[state.hl]
        state.cycles += 7
    elif opcode == 0x5f:
        # MOV E, A
        state.e = state.a
        state.cycles += 5
    elif opcode == 0x60:
        # MOV H, B
        state.h = state.b
        state.cycles += 5
    elif opcode == 0x61:
        # MOV H, C
        state.h = state.c
        state.cycles += 5
    elif opcode == 0x62:
        # MOV H, D
        state.h = state.d
        state.cycles += 5
    elif opcode == 0x63:
        # MOV H, E
        state.h = state.e
        state.cycles += 5
    elif opcode == 0x64:
        # MOV H, H
        state.cycles += 5
    elif opcode == 0x65:
        # MOV H, L
        state.h = state.l
        state.cycles += 5
    elif opcode == 0x66:
        # MOV H, M
        state.h = state.memory[state.hl]
        state.cycles += 7
    elif opcode == 0x67:
        # MOV H, A
        state.h = state.a
        state.cycles += 5
    elif opcode == 0x68:
        # MOV L, B
        state.l = state.b
        state.cycles += 5
    elif opcode == 0x69:
        # MOV L, C
        state.l = state.c
        state.cycles += 5
    elif opcode == 0x6a:
        # MOV L, D
        state.l = state.d
        state.cycles += 5
    elif opcode == 0x6b:
        # MOV L, E
        state.l = state.e
        state.cycles += 5
    elif opcode == 0x6c:
        # MOV L, H
        state.l = state.h
        state.cycles += 5
    elif opcode == 0x6d:
        # MOV L, L
        state.cycles += 5
    elif opcode == 0x6e:
        # MOV L, M
        state.l = state.memory[state.hl]
        state.cycles += 7
    elif opcode == 0x6f:
        # MOV L, A
        state.l = state.a
        state.cycles += 5
    elif opcode == 0x70:
        # MOV M, B
        state.memory[state.hl] = state.b
        state.cycles += 7
    elif opcode == 0x71:
        # MOV M, C
        state.memory[state.hl] = state.c
        state.cycles += 7
    elif opcode == 0x72:
        # MOV M, D
        state.memory[state.hl] = state.d
        state.cycles += 7
    elif opcode == 0x73:
        # MOV M, E
        state.memory[state.hl] = state.e
        state.cycles += 7
    elif opcode == 0x74:
        # MOV M, H
        state.memory[state.hl] = state.h
        state.cycles += 7
    elif opcode == 0x75:
        # MOV M, L
        state.memory[state.hl] = state.l
        state.cycles += 7
    elif opcode == 0x76:
        # HLT
        state.cycles = 7
        sys.exit(0)
    elif opcode == 0x77:
        # MOV M, A
        state.memory[state.hl] = state.a
        state.cycles += 7
    elif opcode == 0x78:
        # MOV A, B
        state.a = state.b
        state.cycles += 5
    elif opcode == 0x79:
        # MOv A, C
        state.a = state.c
        state.cycles += 5
    elif opcode == 0x7a:
        # MOV A, D
        state.a = state.d
        state.cycles += 5
    elif opcode == 0x7b:
        # MOV A, E
        state.a = state.e
        state.cycles += 5
    elif opcode == 0x7c:
        # MOV A, H
        state.a = state.h
        state.cycles += 5
    elif opcode == 0x7d:
        # MOV A, L
        state.a = state.l
        state.cycles += 5
    elif opcode == 0x7e:
        # MOV A, M
        state.a = state.memory[state.hl]
        state.cycles += 7
    elif opcode == 0x7f:
        # MOV A, A
        state.cycles += 5
    elif opcode == 0x80:
        # ADD B
        state.add('b')
    elif opcode == 0x81:
        # ADD C
        state.add('c')
    elif opcode == 0x82:
        # ADD D
        state.add('d')
    elif opcode == 0x83:
        # ADD E
        state.add('e')
    elif opcode == 0x84:
        # ADD H
        state.add('h')
    elif opcode == 0x85:
        # ADD L
        state.add('l')
    elif opcode == 0x86:
        # ADD M
        state.add('m')
    elif opcode == 0x87:
        # ADD A
        state.add('a')
    elif opcode == 0x88:
        # ADC B
        state.adc('b')
    elif opcode == 0x89:
        # ADC C
        state.adc('c')
    elif opcode == 0x8a:
        # ADC D
        state.adc('d')
    elif opcode == 0x8b:
        # ADC E
        state.adc('e')
    elif opcode == 0x8c:
        # ADC H
        state.adc('h')
    elif opcode == 0x8d:
        # ADC L
        state.adc('l')
    elif opcode == 0x8e:
        # ADC M
        state.adc('m')
    elif opcode == 0x8f:
        # ADC A
        state.adc('a')
    elif opcode == 0x90:
        # SUB B
        state.sub('b')
    elif opcode == 0x91:
        # SUB C
        state.sub('c')
    elif opcode == 0x92:
        # SUB D
        state.sub('d')
    elif opcode == 0x93:
        # SUB E
        state.sub('e')
    elif opcode == 0x94:
        # SUB H
        state.sub('h')
    elif opcode == 0x95:
        # SUB L
        state.sub('l')
    elif opcode == 0x96:
        # SUB M
        state.sub('m')
    elif opcode == 0x97:
        # SUB A
        state.sub('a')
    elif opcode == 0x98:
        # SBB B
        state.sbb('b')
    elif opcode == 0x99:
        # SBB C
        state.sbb('c')
    elif opcode == 0x9a:
        # SBB D
        state.sbb('d')
    elif opcode == 0x9b:
        # SBB E
        state.sbb('e')
    elif opcode == 0x9c:
        # SBB H
        state.sbb('h')
    elif opcode == 0x9d:
        # SBB L
        state.sbb('l')
    elif opcode == 0x9e:
        # SBB M
        state.sbb('m')
    elif opcode == 0x9f:
        # SBB A
        state.sbb('a')
    elif opcode == 0xa0:
        # ANA B
        state.ana('b')
    elif opcode == 0xa1:
        # ANA C
        state.ana('c')
    elif opcode == 0xa2:
        # ANA D
        state.ana('d')
    elif opcode == 0xa3:
        # ANA E
        state.ana('e')
    elif opcode == 0xa4:
        # ANA H
        state.ana('h')
    elif opcode == 0xa5:
        # ANA L
        state.ana('l')
    elif opcode == 0xa6:
        # ANA M
        state.ana('m')
    elif opcode == 0xa7:
        # ANA A
        state.ana('a')
    elif opcode == 0xa8:
        # XRA B
        state.xra('b')
    elif opcode == 0xa9:
        # XRA C
        state.xra('c')
    elif opcode == 0xaa:
        # XRA D
        state.xra('d')
    elif opcode == 0xab:
        # XRA E
        state.xra('e')
    elif opcode == 0xac:
        # XRA H
        state.xra('h')
    elif opcode == 0xad:
        # XRA L
        state.xra('l')
    elif opcode == 0xae:
        # XRA M
        state.xra('m')
    elif opcode == 0xaf:
        # XRA A
        state.xra('a')
    elif opcode == 0xb0:
        # ORA B
        state.ora('b')
    elif opcode == 0xb1:
        # ORA C
        state.ora('c')
    elif opcode == 0xb2:
        # ORA D
        state.ora('d')
    elif opcode == 0xb3:
        # ORA E
        state.ora('e')
    elif opcode == 0xb4:
        # ORA H
        state.ora('h')
    elif opcode == 0xb5:
        # ORA L
        state.ora('l')
    elif opcode == 0xb6:
        # ORA M
        state.ora('m')
    elif opcode == 0xb7:
        # ORA A
        state.ora('a')
    elif opcode == 0xb8:
        # CMP B
        state.cmp('b')
    elif opcode == 0xb9:
        # CMP C
        state.cmp('c')
    elif opcode == 0xba:
        # CMP D
        state.cmp('d')
    elif opcode == 0xbb:
        # CMP E
        state.cmp('e')
    elif opcode == 0xbc:
        # CMP H
        state.cmp('h')
    elif opcode == 0xbd:
        # CMP L
        state.cmp('l')
    elif opcode == 0xbe:
        # CMP M
        state.cmp('m')
    elif opcode == 0xbf:
        # CMP A
        state.cmp('a')
    elif opcode == 0xc0:
        # RNZ
        return state.ret('z', True)
    elif opcode == 0xc1:
        # POP B
        state.pop('bc')
    elif opcode == 0xc2:
        # JNZ adr
        return state.jmp(merge_bytes(arg2, arg1), 'z', True)
    elif opcode == 0xc3:
        # JMP adr
        return state.jmp(merge_bytes(arg2, arg1))
    elif opcode == 0xc4:
        # CNZ adr
        return state.call(merge_bytes(arg2, arg1), 'z', True)
    elif opcode == 0xc5:
        # PUSH B
        state.push('bc')
    elif opcode == 0xc6:
        # ADI byte
        state.add(arg1)
        state.pc += 1
    elif opcode == 0xc7:
        # RST 0
        return state.rst(0)
    elif opcode == 0xc8:
        # RZ
        return state.ret('z')
    elif opcode == 0xc9:
        # RET
        return state.ret()
    elif opcode == 0xca:
        # JZ adr
        return state.jmp(merge_bytes(arg2, arg1), 'z')
    elif opcode == 0xcc:
        # CZ adr
        return state.call(merge_bytes(arg2, arg1), 'z')
    elif opcode == 0xcd:
        # CALL adr
        return state.call(merge_bytes(arg2, arg1))
    elif opcode == 0xce:
        # ACI D8
        state.adc(arg1)
        state.pc += 1
    elif opcode == 0xcf:
        # RST 1
        return state.rst(1)
    elif opcode == 0xd0:
        # RNC
        return state.ret('cy', True)
    elif opcode == 0xd1:
        # POP D
        state.pop('de')
    elif opcode == 0xd2:
        # JNC adr
        return state.jmp(merge_bytes(arg2, arg1), 'cy', True)
    elif opcode == 0xd3:
        # OUT byte
        bus.write(arg1, state.a)
        state.pc += 1
        state.cycles += 10
    elif opcode == 0xd4:
        # CNC adr
        return state.call(merge_bytes(arg2, arg1), 'cy', True)
    elif opcode == 0xd5:
        # PUSH D
        state.push('de')
    elif opcode == 0xd6:
        # SUI D8
        state.sub(arg1)
        state.pc += 1
    elif opcode == 0xd7:
        # RST 2
        return state.rst(2)
    elif opcode == 0xd8:
        # RC
        return state.ret('cy')
    elif opcode == 0xd9:
        # RET*
        return state.ret()
    elif opcode == 0xda:
        # JC adr
        return state.jmp(merge_bytes(arg2, arg1), 'cy')
    elif opcode == 0xdb:
        # IN D8
        state.a = bus.read(arg1)
        state.pc += 1
        state.cycles += 10
    elif opcode == 0xdc:
        # CC adr
        return state.call(merge_bytes(arg2, arg1), 'cy')
    elif opcode == 0xdd:
        # CALL* adr
        return state.call(merge_bytes(arg2, arg1))
    elif opcode == 0xde:
        # SBI D8
        state.sbb(arg1)
        state.pc += 1
    elif opcode == 0xdf:
        # RST 3
        return state.rst(3)
    elif opcode == 0xe0:
        # RPO
        return state.ret('p', True)
    elif opcode == 0xe1:
        # POP H
        state.pop('hl')
    elif opcode == 0xe2:
        # JPO adr
        return state.jmp(merge_bytes(arg2, arg1), 'p', True)
    elif opcode == 0xe3:
        # XTHL
        state.l, state.memory[state.sp] = state.memory[state.sp], state.l
        state.h, state.memory[state.sp + 1] = state.memory[state.sp +
                                                           1], state.h
        state.cycles += 18
    elif opcode == 0xe4:
        # CPO adr
        return state.call(merge_bytes(arg2, arg1), 'p', True)
    elif opcode == 0xe5:
        # PUSH H
        state.push('hl')
    elif opcode == 0xe6:
        # ANI byte
        state.ana(arg1)
        state.pc += 1
    elif opcode == 0xe7:
        return state.rst(4)
    elif opcode == 0xe8:
        # RPE
        return state.ret('p')
    elif opcode == 0xe9:
        # PCHL
        state.pc = state.hl
        state.cycles += 5
        return
    elif opcode == 0xea:
        # JPE adr
        return state.jmp(merge_bytes(arg2, arg1), 'p')
    elif opcode == 0xeb:
        # XCHG
        state.hl, state.de = state.de, state.hl
        state.cycles += 5
    elif opcode == 0xec:
        # CPE adr
        return state.call(merge_bytes(arg2, arg1), 'p')
    elif opcode == 0xed:
        # CALL* adr
        return state.call(merge_bytes(arg2, arg1))
    elif opcode == 0xee:
        # XRI D8
        state.xra(arg1)
        state.pc += 1
    elif opcode == 0xef:
        # RST 5
        return state.rst(5)
    elif opcode == 0xf0:
        # RP
        return state.ret('s', True)
    elif opcode == 0xf1:
        # POP PSW
        state.pop('psw')
    elif opcode == 0xf2:
        # JP adr
        return state.jmp(merge_bytes(arg2, arg1), 's', True)
    elif opcode == 0xf3:
        # DI
        state.int_enable = 0
        state.cycles += 4
    elif opcode == 0xf4:
        # CP adr
        return state.call(merge_bytes(arg2, arg1), 's', True)
    elif opcode == 0xf5:
        # PUSH PSW
        state.push('psw')
    elif opcode == 0xf6:
        # ORI D8
        state.ora(arg1)
        state.pc += 1
    elif opcode == 0xf7:
        # RST 6
        return state.rst(6)
    elif opcode == 0xf8:
        # RM
        return state.ret('s')
    elif opcode == 0xf9:
        # SPHL
        state.sp = state.hl
    elif opcode == 0xfa:
        # JM adr
        return state.jmp(merge_bytes(arg2, arg1), 's')
    elif opcode == 0xfb:
        # EI
        state.int_enable = 1
        state.cycles += 4
    elif opcode == 0xfc:
        # CM adr
        return state.call(merge_bytes(arg2, arg1), 's')
    elif opcode == 0xfd:
        # CALL* adr
        return state.call(merge_bytes(arg2, arg1))
    elif opcode == 0xfe:
        # CPI, D8
        state.cmp(arg1)
        state.pc += 1
    elif opcode == 0xff:
        # RST 7
        return state.rst(7)
    else:
        raise NotImplementedError("opcode %02x is not implemented" % opcode)

    state.pc += 1
예제 #8
0
import disassembler

def reverse(lst):
	if len(lst) == 0:
		return []

	return reverse(lst[1:])+[lst[0]]

def main():

	print(reverse([1,2,3]))

#main()
disassembler.disassemble(reverse)
disassembler.disassemble(main)
예제 #9
0
파일: py6502.py 프로젝트: napobear/py6502
    infile = outfile
        
if args.disassemble:
    if not args.quiet:
        print ("Disassembling...")
    try:
        f = open(infile, "r")
        code = json.load(f)
        f.close()
    except:
        print ("Error: Could not decode input file: " + infile)
        sys.exit()

    disassembler = disassembler.Disassembler()
    disassembler.disassemble(code)

if args.execute or args.trace:
    try:
        f = open(infile, "r")
        code = json.load(f)
        f.close()
    except:
        print ("Error: Could not decode input file: " + infile)
        sys.exit()

    if not args.quiet:
        print ("Executing...")
    action = simulator.Simulator(code)
    action.run(args.trace)
예제 #10
0
     if (DECODE_ENABLE):
         if WRITE_TO_FILE:
             decode.write(str(parts[1]) + '\n')
 if (len(parts) == 3 and parts[1] == 'hex '):
     if (c == content[-1]):
         if WRITE_TO_FILE:
             target.write(str(parts[2]))
     else:
         if WRITE_TO_FILE:
             target.write(str(parts[2]) + ',')
         # decode instructions
         if (DECODE_ENABLE and dinsn):
             if WRITE_TO_FILE:
                 decode.write('{0: <12}'.format(str(parts[2])) +
                              ': ')
             insnlist = disassemble(parts[2])
             if (insnlist[0] == 'unknown'):
                 print hex(int(parts[2]))
                 quit()
             for i in insnlist:
                 if WRITE_TO_FILE:
                     decode.write(i + ' ')
             if insnlist[0] not in opcodeSet:
                 opcodeSet[insnlist[0]] = 1
             else:
                 opcodeSet[insnlist[0]] += 1
             if WRITE_TO_FILE:
                 decode.write('\n')
             dinsn = False
 if (DECODE_ENABLE):
     if (len(parts) == 3
예제 #11
0
import disassembler
import sys

def main():
	x = "Test"
	print(x)

if len(sys.argv) == 1:
	main()
else:
	disassembler.disassemble(main);
예제 #12
0
        def getX(self):
            return self.x

    a = A(5, 3)

    b = B(5)

    print(a)
    print(type(a))
    print(type(A))
    print(type(6))

    slope = a.slope()

    bx = b.getX()

    bx2 = B.getX(b)

    slope2 = A.slope(a)

    print(slope, slope2, bx, bx2)


if len(sys.argv) == 1:
    main()
else:
    disassembler.disassemble(Base)
    disassembler.disassemble(A)
    disassembler.disassemble(main)
예제 #13
0
import disassembler


def main():
    x = int(
        input("Ingrese le valor del al cual le desea sacar el factorial: "))
    print(factorial(x))


def factorial(x: int):
    if (x == 1):
        return 1
    else:
        return factorial(x - 1) * x


disassembler.disassemble(main)
disassembler.disassemble(factorial)
예제 #14
0
         target.write(str(parts[1]) + ',')
     if (DECODE_ENABLE):
         if WRITE_TO_FILE: 
             decode.write(str(parts[1]) + '\n')
 if (len(parts) == 3 and parts[1] == 'data'):
     if (c == content[-1]):
         if WRITE_TO_FILE: 
             target.write(str(parts[2]))
     else:
         if WRITE_TO_FILE: 
             target.write(str(parts[2]) + ',')
         # decode instructions
         if (DECODE_ENABLE and dinsn):
             if WRITE_TO_FILE: 
                 decode.write('{0: <12}'.format(str(parts[2]))+': ')
             insnlist = disassemble(hex(int(parts[2])))
             if (insnlist[0] == 'unknown'):
                 print hex(int(parts[2]))
                 quit()
             for i in insnlist:
                 if WRITE_TO_FILE: 
                     decode.write(i+' ')
             if insnlist[0] not in opcodeSet:
                 opcodeSet[insnlist[0]] = 1
             else:
                 opcodeSet[insnlist[0]] += 1
             if WRITE_TO_FILE: 
                 decode.write('\n')
             dinsn = False
 if (DECODE_ENABLE):
     if (len(parts) == 3 and str(parts[2]).find('icpu_dat_i') != -1):
예제 #15
0
import disassembler
import sys


def funA(x, y):
    z = 0
    while x < y:
        z = z + x
        print(x, y, z)
        x = x + 1

    return z


def main():
    x = int(input("Please enter an integer: "))
    y = int(input("Please enter an integer: "))

    z = funA(x, y)
    print("The answer is", z)


if len(sys.argv) == 1:
    main()
else:
    disassembler.disassemble(funA)
    disassembler.disassemble(main)
예제 #16
0
import disassembler
import sys

def f(x,y):
    if x==0:
        return y
    else:
        return g(x, x*y)

def g(x,y):
    return f(x-1,y)

def main():
    print(f(10,5))

if len(sys.argv) == 1:
	main()
else:
	disassembler.disassemble(f)
	disassembler.disassemble(g)
	disassembler.disassemble(main)
예제 #17
0
        self.food = 0

    def eat(self):
        self.food = self.food + 1

    def speak(self):
        print(self.name, "is an animal")


class Dog(Animal):
    def __init__(self, name):
        super().__init__(name)

    def speak(self):
        print(self.name, "says woof!")


def main():
    mesa = Dog("Mesa")

    mesa.eat()
    mesa.speak()


if len(sys.argv) == 1:
    main()
else:
    disassembler.disassemble(Animal)
    disassembler.disassemble(Dog)
    disassembler.disassemble(main)
예제 #18
0
import disassembler
import sys

def reverse(lst):
	if len(lst) == 0:
		return []

	return reverse(lst[1:])+[lst[0]]

def main():

	print(reverse([1,2,3]))

if len(sys.argv) == 1:
	main()
else:
	disassembler.disassemble(reverse)
	disassembler.disassemble(main)
예제 #19
0
import disassembler
import sys


def fact(n):
    if n == 0:
        return 1
    else:
        return n * fact(n - 1)


def main():
    print(fact(5))


if len(sys.argv) == 1:
    main()
else:
    disassembler.disassemble(fact)
    disassembler.disassemble(main)
예제 #20
0
import disassembler

def main():
	x = "How's it going?"

	y = x + " I am trying to get this \"program\" to work!"

	print(y)

#main()
disassembler.disassemble(main)
예제 #21
0
def gcd(x, y):
    if x==0:
        return y
    return gcd(y%x, x)

class Rational:
    def __init__(self, numerator, denominator):
        self.numerator = numerator//gcd(numerator, denominator)
        self.denominator = denominator//gcd(numerator, denominator)
        
    def getNumerator(self):
        return self.numerator
    def getDenominator(self):
        return self.denominator

    def __mul__(self, other):
        return Rational(self.getNumerator()*other.getNumerator(), self.getDenominator()*other.getDenominator())
    def __add__(self, other):
        return Rational((self.getNumerator()* other.getDenominator() + other.getNumerator()* self.getDenominator()), (self.getDenominator()* other.getDenominator()))
    
    def __str__(self):
        return str(self.numerator) + "/" + str(self.denominator)    
        
def main():
    print(Rational(1,2)+Rational(2,3))
    print(Rational(1,2)*Rational(2,3))
disassembler.disassemble(gcd)   
disassembler.disassemble(Rational)
disassembler.disassemble(main)
예제 #22
0
import disassembler


def main():

    x = input("Please enter a string: ")
    for a in x.split():
        print(a)


disassembler.disassemble(main)
예제 #23
0
파일: testCoCo1.py 프로젝트: 8l/CoCo
import disassembler

def funA(x,y):
    z = 0
    while x < y:
        z = z + x
        print(x,y,z)
        x = x + 1
        
    return z

def main():
    x = int(input("Please enter an integer: "))
    y = int(input("Please enter an integer: "))
    
    z = funA(x,y)
    print("The answer is",z)
    
 
def callit():    
    if __name__ == "__main__":
        main()

#callit()

disassembler.disassemble(funA)
disassembler.disassemble(main)