def i_adc(self, op): dst = self.getOperValue(op, 0) src = self.getOperValue(op, 1) # PDE if dst == None or src == None: self.undefFlags() self.setOperValue(op, 0, None) return cf = 0 if self.getFlag(EFLAGS_CF): cf = 1 dstsize = op.opers[0].tsize srcsize = op.opers[1].tsize if (isinstance(op.opers[1], i386ImmOper) and srcsize < dstsize): src = e_bits.sign_extend(src, srcsize, dstsize) srcsize = dstsize #FIXME perhaps unify the add/adc flags/arith code res = dst + src + cf tsize = op.opers[0].tsize self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(res, tsize)) self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(res)) self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(src, dst)) self.setFlag(EFLAGS_ZF, not res) self.setFlag(EFLAGS_SF, e_bits.is_signed(res, tsize)) self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(res, tsize)) self.setOperValue(op, 0, res)
def i_adc(self, op): dst = self.getOperValue(op, 0) src = self.getOperValue(op, 1) cf = 0 if self.getFlag(EFLAGS_CF): cf = 1 dsize = op.opers[0].tsize ssize = op.opers[1].tsize sdst = e_bits.signed(dst, dsize) ssrc = e_bits.signed(src, ssize) if (isinstance(op.opers[1], i386ImmOper) and ssize < dsize): src = e_bits.sign_extend(src, ssize, dsize) ssize = dsize #FIXME perhaps unify the add/adc flags/arith code res = dst + src + cf sres = sdst + ssrc + cf tsize = op.opers[0].tsize self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(res, tsize)) self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(res)) self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(src, dst)) self.setFlag(EFLAGS_ZF, not res) self.setFlag(EFLAGS_SF, e_bits.is_signed(res, tsize)) self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(sres, dsize)) self.setOperValue(op, 0, res)
def i_add(self, op): dst = self.getOperValue(op, 0) src = self.getOperValue(op, 1) dsize = op.opers[0].tsize ssize = op.opers[1].tsize #FIXME PDE and flags if dst == None or src == None: self.undefFlags() self.setOperValue(op, 0, None) return if dsize > ssize: src = e_bits.sign_extend(src, ssize, dsize) ssize = dsize udst = e_bits.unsigned(dst, dsize) usrc = e_bits.unsigned(src, ssize) sdst = e_bits.signed(dst, dsize) ssrc = e_bits.signed(src, ssize) ures = udst + usrc sres = sdst + ssrc self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(ures, dsize)) self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(ures)) self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(src, dst)) self.setFlag(EFLAGS_ZF, not ures) self.setFlag(EFLAGS_SF, e_bits.is_signed(ures, dsize)) self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(sres, dsize)) self.setOperValue(op, 0, ures)
def i_add(self, op): dst = self.getOperValue(op, 0) src = self.getOperValue(op, 1) dsize = op.opers[0].tsize ssize = op.opers[1].tsize if dsize > ssize: src = e_bits.sign_extend(src, ssize, dsize) ssize = dsize udst = e_bits.unsigned(dst, dsize) usrc = e_bits.unsigned(src, ssize) sdst = e_bits.signed(dst, dsize) ssrc = e_bits.signed(src, ssize) ures = udst + usrc sres = sdst + ssrc self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(ures, dsize)) self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(ures)) self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(src, dst)) self.setFlag(EFLAGS_ZF, not ures) self.setFlag(EFLAGS_SF, e_bits.is_signed(ures, dsize)) self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(sres, dsize)) self.setOperValue(op, 0, ures)
def i_and(self, op): src = self.getOperValue(op, 0) dst = self.getOperValue(op, 1) uval = dst & src self.setOperValue(op, 1, uval) osize = op.opers[1].tsize self.setFlag(REG_SR_V, e_bits.is_signed_overflow(uval, osize)) self.setFlag(REG_SR_Z, not uval) self.setFlag(REG_SR_N, uval > e_bits.s_maxes[osize]) self.setFlag(REG_SR_C, e_bits.is_aux_carry(uval, 1))
def i_and(self, op): src = self.getOperValue(op, 0) dst = self.getOperValue(op, 1) uval = dst&src self.setOperValue(op, 1, uval) osize = op.opers[1].tsize self.setFlag(REG_SR_V, e_bits.is_signed_overflow(uval, osize)) self.setFlag(REG_SR_Z, not uval) self.setFlag(REG_SR_N, uval > e_bits.s_maxes[osize]) self.setFlag(REG_SR_C, e_bits.is_aux_carry(uval, 1))
def i_bit(self, op): bit = self.getOperValue(op, 0) dst = self.getOperValue(op, 1) val = dst & bit size = 2 if op.iflags & IF_BYTE: size = 1 self.setFlag(REG_SR_V, e_bits.is_signed_overflow(val, size)) self.setFlag(REG_SR_Z, not val) self.setFlag(REG_SR_N, val < 0) self.setFlag(REG_SR_C, e_bits.is_aux_carry(val, 1))
def i_rra(self, op): oper = self.getOperValue(op, 0) osize = op.opers[0].tsize # tsize needs to be correct! print "op: %s tsize: %s" % (op, osize) shift = (osize*8)-1 uval = ((oper&1)<<shift | oper>>1) self.setOperValue(op, 0, uval) self.setFlag(REG_SR_V, e_bits.is_signed_overflow(uval, osize)) self.setFlag(REG_SR_Z, not uval) self.setFlag(REG_SR_N, uval > e_bits.s_maxes[osize]) self.setFlag(REG_SR_C, e_bits.is_aux_carry(uval, 1))
def i_rra(self, op): oper = self.getOperValue(op, 0) osize = op.opers[0].tsize # tsize needs to be correct! print "op: %s tsize: %s" % (op, osize) shift = (osize * 8) - 1 uval = ((oper & 1) << shift | oper >> 1) self.setOperValue(op, 0, uval) self.setFlag(REG_SR_V, e_bits.is_signed_overflow(uval, osize)) self.setFlag(REG_SR_Z, not uval) self.setFlag(REG_SR_N, uval > e_bits.s_maxes[osize]) self.setFlag(REG_SR_C, e_bits.is_aux_carry(uval, 1))
def i_sxt(self, op): oper = self.getOperValue(op, 0) osize = 1 # must be for msp430 to sign extend smax = e_bits.s_maxes[osize] umax = e_bits.u_maxes[2] if oper > smax: ubits = smax ^ (umax-1) oper |= ubits self.setOperValue(op, 0, oper) self.setFlag(REG_SR_V, e_bits.is_signed_overflow(oper, osize)) self.setFlag(REG_SR_Z, not oper) self.setFlag(REG_SR_N, oper > e_bits.s_maxes[osize]) self.setFlag(REG_SR_C, e_bits.is_aux_carry(oper, 1))
def i_sxt(self, op): oper = self.getOperValue(op, 0) osize = 1 # must be for msp430 to sign extend smax = e_bits.s_maxes[osize] umax = e_bits.u_maxes[2] if oper > smax: ubits = smax ^ (umax - 1) oper |= ubits self.setOperValue(op, 0, oper) self.setFlag(REG_SR_V, e_bits.is_signed_overflow(oper, osize)) self.setFlag(REG_SR_Z, not oper) self.setFlag(REG_SR_N, oper > e_bits.s_maxes[osize]) self.setFlag(REG_SR_C, e_bits.is_aux_carry(oper, 1))
def i_inc(self, op): if op.iflags & IF_BYTE: size = BYTE size = WORD #size = op.opers[0].tsize val = self.getOperValue(op, 0) sval = e_bits.signed(val, size) sval += 1 self.setOperValue(op, 0, sval) # Another arithmetic op where doing signed and unsigned is easier ;) self.setFlag(REG_SR_V, e_bits.is_signed_overflow(sval, size)) self.setFlag(REG_SR_Z, not sval) self.setFlag(REG_SR_N, sval < 0) self.setFlag(REG_SR_C, e_bits.is_aux_carry(val, 1))
def intSubBase(self, src, dst, ssize, dsize): usrc = e_bits.unsigned(src, ssize) udst = e_bits.unsigned(dst, dsize) ssrc = e_bits.signed(src, ssize) sdst = e_bits.signed(dst, dsize) ures = udst - usrc sres = sdst - ssrc #print "dsize/ssize: %d %d" % (dsize, ssize) #print "unsigned: %d %d %d" % (usrc, udst, ures) #print "signed: %d %d %d" % (ssrc, sdst, sres) self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(sres, dsize)) self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(usrc, udst)) self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(ures, dsize)) self.setFlag(EFLAGS_SF, e_bits.is_signed(ures, dsize)) self.setFlag(EFLAGS_ZF, not sres) self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(ures)) return ures