def doFlags(self, flagtup):
(ssize, dsize, sres, ures, sdst, udst) = flagtup
self.setFlag(CCR_H, e_bits.is_signed_half_carry(ures, dsize, udst))
self.setFlag(CCR_C, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(CCR_Z, not ures)
self.setFlag(CCR_N, e_bits.is_signed(ures, dsize))
self.setFlag(CCR_V, e_bits.is_signed_overflow(sres, dsize))
def doFlags(self, flagtup):
(ssize, dsize, sres, ures, sdst, udst) = flagtup
self.setFlag(h8_regs.CCR_H, e_bits.is_signed_half_carry(ures, dsize, udst))
self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(h8_regs.CCR_Z, not ures)
self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, dsize))
self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(sres, dsize))
def i_add(self, op):
(ssize, dsize, sres, ures, sdst, udst) = self.integerAddition(op)
self.setOperValue(op, 1, ures)
# FIXME: test and validate
self.setFlag(CCR_H, e_bits.is_signed_half_carry(sres, dsize, sdst))
self.setFlag(CCR_C, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(CCR_Z, not ures)
self.setFlag(CCR_N, e_bits.is_signed(ures, dsize))
self.setFlag(CCR_V, e_bits.is_signed_overflow(sres, dsize))
def i_add(self, op):
(ssize, dsize, sres, ures, sdst, udst) = self.integerAddition(op)
self.setOperValue(op, 1, ures)
# FIXME: test and validate
self.setFlag(h8_regs.CCR_H, e_bits.is_signed_half_carry(sres, dsize, sdst))
self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(h8_regs.CCR_Z, not ures)
self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, dsize))
self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(sres, dsize))
def i_neg(self, op):
dsize = op.opers[0].tsize
oper = self.getOperValue(op, 0)
oper = e_bits.signed(oper, dsize)
oper = -oper
self.setOperValue(op, 0, oper)
self.setFlag(CCR_H, e_bits.is_signed_half_carry(oper, dsize, oper))
self.setFlag(CCR_N, e_bits.is_signed(oper, dsize))
self.setFlag(CCR_Z, not oper)
self.setFlag(CCR_V, e_bits.is_signed_overflow(oper, dsize))
self.setFlag(CCR_C, e_bits.is_unsigned_carry(oper, dsize))
def i_neg(self, op):
dsize = op.opers[0].tsize
oper = self.getOperValue(op, 0)
oper = e_bits.signed(oper, dsize)
oper = -oper
self.setOperValue(op, 0, oper)
self.setFlag(h8_regs.CCR_H, e_bits.is_signed_half_carry(oper, dsize, oper))
self.setFlag(h8_regs.CCR_N, e_bits.is_signed(oper, dsize))
self.setFlag(h8_regs.CCR_Z, not oper)
self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(oper, dsize))
self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(oper, dsize))