def i_rcl(self, op):
dsize = op.opers[0].tsize
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
src = src & 0x1f
# Put that carry bit up there.
if self.getFlag(EFLAGS_CF):
dst = dst | (1 << (8 * dsize))
# Add one to account for carry
x = ((8*dsize) - src) + 1
#FIXME is this the one that can end up negative?
res = (dst << src) | (dst >> x)
cf = (res >> (8*dsize)) & 1
res = e_bits.unsigned(res, dsize)
self.setFlag(EFLAGS_CF, cf)
if src == 1:
m1 = e_bits.msb(res, dsize)
m2 = e_bits.msb(res << 1, dsize)
self.setFlag(EFLAGS_OF, m1 ^ m2)
self.setOperValue(op, 0, res)
def i_rcl(self, op):
dsize = op.opers[0].tsize
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
src = src & 0x1f
# Put that carry bit up there.
if self.getFlag(EFLAGS_CF):
dst = dst | (1 << (8 * dsize))
# Add one to account for carry
x = ((8 * dsize) - src) + 1
#FIXME is this the one that can end up negative?
res = (dst << src) | (dst >> x)
cf = (res >> (8 * dsize)) & 1
res = e_bits.unsigned(res, dsize)
self.setFlag(EFLAGS_CF, cf)
if src == 1:
m1 = e_bits.msb(res, dsize)
m2 = e_bits.msb(res << 1, dsize)
self.setFlag(EFLAGS_OF, m1 ^ m2)
self.setOperValue(op, 0, res)
def i_inv(self, op):
dst = self.getOperValue(op, 0)
size = self.getOperSize(op)
udst = e_bits.unsigned(dst, size)
res = e_bits.unsigned(~dst, size)
self.setFlag(SR_N, e_bits.msb(res, size))
self.setFlag(SR_Z, res == 0)
self.setFlag(SR_C, res != 0)
self.setFlag(SR_V, e_bits.msb(udst, size))
self.setOperValue(op, 0, res)
def i_inv(self, op):
dst = self.getOperValue(op, 0)
size = self.getOperSize(op)
udst = e_bits.unsigned(dst, size)
res = e_bits.unsigned(~dst, size)
self.setFlag(SR_N, e_bits.msb(res, size))
self.setFlag(SR_Z, res == 0)
self.setFlag(SR_C, res != 0)
self.setFlag(SR_V, e_bits.msb(udst, size))
self.setOperValue(op, 0, res)
def i_sal(self, op):
dsize = op.opers[0].tsize
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
src = src & 0x1f
# According to intel manual, if src == 0 eflags are not changed
if src == 0:
return
res = dst << src
cf = (res >> 8*dsize) & 1
res = e_bits.unsigned(res, dsize)
self.setFlag(EFLAGS_CF, cf)
self.setFlag(EFLAGS_SF, e_bits.is_signed(res, dsize))
self.setFlag(EFLAGS_ZF, not res)
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(res))
if src == 1:
self.setFlag(EFLAGS_OF, not e_bits.msb(res, dsize) == cf)
else:
self.setFlag(EFLAGS_OF, 0) # Undefined, but zero'd on core2 duo
self.setOperValue(op, 0, res)
def i_sar(self, op):
dsize = op.opers[0].tsize
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
src = src & 0x1f
# According to intel manual, if src == 0 eflags are not changed
if src == 0:
return
signed = e_bits.msb(dst, dsize)
res = dst >> src
cf = (dst >> (src - 1)) & 1
# If it was signed, we need to fill in all those bits we
# shifted off with ones.
if signed:
x = (8 * dsize) - src
umax = e_bits.u_maxes[dsize]
res |= (umax >> x) << x
res = e_bits.unsigned(res, dsize)
self.setFlag(EFLAGS_CF, cf)
self.setFlag(EFLAGS_SF, e_bits.is_signed(res, dsize))
self.setFlag(EFLAGS_ZF, not res)
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(res))
if src == 1:
self.setFlag(EFLAGS_OF, False)
else:
self.setFlag(EFLAGS_OF, 0) # Undefined, but zero'd on core2 duo
self.setOperValue(op, 0, res)
def i_sar(self, op):
dsize = op.opers[0].tsize
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
src = src & 0x1f
# According to intel manual, if src == 0 eflags are not changed
if src == 0:
return
signed = e_bits.msb(dst, dsize)
res = dst >> src
cf = (dst >> (src-1)) & 1
# If it was signed, we need to fill in all those bits we
# shifted off with ones.
if signed:
x = (8*dsize) - src
umax = e_bits.u_maxes[dsize]
res |= (umax >> x) << x
res = e_bits.unsigned(res, dsize)
self.setFlag(EFLAGS_CF, cf)
self.setFlag(EFLAGS_SF, e_bits.is_signed(res, dsize))
self.setFlag(EFLAGS_ZF, not res)
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(res))
if src == 1:
self.setFlag(EFLAGS_OF, False)
else:
self.setFlag(EFLAGS_OF, 0) # Undefined, but zero'd on core2 duo
self.setOperValue(op, 0, res)
def i_sal(self, op):
dsize = op.opers[0].tsize
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
src = src & 0x1f
# According to intel manual, if src == 0 eflags are not changed
if src == 0:
return
res = dst << src
cf = (res >> 8 * dsize) & 1
res = e_bits.unsigned(res, dsize)
self.setFlag(EFLAGS_CF, cf)
self.setFlag(EFLAGS_SF, e_bits.is_signed(res, dsize))
self.setFlag(EFLAGS_ZF, not res)
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(res))
if src == 1:
self.setFlag(EFLAGS_OF, not e_bits.msb(res, dsize) == cf)
else:
self.setFlag(EFLAGS_OF, 0) # Undefined, but zero'd on core2 duo
self.setOperValue(op, 0, res)
def i_rra(self, op):
dst = self.getOperValue(op, 0)
size = self.getOperSize(op)
udst = e_bits.unsigned(dst, size)
shift = (size * 8) - 1
res = (e_bits.msb(udst, size) << shift) | (udst>>1)
ures = e_bits.unsigned(res, size)
self.setFlag(SR_N, e_bits.msb(ures, size))
self.setFlag(SR_Z, ures == 0)
self.setFlag(SR_C, e_bits.lsb(udst))
self.setFlag(SR_V, 0)
self.setOperValue(op, 0, ures)
def i_xor(self, op):
src = self.getOperValue(op, 0)
dst = self.getOperValue(op, 1)
size = self.getOperSize(op)
usrc = e_bits.unsigned(src, size)
udst = e_bits.unsigned(dst, size)
ures = usrc ^ udst
self.setFlag(SR_N, e_bits.msb(ures, size))
self.setFlag(SR_Z, ures == 0)
self.setFlag(SR_C, ures != 0)
self.setFlag(SR_V, e_bits.msb(usrc, size) and e_bits.msb(udst, size))
self.setOperValue(op, 1, ures)
def i_xor(self, op):
src = self.getOperValue(op, 0)
dst = self.getOperValue(op, 1)
size = self.getOperSize(op)
usrc = e_bits.unsigned(src, size)
udst = e_bits.unsigned(dst, size)
ures = usrc ^ udst
self.setFlag(SR_N, e_bits.msb(ures, size))
self.setFlag(SR_Z, ures == 0)
self.setFlag(SR_C, ures != 0)
self.setFlag(SR_V, e_bits.msb(usrc, size) and e_bits.msb(udst, size))
self.setOperValue(op, 1, ures)
def i_rra(self, op):
dst = self.getOperValue(op, 0)
size = self.getOperSize(op)
udst = e_bits.unsigned(dst, size)
shift = (size * 8) - 1
res = (e_bits.msb(udst, size) << shift) | (udst>>1)
ures = e_bits.unsigned(res, size)
self.setFlag(SR_N, e_bits.msb(ures, size))
self.setFlag(SR_Z, ures == 0)
self.setFlag(SR_C, e_bits.lsb(udst))
self.setFlag(SR_V, 0)
self.setOperValue(op, 0, ures)
def i_rol(self, op):
dstSize = op.opers[0].tsize
count = self.getOperValue(op, 1)
tempCount = shiftMask(count, dstSize)
if tempCount > 0: # Yeah, i know...weird. See the intel manual
while tempCount:
val = self.getOperValue(op, 0)
tempCf = e_bits.msb(val, dstSize)
self.setOperValue(op, 0, (val * 2) + tempCf)
tempCount -= 1
val = self.getOperValue(op, 0)
self.setFlag(EFLAGS_CF, e_bits.lsb(val))
if count == 1:
val = self.getOperValue(op, 0)
cf = self.getFlag(EFLAGS_CF)
self.setFlag(EFLAGS_OF, e_bits.msb(val, dstSize) ^ cf)
else:
self.setFlag(EFLAGS_OF, False)
def i_rol(self, op):
dstSize = op.opers[0].tsize
count = self.getOperValue(op, 1)
tempCount = shiftMask(count, dstSize)
if tempCount > 0: # Yeah, i know...weird. See the intel manual
while tempCount:
val = self.getOperValue(op, 0)
tempCf = e_bits.msb(val, dstSize)
self.setOperValue(op, 0, (val * 2) + tempCf)
tempCount -= 1
val = self.getOperValue(op, 0)
self.setFlag(EFLAGS_CF, e_bits.lsb(val))
if count == 1:
val = self.getOperValue(op, 0)
cf = self.getFlag(EFLAGS_CF)
self.setFlag(EFLAGS_OF, e_bits.msb(val, dstSize) ^ cf)
else:
self.setFlag(EFLAGS_OF, False)
def i_tst(self, op):
dst = self.getOperValue(op, 0)
size = self.getOperSize(op)
udst = e_bits.unsigned(dst, size)
self.setFlag(SR_N, e_bits.msb(udst, size))
self.setFlag(SR_Z, udst == 0)
self.setFlag(SR_C, 1)
self.setFlag(SR_V, 0)
def i_tst(self, op):
dst = self.getOperValue(op, 0)
size = self.getOperSize(op)
udst = e_bits.unsigned(dst, size)
self.setFlag(SR_N, e_bits.msb(udst, size))
self.setFlag(SR_Z, udst == 0)
self.setFlag(SR_C, 1)
self.setFlag(SR_V, 0)
def i_ror(self, op):
dstSize = op.opers[0].tsize
count = self.getOperValue(op, 1)
tempCount = shiftMask(count, dstSize)
if tempCount > 0: # Yeah, i know...weird. See the intel manual
while tempCount:
val = self.getOperValue(op, 0)
tempCf = e_bits.lsb(val)
self.setOperValue(op, 0, (val / 2) + (tempCf * (2 ** dstSize)))
tempCount -= 1
val = self.getOperValue(op, 0)
self.setFlag(EFLAGS_CF, e_bits.msb(val, dstSize))
if count == 1:
val = self.getOperValue(op, 0)
cf = self.getFlag(EFLAGS_CF)
# FIXME: This may be broke...the manual is kinda flaky here
self.setFlag(EFLAGS_OF, e_bits.msb(val, dstSize) ^ (e_bits.msb(val, dstSize) - 1))
else:
self.setFlag(EFLAGS_OF, False)
def i_ror(self, op):
dstSize = op.opers[0].tsize
count = self.getOperValue(op, 1)
tempCount = shiftMask(count, dstSize)
if tempCount > 0: # Yeah, i know...weird. See the intel manual
while tempCount:
val = self.getOperValue(op, 0)
tempCf = e_bits.lsb(val)
self.setOperValue(op, 0, (val / 2) + (tempCf * (2 ** dstSize)))
tempCount -= 1
val = self.getOperValue(op, 0)
self.setFlag(EFLAGS_CF, e_bits.msb(val, dstSize))
if count == 1:
val = self.getOperValue(op, 0)
cf = self.getFlag(EFLAGS_CF)
# FIXME: This may be broke...the manual is kinda flaky here
self.setFlag(EFLAGS_OF, e_bits.msb(val, dstSize) ^ (e_bits.msb(val, dstSize) - 1))
else:
self.setFlag(EFLAGS_OF, False)
def doAnd(self, a, b, size):
ua = e_bits.unsigned(a, size)
ub = e_bits.unsigned(b, size)
res = ua & ub
self.setFlag(SR_N, e_bits.msb(res, size))
self.setFlag(SR_Z, res == 0)
self.setFlag(SR_C, res != 0)
self.setFlag(SR_V, 0)
return res
def doAnd(self, a, b, size):
ua = e_bits.unsigned(a, size)
ub = e_bits.unsigned(b, size)
res = ua & ub
self.setFlag(SR_N, e_bits.msb(res, size))
self.setFlag(SR_Z, res == 0)
self.setFlag(SR_C, res != 0)
self.setFlag(SR_V, 0)
return res
def i_rla(self, op):
dst = self.getOperValue(op, 0)
size = self.getOperSize(op)
udst = e_bits.unsigned(dst, size)
self.setFlag(SR_C, e_bits.msb(udst, size))
res = udst << 1
ures = e_bits.unsigned(res, size)
if size == BYTE:
val_min = 0x40
val_max = 0xc0
else:
val_min = 0x4000
val_max = 0xc000
self.setFlag(SR_N, e_bits.msb(ures, size))
self.setFlag(SR_Z, ures == 0)
self.setFlag(SR_V, udst >= val_min and udst < val_max)
self.setOperValue(op, 0, ures)
def i_rla(self, op):
dst = self.getOperValue(op, 0)
size = self.getOperSize(op)
udst = e_bits.unsigned(dst, size)
self.setFlag(SR_C, e_bits.msb(udst, size))
res = udst << 1
ures = e_bits.unsigned(res, size)
if size == BYTE:
val_min = 0x40
val_max = 0xc0
else:
val_min = 0x4000
val_max = 0xc000
self.setFlag(SR_N, e_bits.msb(ures, size))
self.setFlag(SR_Z, ures == 0)
self.setFlag(SR_V, udst >= val_min and udst < val_max)
self.setOperValue(op, 0, ures)
def test_msb(self):
self.assertEqual(1, e_bits.msb(0x80, 1))
self.assertEqual(0, e_bits.msb(0x7f, 1))
self.assertEqual(1, e_bits.msb(0x8000, 2))
self.assertEqual(0, e_bits.msb(0x7fff, 2))
self.assertEqual(1, e_bits.msb(0x80000000, 4))
self.assertEqual(0, e_bits.msb(0x7fffffff, 4))
self.assertEqual(1, e_bits.msb(0x8000000000000000, 8))
self.assertEqual(0, e_bits.msb(0x7fffffffffffffff, 8))
self.assertEqual(1, e_bits.msb_minus_one(0x40, 1))
self.assertEqual(0, e_bits.msb_minus_one(0xbf, 1))
self.assertEqual(1, e_bits.msb_minus_one(0x4000, 2))
self.assertEqual(0, e_bits.msb_minus_one(0xbfff, 2))
self.assertEqual(1, e_bits.msb_minus_one(0x40000000, 4))
self.assertEqual(0, e_bits.msb_minus_one(0xbfffffff, 4))
self.assertEqual(1, e_bits.msb_minus_one(0x4000000000000000, 8))
self.assertEqual(0, e_bits.msb_minus_one(0xbfffffffffffffff, 8))
def doSubC(self, a, b, carry, size):
ua = e_bits.unsigned(a, size)
ub = e_bits.unsigned(b, size)
sa = e_bits.signed(a, size)
sb = e_bits.signed(b, size)
ures = ua - ub - 1 + carry
sres = sa - sb - 1 + carry
res = e_bits.unsigned(ures, size)
self.setFlag(SR_N, e_bits.msb(res, size))
self.setFlag(SR_Z, res == 0)
self.setFlag(SR_C, not e_bits.is_unsigned_carry(ures, size))
self.setFlag(SR_V, e_bits.is_signed_overflow(sres, size))
return res
def doSubC(self, a, b, carry, size):
ua = e_bits.unsigned(a, size)
ub = e_bits.unsigned(b, size)
sa = e_bits.signed(a, size)
sb = e_bits.signed(b, size)
ures = ua - ub - 1 + carry
sres = sa - sb - 1 + carry
res = e_bits.unsigned(ures, size)
self.setFlag(SR_N, e_bits.msb(res, size))
self.setFlag(SR_Z, res == 0)
self.setFlag(SR_C, not e_bits.is_unsigned_carry(ures, size))
self.setFlag(SR_V, e_bits.is_signed_overflow(sres, size))
return res
def i_sxt(self, op):
dst = self.getOperValue(op, 0)
udst = e_bits.unsigned(dst, BYTE)
smax = e_bits.s_maxes[BYTE]
umax = e_bits.u_maxes[WORD]
if udst > smax:
ubits = smax ^ umax
udst |= ubits
self.setFlag(SR_N, e_bits.msb(udst, WORD))
self.setFlag(SR_Z, dst == 0)
self.setFlag(SR_C, dst != 0)
self.setFlag(SR_V, 0)
self.setOperValue(op, 0, udst)
def i_sxt(self, op):
dst = self.getOperValue(op, 0)
udst = e_bits.unsigned(dst, BYTE)
smax = e_bits.s_maxes[BYTE]
umax = e_bits.u_maxes[WORD]
if udst > smax:
ubits = smax ^ umax
udst |= ubits
self.setFlag(SR_N, e_bits.msb(udst, WORD))
self.setFlag(SR_Z, dst == 0)
self.setFlag(SR_C, dst != 0)
self.setFlag(SR_V, 0)
self.setOperValue(op, 0, udst)
def doDecAddC(self, a, b, carry, size):
ua = e_bits.unsigned(a, size)
ub = e_bits.unsigned(b, size)
int_a = e_enc.bcd_to_int(ua)
int_b = e_enc.bcd_to_int(ub)
int_res = int_a + int_b + carry
bcd_res = e_enc.int_to_bcd(int_res)
res = e_bits.unsigned(bcd_res, size)
if size == BYTE:
bcd_max = 99
else:
bcd_max = 9999
self.setFlag(SR_N, e_bits.msb(res, size))
self.setFlag(SR_Z, res == 0)
self.setFlag(SR_C, 1 if int_res > bcd_max else 0)
return res
def doDecAddC(self, a, b, carry, size):
ua = e_bits.unsigned(a, size)
ub = e_bits.unsigned(b, size)
int_a = e_enc.bcd_to_int(ua)
int_b = e_enc.bcd_to_int(ub)
int_res = int_a + int_b + carry
bcd_res = e_enc.int_to_bcd(int_res)
res = e_bits.unsigned(bcd_res, size)
if size == BYTE:
bcd_max = 99
else:
bcd_max = 9999
self.setFlag(SR_N, e_bits.msb(res, size))
self.setFlag(SR_Z, res == 0)
self.setFlag(SR_C, 1 if int_res > bcd_max else 0)
return res