def _div(self, op, isInvalid=None):
oper = op.opers[0]
denom = self.getOperObj(op, 0)
if denom == 0:
# TODO: make effect
raise envi.DivideByZero('AMD64 Divide by zero')
if isInvalid is None:
limit = (2 ** (oper.tsize * 8)) - 1
isInvalid = lambda val: val > limit
if oper.tsize == 8:
rax = Var('rax', self._psize)
rdx = Var('rdx', self._psize)
num = (rdx << Const(64, self._psize)) + rax
temp = num / denom
if temp.isDiscrete() and isInvalid(temp):
# TODO: make effect
raise envi.DivideError('AMD64 i_div #DE')
self.effSetVariable('rax', temp)
self.effSetVariable('rdx', num % denom)
return
return vsym_i386.IntelSymbolikTranslator._div(self, op, isInvalid=isInvalid)
def i_div(self, op):
#FIXME this is probably broke
oper = op.opers[0]
val = self.getOperValue(op, 1)
if val == 0: raise envi.DivideByZero(self)
if oper.tsize == 1:
ax = self.getRegister(REG_AX)
quot = ax / val
rem = ax % val
#if quot > 255:
#FIXME stuff
#print "FIXME: division exception"
self.setRegister(REG_EAX, (quot << 8) + rem)
elif oper.tsize == 4:
#FIXME 16 bit over-ride
eax = self.getRegister(REG_EAX)
edx = self.getRegister(REG_EDX)
tot = (edx << 32) + eax
quot = tot / val
rem = tot % val
#if quot > 0xffffffff:
#print "FIXME: division exception"
self.setRegister(REG_EAX, quot)
self.setRegister(REG_EDX, rem)
else:
raise envi.UnsupportedInstruction(self, op)
def i_idiv(self, op):
#FIXME this needs emulation testing!
tsize = op.opers[0].tsize
if tsize == 1:
ax = self.getRegister(REG_AX)
ax = e_bits.signed(ax, 2)
d = self.getOperValue(op, 0)
d = e_bits.signed(d, 1)
if d == 0: raise envi.DivideByZero(self)
q = ax / d
r = ax % d
res = ((r & 0xff) << 8) | (q & 0xff)
self.setRegister(REG_AX, res)
elif tsize == 2:
val = self.twoRegCompound(REG_DX, REG_AX, 2)
val = e_bits.signed(val, 4)
d = self.getOperValue(op, 0)
d = e_bits.signed(d, 2)
if d == 0: raise envi.DivideByZero(self)
q = val / d
r = val % d
self.setRegister(REG_AX, q)
self.setRegister(REG_DX, r)
elif tsize == 4:
val = self.twoRegCompound(REG_EDX, REG_EAX, 4)
val = e_bits.signed(val, 8)
d = self.getOperValue(op, 0)
d = e_bits.signed(d, 4)
if d == 0: raise envi.DivideByZero(self)
q = val / d
r = val % d
self.setRegister(REG_EAX, q)
self.setRegister(REG_EDX, r)
else:
raise envi.UnsupportedInstruction(self, op)
def i_idiv(self, op):
tsize = op.opers[0].tsize
if tsize == 8:
val = self.twoRegCompound(REG_RDX, REG_RAX, 8)
val = e_bits.signed(val, 16)
d = self.getOperValue(op, 0)
d = e_bits.signed(d, 8)
if d == 0:
raise envi.DivideByZero(self)
q = val // d
r = val % d
self.setRegister(REG_RAX, q)
self.setRegister(REG_RDX, r)
else:
e_i386.IntelEmulator.i_idiv(self, op)
def i_idiv(self, op):
tsize = op.opers[0].tsize
if tsize == 8:
val = self.twoRegCompound(REG_RDX, REG_RAX, 8)
val = e_bits.signed(val, 16)
d = self.getOperValue(op, 0)
d = e_bits.signed(d, 8)
if d == 0:
raise envi.DivideByZero(self)
sign = (val < 0 and d > 0) or (val > 0 and d < 0)
q = (abs(val) // abs(d))
r = (abs(val) % abs(d))
if sign:
q = -q
r = -r
self.setRegister(REG_RAX, q)
self.setRegister(REG_RDX, r)
else:
e_i386.IntelEmulator.i_idiv(self, op)
