def test_target_clock(capfd, target, simulator):
circ = common.TestBasicClkCircuit
actions = [
Poke(circ.I, 0),
Print(circ.I),
Expect(circ.O, 0),
Poke(circ.CLK, 0),
Print(circ.O),
Step(circ.CLK, 1),
Poke(circ.I, BitVector(1, 1)),
Eval(),
Print(circ.O),
]
run(circ, actions, target, simulator, flags=["-Wno-lint"])
out, err = capfd.readouterr()
lines = out.splitlines()
if target == fault.verilator_target.VerilatorTarget:
assert lines[-3] == "BasicClkCircuit.I = 0", out
assert lines[-2] == "BasicClkCircuit.O = 0", out
assert lines[-1] == "BasicClkCircuit.O = 1", out
else:
if simulator == "ncsim":
assert lines[-6] == "BasicClkCircuit.I = 0", out
assert lines[-5] == "BasicClkCircuit.O = 0", out
assert lines[-4] == "BasicClkCircuit.O = 1", out
elif simulator == "vcs":
assert lines[-9] == "BasicClkCircuit.I = 0", out
assert lines[-8] == "BasicClkCircuit.O = 0", out
assert lines[-7] == "BasicClkCircuit.O = 1", out
else:
raise NotImplementedError(f"Unsupported simulator: {simulator}")
def test_target_clock(capsys, target, simulator):
circ = TestBasicClkCircuit
actions = [
Print(TEST_START + '\n'),
Poke(circ.I, 0),
Eval(),
Print("%x\n", circ.I),
Expect(circ.O, 0),
Poke(circ.CLK, 0),
Print("%x\n", circ.O),
Step(circ.CLK, 1),
Poke(circ.I, BitVector[1](1)),
Eval(),
Print("%x\n", circ.O),
]
run(circ,
actions,
target,
simulator,
flags=["-Wno-lint"],
disp_type='realtime')
messages = outlines(capsys)
idx = messages.index(TEST_START) + 1
actual = "\n".join(messages[idx:idx + 3])
assert actual == """\
def test_verilator_trace():
circ = TestBasicClkCircuit
actions = [
Poke(circ.I, 0),
Print("%x", circ.I),
Expect(circ.O, 0),
Poke(circ.CLK, 0),
Print("%x", circ.O),
Step(circ.CLK, 1),
Poke(circ.I, BitVector[1](1)),
Eval(),
Print("%x", circ.O),
]
flags = ["-Wno-lint", "--trace"]
with tempfile.TemporaryDirectory(dir=".") as tempdir:
assert not os.path.isfile(f"{tempdir}/logs/BasicClkCircuit.vcd"), \
"Expected logs to be empty"
m.compile(f"{tempdir}/{circ.name}", circ,
output="coreir-verilog")
target = fault.verilator_target.VerilatorTarget(
circ, directory=f"{tempdir}/",
flags=flags, skip_compile=True)
target.run(actions)
assert os.path.isfile(f"{tempdir}/logs/BasicClkCircuit.vcd"), \
"Expected VCD to exist"
def test_action_strs():
circ = common.TestBasicClkCircuit
assert str(Poke(circ.I, 1)) == 'Poke(BasicClkCircuit.I, 1)'
assert str(Expect(circ.O, 1)) == 'Expect(BasicClkCircuit.O, 1)'
assert str(Eval()) == 'Eval()'
assert str(Step(circ.CLK, 1)) == 'Step(BasicClkCircuit.CLK, steps=1)'
assert str(Print(circ.O, "%08x")) == 'Print(BasicClkCircuit.O, "%08x")'
assert str(Peek(circ.O)) == 'Peek(BasicClkCircuit.O)'
def test_retarget_tester(target, simulator):
circ = TestBasicClkCircuit
expected = [
Poke(circ.I, 0),
Eval(),
Expect(circ.O, 0),
Poke(circ.CLK, 0),
Step(circ.CLK, 1),
Print("%08x", circ.O)
]
tester = fault.Tester(circ, circ.CLK)
tester.poke(circ.I, 0)
tester.eval()
tester.expect(circ.O, 0)
tester.poke(circ.CLK, 0)
tester.step()
tester.print("%08x", circ.O)
for i, exp in enumerate(expected):
check(tester.actions[i + 1], exp)
circ_copy = TestBasicClkCircuitCopy
copy = tester.retarget(circ_copy, circ_copy.CLK)
copy_expected = [
Poke(circ_copy.I, 0),
Eval(),
Expect(circ_copy.O, 0),
Poke(circ_copy.CLK, 0),
Step(circ_copy.CLK, 1),
Print("%08x", circ_copy.O)
]
for i, exp in enumerate(copy_expected):
check(copy.actions[i + 1], exp)
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
copy.compile_and_run(target, directory=_dir, flags=["-Wno-fatal"])
else:
copy.compile_and_run(target,
directory=_dir,
simulator=simulator,
magma_opts={"sv": True})
def test_retarget_tester(target, simulator):
circ = common.TestBasicClkCircuit
expected = [
Poke(circ.I, 0),
Eval(),
Expect(circ.O, 0),
Poke(circ.CLK, 0),
Step(circ.CLK, 1),
Print(circ.O, "%08x")
]
tester = fault.Tester(circ, circ.CLK, default_print_format_str="%08x")
tester.poke(circ.I, 0)
tester.eval()
tester.expect(circ.O, 0)
tester.poke(circ.CLK, 0)
tester.step()
tester.print(circ.O)
for i, exp in enumerate(expected):
check(tester.actions[i], exp)
circ_copy = common.TestBasicClkCircuitCopy
copy = tester.retarget(circ_copy, circ_copy.CLK)
assert copy.default_print_format_str == "%08x"
copy_expected = [
Poke(circ_copy.I, 0),
Eval(),
Expect(circ_copy.O, 0),
Poke(circ_copy.CLK, 0),
Step(circ_copy.CLK, 1),
Print(circ_copy.O, "%08x")
]
for i, exp in enumerate(copy_expected):
check(copy.actions[i], exp)
with tempfile.TemporaryDirectory() as _dir:
if target == "verilator":
copy.compile_and_run(target, directory=_dir, flags=["-Wno-fatal"])
else:
copy.compile_and_run(target, directory=_dir, simulator=simulator)
def test_tester_peek(target, simulator):
circ = TestBasicClkCircuit
tester = fault.Tester(circ, circ.CLK)
tester.poke(circ.I, 0)
tester.expect(circ.O, 0)
check(tester.actions[0], Poke(circ.I, 0))
check(tester.actions[1], Expect(circ.O, 0))
tester.poke(circ.CLK, 0)
check(tester.actions[2], Poke(circ.CLK, 0))
tester.step()
check(tester.actions[3], Step(circ.CLK, 1))
with tempfile.TemporaryDirectory(dir=".") as _dir:
if target == "verilator":
tester.compile_and_run(target, directory=_dir, flags=["-Wno-fatal"])
else:
tester.compile_and_run(target, directory=_dir, simulator=simulator)
def test_tester_clock():
circ = TestBasicClkCircuit
builder = VectorBuilder(circ)
builder.process(Poke(circ.I, BitVector[1](0)))
builder.process(Print("%x", circ.O))
builder.process(Expect(circ.O, BitVector[1](0)))
assert builder.vectors == [[
BitVector[1](0), BitVector[1](0), fault.AnyValue
]]
builder.process(Poke(circ.CLK, BitVector[1](0)))
assert builder.vectors == [[
BitVector[1](0), BitVector[1](0), BitVector[1](0)
]]
builder.process(Step(circ.CLK, 1))
assert builder.vectors == [[
BitVector[1](0), BitVector[1](0), BitVector[1](0)
], [BitVector[1](0), fault.AnyValue, BitVector[1](1)]]
def test_action_strs():
circ = common.TestBasicClkCircuit
assert str(Poke(circ.I, 1)) == 'Poke(BasicClkCircuit.I, 1)'
assert str(Expect(circ.O, 1)) == 'Expect(BasicClkCircuit.O, 1)'
assert str(Eval()) == 'Eval()'
assert str(Step(circ.CLK, 1)) == 'Step(BasicClkCircuit.CLK, steps=1)'
assert str(Print(circ.O, "%08x")) == 'Print(BasicClkCircuit.O, "%08x")'
assert str(Peek(circ.O)) == 'Peek(BasicClkCircuit.O)'
index = f"__fault_loop_var_action_0"
assert str(Loop(12, index, [Peek(circ.O), Poke(circ.I, 1)])) == \
f'Loop(12, {index}, ' \
f'[Peek(BasicClkCircuit.O), Poke(BasicClkCircuit.I, 1)])'
file = File("my_file", Tester(circ), "r", 1)
assert str(FileOpen(file)) == 'FileOpen(File<"my_file">)'
assert str(FileRead(file)) == 'FileRead(File<"my_file">)'
assert str(FileWrite(file, 3)) == 'FileWrite(File<"my_file">, 3)'
assert str(FileClose(file)) == 'FileClose(File<"my_file">)'
def test_magma_simulator_target_clock(backend, capfd):
circ = common.TestBasicClkCircuit
actions = [
Poke(circ.I, BitVector(0, 1)),
Print(circ.I),
Expect(circ.O, BitVector(0, 1)),
# TODO(rsetaluri): Figure out how to set clock value directly with the
# coreir simulator. Currently it does not allow this.
# Poke(circ.CLK, BitVector(0, 1)),
Step(circ.CLK, 1),
Poke(circ.I, BitVector(1, 1)),
Eval(),
Print(circ.O),
]
run(circ, actions, circ.CLK, backend)
out, err = capfd.readouterr()
lines = out.splitlines()
assert lines[-2] == "BasicClkCircuit.I = 0", "Print output incorrect"
assert lines[-1] == "BasicClkCircuit.O = 1", "Print output incorrect"
def test_target_clock(capsys, target, simulator):
circ = TestBasicClkCircuit
actions = [
Poke(circ.I, 0),
Print("%x\n", circ.I),
Expect(circ.O, 0),
Poke(circ.CLK, 0),
Print("%x\n", circ.O),
Step(circ.CLK, 1),
Poke(circ.I, BitVector[1](1)),
Eval(),
Print("%x\n", circ.O),
]
run(circ,
actions,
target,
simulator,
flags=["-Wno-lint"],
disp_type='realtime')
messages = outlines(capsys)
if target == fault.verilator_target.VerilatorTarget:
assert messages[-4] == "0"
assert messages[-3] == "0"
assert messages[-2] == "1"
else:
if simulator == "ncsim":
assert messages[-7] == "0"
assert messages[-6] == "0"
assert messages[-5] == "1"
elif simulator == "vcs":
assert messages[-10] == "0"
assert messages[-9] == "0"
assert messages[-8] == "1"
else:
raise NotImplementedError(f"Unsupported simulator: {simulator}")