def ana_a_chn(rms_rootpath, cali_rootpath, mode="CHN", APAno = 4, \
rmsrunno = "run01rms", calirunno = "run01fpg",
wibno=0, fembno=0, chnno=0, gain="250", tp="20", \
jumbo_flag=False, fft_en= True, fft_s=5000, fft_avg_cycle=50, cap=1.85E-13, apa="ProtoDUNE" ):
femb_pos_np = femb_position(APAno)
wibfemb = "WIB" + format(wibno, '02d') + "_" + "FEMB" + format(
fembno, '1d')
apainfo = None
for femb_pos in femb_pos_np:
if femb_pos[1] == wibfemb:
apainfo = femb_pos
break
apa_map = APA_MAP()
apa_map.APA = apa
All_sort, X_sort, V_sort, U_sort = apa_map.apa_femb_mapping()
wireinfo = None
for onewire in All_sort:
if (int(onewire[1]) == chnno):
wireinfo = onewire
break
feset_info = [gain, tp]
rmsdata = read_rawdata_fast(rms_rootpath, rmsrunno, wibno, fembno, chnno,
gain, tp, jumbo_flag)
calidata = read_rawdata(cali_rootpath, calirunno, wibno, fembno, chnno,
gain, tp, jumbo_flag)
chn_noise_paras = noise_a_chn(rmsdata, chnno, fft_en, fft_s, fft_avg_cycle,
wibno, fembno)
chn_cali_paras = cali_a_chn(calidata, chnno, cap, wibno, fembno)
def APA_sort(APAno = 1):
femb_pos_np = femb_position(APAno)
All_sort, X_sort, V_sort, U_sort = apamap.apa_femb_mapping_pd()
APA_sort_all = []
for apa_slot in range(1,21,1):
for femb_pos in femb_pos_np:
if int(femb_pos[0][2:4]) == apa_slot :
break
APA_sort_all.append([femb_pos, All_sort])
APA_X_sort = []
for apa_slot in range(1,21,1):
for femb_pos in femb_pos_np:
if int(femb_pos[0][2:4]) == apa_slot :
break
APA_X_sort.append([femb_pos, X_sort])
APA_V_sort = []
for apa_slot in range(1,21,1):
for femb_pos in femb_pos_np:
if int(femb_pos[0][2:4]) == apa_slot :
break
APA_V_sort.append([femb_pos, V_sort])
APA_U_sort = []
for apa_slot in range(1,21,1):
for femb_pos in femb_pos_np:
if int(femb_pos[0][2:4]) == apa_slot :
break
APA_U_sort.append([femb_pos, U_sort])
return APA_sort_all, APA_X_sort, APA_V_sort, APA_U_sort
def wf_a_asic(rms_rootpath, fpga_rootpath, asic_rootpath, APAno = 4, \
rmsrunno = "run01rms", fpgarunno = "run01fpg", asicrunno = "run01asi",\
wibno=0, fembno=0, asicno=0, gain="250", tp="05" ,\
jumbo_flag=False, apa= "ProtoDUNE" ):
femb_pos_np = femb_position(APAno)
wibfemb = "WIB" + format(wibno, '02d') + "_" + "FEMB" + format(
fembno, '1d')
apainfo = None
for femb_pos in femb_pos_np:
if femb_pos[1] == wibfemb:
apainfo = femb_pos
break
feset_info = [gain, tp]
apa_map = APA_MAP()
apa_map.APA = apa
All_sort, X_sort, V_sort, U_sort = apa_map.apa_femb_mapping()
rmsdata = read_rawdata_coh(rms_rootpath, rmsrunno, wibno, fembno,
16 * asicno, gain, tp, jumbo_flag)
asic_results = []
for chni in range(16):
chnno = chni + 16 * asicno
wireinfo = None
for onewire in All_sort:
if (int(onewire[1]) == chnno):
wireinfo = onewire
break
chn_noise_paras = noise_a_chn(rmsdata, chnno, fft_en=True)
rms = chn_noise_paras[1]
ped = chn_noise_paras[2]
hfrms = chn_noise_paras[7]
hfped = chn_noise_paras[8]
sfrms = chn_noise_paras[13]
sfped = chn_noise_paras[14]
unstk_ratio = chn_noise_paras[15]
raw_data = chn_noise_paras[3]
r100us_data = chn_noise_paras[4]
fft_f = chn_noise_paras[5]
fft_p = chn_noise_paras[6]
fft_fl = chn_noise_paras[16]
fft_pl = chn_noise_paras[17]
print[apainfo, APAno, wibno, fembno, asicno, chni, wireinfo]
#0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
asic_results.append([
apainfo, APAno, wibno, fembno, asicno, chni, rms, ped, hfrms,
hfped, sfrms, sfped, unstk_ratio, raw_data, r100us_data, fft_f,
fft_p, fft_fl, fft_pl, wireinfo
])
return asic_results
def mp_ana_a_chn(rms_rootpath, cali_rootpath, mode="CHN", APAno = 4, \
rmsrunno = "run01rms", calirunno = "run01fpg",
wibno=0, fembno=0, chnno=0, gain="250", tp="20", \
jumbo_flag=False, fft_en= True, fft_s=5000, fft_avg_cycle=50, cap=1.85E-13 ):
femb_pos_np = femb_position(APAno)
wibfemb = "WIB" + format(wibno, '02d') + "_" + "FEMB" + format(
fembno, '1d')
apainfo = None
for femb_pos in femb_pos_np:
if femb_pos[1] == wibfemb:
apainfo = femb_pos
break
apa_map = APA_MAP()
All_sort, X_sort, V_sort, U_sort = apa_map.apa_femb_mapping()
wireinfo = None
for onewire in All_sort:
if (int(onewire[1]) == chnno):
wireinfo = onewire
break
feset_info = [gain, tp]
rmsdata = read_rawdata_fast(rms_rootpath, rmsrunno, wibno, fembno, chnno,
gain, tp, jumbo_flag)
calidata = read_rawdata(cali_rootpath, calirunno, wibno, fembno, chnno,
gain, tp, jumbo_flag)
from multiprocessing import Pipe
pc1, cc1 = Pipe()
pc2, cc2 = Pipe()
noise_a_chn_argvs = (cc1, rmsdata, chnno, fft_en, fft_s, fft_avg_cycle,
wibno, fembno)
cali_a_chn_argvs = (cc2, calidata, chnno, cap)
p1 = mp.Process(target=mp_noise_a_chn, args=noise_a_chn_argvs)
p2 = mp.Process(target=mp_cali_a_chn, args=cali_a_chn_argvs)
p1.start()
p2.start()
chn_noise_paras = pc1.recv()
chn_cali_paras = pc2.recv()
p1.join()
p2.join()
def pipe_ana_a_chn(cc, out_path, rms_rootpath, fpga_rootpath, asic_rootpath, APAno = 4, \
rmsrunno = "run01rms", fpgarunno = "run01fpg", asicrunno = "run01asi",
wibno=0, fembno=0, chnno=0, gain="250", tp="20", \
jumbo_flag=False, fft_s=5000, apa = "ProtoDUNE" ):
input_info = ["RMS Raw data Path = %s"%rms_rootpath + rmsrunno,
"Cali(FPGA DAC) Raw data Path = %s"%fpga_rootpath + fpgarunno,
"Cali(ASIC DAC) Raw data Path = %s"%asic_rootpath + asicrunno,
"APA#%d"%APAno ,
"WIB#%d"%wibno ,
"Gain = %2.1f mV/fC"% (int(gain)/10.0) ,
"Tp = %1.1f$\mu$s"% (int(tp)/10.0) ]
wibfemb= "WIB"+format(wibno,'02d') + "_" + "FEMB" + format(fembno,'1d')
#print wibfemb + "chn%d"%chnno
femb_pos_np = femb_position (APAno)
apainfo = None
for femb_pos in femb_pos_np:
if femb_pos[1] == wibfemb:
apainfo = femb_pos
break
apa_map = APA_MAP()
apa_map.APA = apa
All_sort, X_sort, V_sort, U_sort = apa_map.apa_femb_mapping()
wireinfo = None
for onewire in All_sort:
if (int(onewire[1]) == chnno):
wireinfo = onewire
break
feset_info = [gain, tp]
if (os.path.exists(rms_rootpath + rmsrunno)):
rmsdata = read_rawdata(rms_rootpath, rmsrunno, wibno, fembno, chnno, gain, tp, jumbo_flag)
chn_noise_paras = noise_a_chn(rmsdata, chnno,fft_en = True, fft_s=fft_s, fft_avg_cycle=50, wibno=wibno, fembno=fembno)
else:
print "Path: %s%s doesnt' exist, ignore anyway"%(rms_rootpath, rmsrunno)
chn_noise_paras = None
cc.send(chn_noise_paras)
cc.close()
def wfcoh_a_asic(rms_rootpath, fpga_rootpath, asic_rootpath, APAno = 4, \
rmsrunno = "run01rms", fpgarunno = "run01fpg", asicrunno = "run01asi",\
wibno=0, fembno=0, asicno=0, gain="250", tp="05" ,\
jumbo_flag=False, apa= "ProtoDUNE" ):
femb_pos_np = femb_position(APAno)
wibfemb = "WIB" + format(wibno, '02d') + "_" + "FEMB" + format(
fembno, '1d')
apainfo = None
for femb_pos in femb_pos_np:
if femb_pos[1] == wibfemb:
apainfo = femb_pos
break
feset_info = [gain, tp]
apa_map = APA_MAP()
apa_map.APA = apa
All_sort, X_sort, V_sort, U_sort = apa_map.apa_femb_mapping()
rmsdata = read_rawdata_coh(rms_rootpath, rmsrunno, wibno, fembno,
16 * asicno, gain, tp, jumbo_flag)
asic_results = []
for chni in range(16):
chnno = chni + 16 * asicno
wireinfo = None
for onewire in All_sort:
if (int(onewire[1]) == chnno):
wireinfo = onewire
break
wiretype = wireinfo[0][0]
print[APAno, wibno, fembno, asicno, chni, wireinfo]
rpath = "/nfs/home/shanshan/coh_study/"
rpath = "./"
t_pat = "Test035"
pre_ana = t_pat + "_ProtoDUNE_CE_characterization_summary" + ".csv"
ppath = rpath + pre_ana
ccs = []
with open(ppath, 'r') as fp:
for cl in fp:
tmp = cl.split(",")
x = []
for i in tmp:
x.append(i.replace(" ", ""))
x = x[:-1]
ccs.append(x)
ccs_title = ccs[0]
ccs = ccs[1:]
asic_ccs = []
for ci in ccs:
if (APAno == int(ci[0][1])) and (int(ci[3]) == wibno) and (int(
ci[4]) == fembno) and (int(ci[5]) == asicno):
asic_ccs.append(ci)
cohdata, cohdata_flg = coh_noise_ana(asic_ccs,
rmsdata,
wiretype=wiretype)
chn_noise_paras = noise_a_coh(cohdata,
cohdata_flg,
rmsdata,
chnno=chni,
fft_en=True,
fft_s=2000,
fft_avg_cycle=50,
wibno=wibno,
fembno=fembno)
fig = plt.figure(figsize=(32, 18))
axu = []
axm = []
axd = []
axu.append(plt.subplot2grid((3, 3), (0, 0), colspan=3, rowspan=1))
axm.append(plt.subplot2grid((3, 3), (1, 0), colspan=3, rowspan=1))
axd.append(plt.subplot2grid((3, 3), (2, 0), colspan=3, rowspan=1))
# chn_noise_paras = w_results[chni]
# wireinfo = wireinfo[0][0]
rms = chn_noise_paras[1]
ped = chn_noise_paras[2]
cohrms = chn_noise_paras[14]
cohped = chn_noise_paras[15]
postrms = chn_noise_paras[7]
postped = chn_noise_paras[8]
rawdata = chn_noise_paras[3]
postdata = chn_noise_paras[9]
label = wireinfo[0] + "_ASIC" + str(wireinfo[2]) + "_CHN" + wireinfo[3]
ped_wf_subplot(axu[0],
rawdata[0:1000],
ped,
rms,
t_rate=0.5,
title="Waveforms of raw data (2MSPS)",
label=label)
ped_wf_subplot(axm[0],
cohdata[0:1000],
cohped,
cohrms,
t_rate=0.5,
title="Waveforms of coherent noise (2MSPS)",
label=label)
ped_wf_subplot(axd[0],
postdata[0:1000],
postped,
postrms,
t_rate=0.5,
title="Waveforms of post-filter data (2MSPS)",
label=label)
fig_title = apainfo[0] + "_" + apainfo[1] + "_FE%d_%s" % (wireinfo[2],
wiretype)
plt.tight_layout(rect=[0, 0.05, 1, 0.95])
fig.suptitle(fig_title, fontsize=20)
plt.savefig(out_path + fig_title + "_coh_wf_%s.png" % label,
format='png')
plt.close()
return asic_results
def plot_a_chn(out_path, rms_rootpath, fpga_rootpath, asic_rootpath, APAno = 4, \
rmsrunno = "run01rms", fpgarunno = "run01fpg", asicrunno = "run01asi",
wibno=0, fembno=0, chnno=0, gain="250", tp="20", \
jumbo_flag=False, fft_s=5000, apa="ProtoDUNE", tpcno="0" ):
input_info = ["RMS Raw data Path = %s"%rms_rootpath + rmsrunno,
"Cali(FPGA DAC) Raw data Path = %s"%fpga_rootpath + fpgarunno,
"Cali(ASIC DAC) Raw data Path = %s"%asic_rootpath + asicrunno,
"APA#%d"%APAno ,
"WIB#%d"%wibno ,
"Gain = %2.1f mV/fC"% (int(gain)/10.0) ,
"Tp = %1.1f$\mu$s"% (int(tp)/10.0) ]
out_fn = "APA%d_"%APAno + tpcno +"_WIB%d"%wibno + "_FEMB%d"%fembno + "_CHN%d"%chnno + "_Gain%s"%gain + "_Tp%s"%tp+ "_" + rmsrunno + "_" + fpgarunno + "_" + asicrunno + ".pdf"
fp = out_path + out_fn
pp = PdfPages(fp)
femb_pos_np = femb_position (APAno)
wibfemb= "WIB"+format(wibno,'02d') + "_" + "FEMB" + format(fembno,'1d')
apainfo = None
for femb_pos in femb_pos_np:
if femb_pos[1] == wibfemb:
apainfo = femb_pos
break
apa_map = APA_MAP()
apa_map.APA = apa
All_sort, X_sort, V_sort, U_sort = apa_map.apa_femb_mapping()
wireinfo = None
for onewire in All_sort:
if (int(onewire[1]) == chnno):
wireinfo = onewire
break
feset_info = [gain, tp]
rms_info = feset_info + ["RMS"]
if (os.path.exists(rms_rootpath + rmsrunno)):
rmsdata = read_rawdata(rms_rootpath, rmsrunno, wibno, fembno, chnno, gain, tp, jumbo_flag)
chn_noise_paras = noise_a_chn(rmsdata, chnno,fft_en = True, fft_s=fft_s, fft_avg_cycle=50, wibno=wibno, fembno=fembno)
ped_wf_plot(pp, apainfo, wireinfo, rms_info, chn_noise_paras)
ped_fft_plot(pp, apainfo, wireinfo, rms_info, chn_noise_paras, fl_flg=False)
ped_fft_plot(pp, apainfo, wireinfo, rms_info, chn_noise_paras, fl_flg=True)
else:
print "Path: %s%s doesnt' exist, ignore anyway"%(rms_rootpath, rmsrunno)
fpga_info = feset_info + ["FPGA-DAC Cali"]
if (os.path.exists(fpga_rootpath + fpgarunno)):
fpgadata = read_rawdata(fpga_rootpath, fpgarunno, wibno, fembno, chnno, gain, tp, jumbo_flag)
chn_cali_paras = cali_a_chn(fpgadata, chnno, wibno=wibno, fembno=fembno )
cali_wf_plot(pp, apainfo, wireinfo, fpga_info, chn_cali_paras)
cali_linear_fitplot(pp, apainfo, wireinfo, fpga_info, chn_cali_paras)
else:
print "Path: %s%s doesnt' exist, ignore anyway"%(fpga_rootpath, fpgarunno)
asic_info = feset_info + ["ASIC-DAC Cali"]
if (os.path.exists(asic_rootpath + asicrunno)):
asicdata = read_rawdata(asic_rootpath, asicrunno, wibno, fembno, chnno, gain, tp, jumbo_flag)
chn_cali_paras = cali_a_chn(asicdata, chnno, wibno=wibno, fembno=fembno )
cali_wf_plot(pp, apainfo, wireinfo, asic_info, chn_cali_paras)
cali_linear_fitplot(pp, apainfo, wireinfo, asic_info, chn_cali_paras)
else:
print "Path: %s%s doesnt' exist, ignore anyway"%(asic_rootpath, asicrunno)
pp.close()
print "results path: " + fp
def All_FEMBs_results(path,
rundir,
APA="ProtoDUNE",
APAno=1,
gain=3,
mode=0,
wib_np=[0, 1, 2, 3, 4],
tp=2,
jumbo_flag=True,
feed_freq=500,
hp_filter=False,
t_no=1):
apamap.APA = APA
runpath = path + rundir + "/"
start = timer()
for root, dirs, files in os.walk(runpath):
break
alldata = []
allresult = []
for wib in wib_np:
wibinfo_rt = "WIB" + format(wib,
"02d") + "step" + str(gain) + str(mode)
path_wib_rt = runpath + wibinfo_rt + "/"
wibinfo_ln = "WIB" + format(wib,
"02d") + "step" + str(gain) + str(mode)
path_wib_ln = runpath + wibinfo_ln + "/"
missing_wib = False
if os.path.isdir(path_wib_rt):
wibinfo = wibinfo_rt
path_wib = path_wib_rt
#print "%s"%path_wib
elif os.path.isdir(path_wib_ln):
wibinfo = wibinfo_ln
path_wib = path_wib_ln
#print "%s"%path_wib
else:
path_wib = path_wib_ln
print "%s, path doesn't exist!!!" % path_wib
missing_wib = True
if (missing_wib == False):
for root1, dirs1, rawfiles in os.walk(path_wib):
break
print("APAno", APAno)
femb_pos_np = femb_position(APAno)
#print("femb_pos_np",femb_pos_np)
apa_femb_loc, X_sort, V_sort, U_sort = apamap.apa_femb_mapping_pd()
for rawfile in rawfiles:
rawfilep = path_wib + rawfile
#print("rawfilep",rawfilep)
if (rawfilep.find(".bin") >= 0) and (rawfilep.find(wibinfo) >=
0):
wib = int(rawfilep[(rawfilep.find("WIB") +
3):(rawfilep.find("WIB") + 5)])
femb = int(rawfilep[rawfilep.find("FEMB") + 4])
chip = int(rawfilep[rawfilep.find("CHIP") + 4])
filetp = int(rawfilep[rawfilep.find("CHIP") + 6])
if os.path.isfile(rawfilep) and (filetp == tp):
with open(rawfilep, 'rb') as f:
raw_data = f.read()
len_file = len(raw_data)
for apa_loc in femb_pos_np:
if (apa_loc[1] == "WIB" + format(wib, "02d") +
"_" + "FEMB" + str(femb)):
break
smps = (len_file - 1024) / 2 / 16
if (smps > 100000):
smps = 100000
elif (smps > 20000):
smps = 20000
elif (smps > 10000):
smps = 10000
else:
pass
chn_data, feed_loc, chn_peakp, chn_peakn = raw_convertor_peak(
raw_data, smps, jumbo_flag)
for chn in range(16):
fembchn = chip * 16 + chn
for apa_info in apa_femb_loc:
if int(apa_info[1]) == fembchn:
break
rms_data = []
for oneloc in feed_loc[0:-1]:
rms_data = rms_data + chn_data[chn][
oneloc + 100:oneloc + feed_freq]
if (hp_filter == True):
flt_tmp_data = hp_flt_applied(chn_data[chn],
fs=2000000,
passfreq=1000,
flt_order=2)
flt_tmp_data = np.array(
flt_tmp_data) + np.mean(rms_data)
rms_data_tmp = []
for oneloc in feed_loc[0:-1]:
rms_data_tmp = rms_data_tmp + (
flt_tmp_data[oneloc + 100:oneloc +
feed_freq].tolist())
rms_data = rms_data_tmp
chn_full_data = flt_tmp_data
else:
rms_data = rms_data
chn_full_data = chn_data[chn]
rms_data_raw = rms_data
rms_len = len(rms_data)
raw_rms0 = np.std(rms_data[0:int(rms_len / 2)])
raw_rms1 = np.std(rms_data[int(rms_len /
2):rms_len])
if (raw_rms0 < raw_rms1):
rms_data = rms_data[0:int(rms_len / 2)]
else:
rms_data = rms_data[int(rms_len / 2):rms_len]
raw_mean = np.mean(rms_data)
raw_rms = np.std(rms_data)
sf_raw_rms = []
for tmp in rms_data:
if (tmp % 64 == 63) or (tmp % 64 == 0) or (
tmp % 64 == 1) or (tmp % 64
== 62) or (tmp % 64
== 2):
pass
else:
sf_raw_rms.append(tmp)
if (len(sf_raw_rms) > 2):
sf_mean = np.mean(sf_raw_rms)
sf_rms = np.std(sf_raw_rms)
else:
sf_rms = raw_rms
sf_mean = raw_mean
sf_ratio = (len(sf_raw_rms)) * 1.0 / (
len(rms_data))
chn_peakp_avg = np.mean(chn_peakp[chn])
chn_peakn_avg = np.mean(chn_peakn[chn])
alldata.append( [apa_loc, apa_info, wib, femb, chip, \
chn, raw_mean, raw_rms, sf_mean, sf_rms, \
sf_ratio, chn_peakp_avg, chn_peakn_avg, rms_data_raw, chn_full_data, \
feed_loc, chn_peakp[chn], chn_peakn[chn] ] )
pulsemax_data = np.max(
chn_full_data[feed_loc[0]:feed_loc[0] + 100])
pulsemax_data_loc = np.where(
chn_full_data[feed_loc[0]:feed_loc[0] +
100] == pulsemax_data)
ppeak_oft_feed = pulsemax_data_loc[0][0]
pulsemin_data = np.min(
chn_full_data[feed_loc[0]:feed_loc[0] + 100])
pulsemin_data_loc = np.where(
chn_full_data[feed_loc[0]:feed_loc[0] +
100] == pulsemin_data)
npeak_oft_feed = pulsemin_data_loc[0][0]
allresult.append( [apa_loc[0], apa_loc[1], apa_info[0], apa_info[1], apa_info[2], apa_info[3], \
wib, femb, chip, chn, \
raw_mean, raw_rms, len(rms_data), \
sf_mean, sf_rms, len(sf_raw_rms), sf_ratio, \
chn_peakp_avg, chn_peakn_avg, ppeak_oft_feed, npeak_oft_feed ] )
print "time passed = %d" % (timer() - start)
import pickle
resultpath = path + "results/" + rundir + "/"
if (os.path.exists(resultpath)):
pass
else:
try:
os.makedirs(resultpath)
except OSError:
print "Error to create a folder"
exit()
savefile = resultpath + apamap.APA + "_APA" + str(APAno) + '_gain' + str(
gain) + "_tp" + str(tp) + '_results.bin'
if (os.path.isfile(savefile)):
pass
else:
with open(savefile, "wb") as fp:
pickle.dump(allresult, fp)
if gain == 3:
str_gain = 25.0
egain = 78
elif gain == 1:
str_gain = 14.0
egain = 145
elif gain == 2:
str_gain = 7.8
egain = 250
elif gain == 0:
str_gain = 4.7
egain = 425
if tp == 3:
str_tp = 2.0
elif tp == 1:
str_tp = 3.0
elif tp == 2:
str_tp = 0.5
elif tp == 0:
str_tp = 1.0
item_n = ["APA_LOC", "WIB_FEMB", "Wire", "FEMBchn(0-127)", "FEMBasic(1-8)", "ASICchn(0-15)", \
"WIB(0-4)", "FEMB(0-4)", "ASIC(0-7)", "ASICchn(0-15)", \
"Baseline (Raw data) \ bin", "RMS(raw data) \ bin", "Sample count (raw data)", \
"Baseline (SF data) \ bin", "RMS(SF data) \ bin", "Sample count (SF data)", "SF ratio", \
"Pos_Amplitude \ bin", "Neg_Amplitude \ bin", "1st_PPeak_LOC \ bin", "1st_NPeak_LOC \ bin", \
"Gain \ mV/fC", "Shape Time / us", "Inverted gain \ e-/bin" ]
fe_paras = [str_gain, str_tp, egain]
strdate_pos = resultpath.find("Rawdata_")
strdate = resultpath[strdate_pos:strdate_pos + 18]
csvfile = resultpath + "Test" + format(
t_no, "03d"
) + "_" + strdate + "_" + rundir + "_" + apamap.APA + "_APA" + str(
APAno) + '_gain' + str(gain) + "_tp" + str(tp) + '_results.csv'
with open(csvfile, 'w') as fp:
fp.write(",".join(str(i) for i in item_n) + "," + "\n")
for x in allresult:
fp.write(",".join(str(i) for i in x) + "," +
",".join(str(i) for i in fe_paras) + "," + "\n")
return alldata
def mp_ana_a_asic(mpout, rms_rootpath, fpga_rootpath, asic_rootpath, APAno = 4, \
rmsrunno = "run01rms", fpgarunno = "run01fpg", asicrunno = "run01asi",
wibno=0, fembno=0, asicno=0, gain="250", tp="05" ,\
jumbo_flag=False, apa= "ProtoDUNE" ):
femb_pos_np = femb_position(APAno)
wibfemb = "WIB" + format(wibno, '02d') + "_" + "FEMB" + format(
fembno, '1d')
apainfo = None
for femb_pos in femb_pos_np:
if femb_pos[1] == wibfemb:
apainfo = femb_pos
break
feset_info = [gain, tp]
apa_map = APA_MAP()
apa_map.APA = apa
All_sort, X_sort, V_sort, U_sort = apa_map.apa_femb_mapping()
rmsdata = read_rawdata_fast(rms_rootpath, rmsrunno, wibno, fembno,
16 * asicno, gain, tp, jumbo_flag)
fpg_cali_flg = False
if (os.path.exists(fpga_rootpath + fpgarunno)):
fpg_cali_flg = True
fpgadata = read_rawdata_fast(fpga_rootpath, fpgarunno, wibno, fembno,
16 * asicno, gain, tp, jumbo_flag)
asi_cali_flg = False
if (os.path.exists(asic_rootpath + asicrunno)):
asi_cali_flg = True
asicdata = read_rawdata_fast(asic_rootpath, asicrunno, wibno, fembno,
16 * asicno, gain, tp, jumbo_flag)
asic_results = []
for chni in range(16):
chnno = chni + 16 * asicno
wireinfo = None
for onewire in All_sort:
if (int(onewire[1]) == chnno):
wireinfo = onewire
break
chn_noise_paras = noise_a_coh(rmsdata, chnno, fft_en=False)
rms = chn_noise_paras[1]
ped = chn_noise_paras[2]
hfrms = chn_noise_paras[7]
hfped = chn_noise_paras[8]
sfrms = chn_noise_paras[13]
sfped = chn_noise_paras[14]
unstk_ratio = chn_noise_paras[15]
if (fpg_cali_flg):
chn_fpga_paras = cali_a_chn(fpgadata, chnno)
fpg_encperlsb, fpg_chninl = cali_linear_calc(chn_fpga_paras)
else:
fpg_encperlsb, fpg_chninl = [-1, -1]
if (asi_cali_flg):
chn_asic_paras = cali_a_chn(asicdata, chnno)
asi_encperlsb, asi_chninl = cali_linear_calc(chn_asic_paras)
else:
asi_encperlsb, asi_chninl = [-1, -1]
asic_results.append([
rms, ped, hfrms, hfped, sfrms, sfped, unstk_ratio, fpg_cali_flg,
fpg_encperlsb, fpg_chninl, asi_cali_flg, asi_encperlsb, asi_chninl
])
toqueue = [apainfo, wireinfo, feset_info] + asic_results
size_toqueue = sys.getsizeof(toqueue)
if (size_toqueue * 64 > 32768):
print "Since multiprocessing.queue is using, the maximum buffer size can't exceed 32768 bytes, there is potiential risk using queue function."
print "print limit the size of to queue to less than 512bytes, or re-write mp_ana_a_asic with Pipe"
sys.exit()
else:
mpout.put(toqueue)
def pipe_ana_a_asic(cc, femb_ccs, rms_rootpath, fpga_rootpath, asic_rootpath, APAno = 4, \
rmsrunno = "run01rms", fpgarunno = "run01fpg", asicrunno = "run01asi",
wibno=0, fembno=0, asicno=0, gain="250", tp="05" ,\
jumbo_flag=False , apa= "ProtoDUNE" ):
asic_ccs = []
for ci in femb_ccs:
if (asicno == int(ci[5])):
asic_ccs.append(ci)
femb_pos_np = femb_position(APAno)
wibfemb = "WIB" + format(wibno, '02d') + "_" + "FEMB" + format(
fembno, '1d')
apainfo = None
for femb_pos in femb_pos_np:
if femb_pos[1] == wibfemb:
apainfo = femb_pos
break
feset_info = [gain, tp]
apa_map = APA_MAP()
apa_map.APA = apa
All_sort, X_sort, V_sort, U_sort = apa_map.apa_femb_mapping()
rmsdata = read_rawdata_coh(rms_rootpath, rmsrunno, wibno, fembno,
16 * asicno, gain, tp, jumbo_flag)
fpg_cali_flg = False
if (os.path.exists(fpga_rootpath + fpgarunno)):
fpg_cali_flg = True
fpgadata = read_rawdata_fast(fpga_rootpath, fpgarunno, wibno, fembno,
16 * asicno, gain, tp, jumbo_flag)
asi_cali_flg = False
if (os.path.exists(asic_rootpath + asicrunno)):
asi_cali_flg = True
asicdata = read_rawdata_fast(asic_rootpath, asicrunno, wibno, fembno,
16 * asicno, gain, tp, jumbo_flag)
cohdatax, cohdatax_flg = coh_noise_ana(asic_ccs, rmsdata, wiretype="X")
# cohdatau ,cohdatau_flg = coh_noise_ana(asic_ccs, rmsdata, wiretype = "U")
# cohdatav ,cohdatav_flg = coh_noise_ana(asic_ccs, rmsdata, wiretype = "V")
cohdatauv, cohdatauv_flg = coh_noise_ana(asic_ccs, rmsdata, wiretype="UV")
asic_results = []
for chni in range(16):
chnno = chni + 16 * asicno
wireinfo = None
for onewire in All_sort:
if (int(onewire[1]) == chnno):
wireinfo = onewire
break
if wireinfo[0][0] in "X":
cohdata = cohdatax
cohdata_flg = cohdatax_flg
# elif wireinfo[0][0] in "U":
# cohdata = cohdatauv
# cohdata_flg = cohdatauv_flg
# elif wireinfo[0][0] in "V":
# cohdata = cohdatauv
# cohdata_flg = cohdatauv_flg
elif wireinfo[0][0] in "UV":
cohdata = cohdatauv
cohdata_flg = cohdatauv_flg
chn_noise_paras = noise_a_coh(cohdata,
cohdata_flg,
rmsdata,
chnno,
fft_en=False)
rms = chn_noise_paras[1]
ped = chn_noise_paras[2]
hfrms = chn_noise_paras[7]
hfped = chn_noise_paras[8]
sfrms = chn_noise_paras[13]
sfped = chn_noise_paras[14]
unstk_ratio = chn_noise_paras[15]
if (fpg_cali_flg):
chn_fpga_paras = cali_a_chn(fpgadata, chnno)
fpg_encperlsb, fpg_chninl = cali_linear_calc(chn_fpga_paras)
else:
fpg_encperlsb, fpg_chninl = [-1, -1]
if (asi_cali_flg):
chn_asic_paras = cali_a_chn(asicdata, chnno)
asi_encperlsb, asi_chninl = cali_linear_calc(chn_asic_paras)
else:
asi_encperlsb, asi_chninl = [-1, -1]
asic_results.append([
apainfo, wireinfo, feset_info, wibno, fembno, chnno, rms, ped,
hfrms, hfped, sfrms, sfped, unstk_ratio, fpg_cali_flg,
fpg_encperlsb, fpg_chninl, asi_cali_flg, asi_encperlsb, asi_chninl
])
toqueue = asic_results
cc.send(toqueue)
cc.close()
def pipe_ana_a_asic(cc, rms_rootpath, fpga_rootpath, asic_rootpath, APAno = 4, \
rmsrunno = "run01rms", fpgarunno = "run01fpg", asicrunno = "run01asi",
wibno=0, fembno=0, asicno=0, gain="250", tp="05" ,\
jumbo_flag=False ):
femb_pos_np = femb_position(APAno)
wibfemb = "WIB" + format(wibno, '02d') + "_" + "FEMB" + format(
fembno, '1d')
apainfo = None
for femb_pos in femb_pos_np:
if femb_pos[1] == wibfemb:
apainfo = femb_pos
break
feset_info = [gain, tp]
apa_map = APA_MAP()
All_sort, X_sort, V_sort, U_sort = apa_map.apa_femb_mapping()
rmsdata = read_rawdata(rms_rootpath, rmsrunno, wibno, fembno, 16 * asicno,
gain, tp, jumbo_flag)
fpg_cali_flg = False
if (os.path.exists(fpga_rootpath + fpgarunno)):
fpg_cali_flg = True
fpgadata = read_rawdata(fpga_rootpath, fpgarunno, wibno, fembno,
16 * asicno, gain, tp, jumbo_flag)
asi_cali_flg = False
if (os.path.exists(asic_rootpath + asicrunno)):
asi_cali_flg = True
asicdata = read_rawdata(asic_rootpath, asicrunno, wibno, fembno,
16 * asicno, gain, tp, jumbo_flag)
asic_results = []
for chni in range(16):
chnno = chni + 16 * asicno
wireinfo = None
for onewire in All_sort:
if (int(onewire[1]) == chnno):
wireinfo = onewire
break
chn_noise_paras = noise_a_chn(rmsdata, chnno, fft_en=False)
rms = chn_noise_paras[1]
ped = chn_noise_paras[2]
hfrms = chn_noise_paras[7]
hfped = chn_noise_paras[8]
sfrms = chn_noise_paras[13]
sfped = chn_noise_paras[14]
unstk_ratio = chn_noise_paras[15]
if (fpg_cali_flg):
chn_fpga_paras = cali_a_chn(fpgadata, chnno)
fpg_encperlsb, fpg_chninl = cali_linear_calc(chn_fpga_paras)
else:
fpg_encperlsb, fpg_chninl = [-1, -1]
if (asi_cali_flg):
chn_asic_paras = cali_a_chn(asicdata, chnno)
asi_encperlsb, asi_chninl = cali_linear_calc(chn_asic_paras)
else:
asi_encperlsb, asi_chninl = [-1, -1]
asic_results.append([
apainfo, wireinfo, feset_info, wibno, fembno, chnno, rms, ped,
hfrms, hfped, sfrms, sfped, unstk_ratio, fpg_cali_flg,
fpg_encperlsb, fpg_chninl, asi_cali_flg, asi_encperlsb, asi_chninl
])
toqueue = asic_results
cc.send(toqueue)
cc.close()
