def reset(self, iTrace=None): self.femb = FEMB_UDP() self.figure.clf() self.subgs = [None] * 16 self.ax = [None] * 32 self.plot = [None] * 32 # 4x4 grid, one cell per channel self.gs = gridspec.GridSpec(4, 4) self.gs.update(wspace=0.2, hspace=0.2) # 2 plots per channel for row in range(4): for col in range(4): self.subgs[col + 4 * row] = gridspec.GridSpecFromSubplotSpec( 2, 1, subplot_spec=self.gs[col + 4 * row], hspace=0.0) self.ax[col + 8 * row] = self.figure.add_subplot( self.subgs[col + 4 * row][0]) self.ax[col + 8 * row].tick_params(axis='x', colors='blue') self.ax[col + 8 * row].tick_params(axis='y', colors='blue') self.ax[col + 8 * row].xaxis.tick_top() self.ax[col + 8 * row].yaxis.tick_right() self.ax[4 + col + 8 * row] = self.figure.add_subplot( self.subgs[col + 4 * row][1]) self.ax[4 + col + 8 * row].tick_params(axis='x', colors='red') self.ax[4 + col + 8 * row].tick_params(axis='y', colors='red') if iTrace is None: self.ani = animation.FuncAnimation(self.figure, self.plotData, interval=1000, blit=True) else: self.plotData(0, iTrace) self.canvas.draw()
def __init__(self): super().__init__() #declare board specific registers self.FEMB_VER = "SBND(FE-ASIC with internal DAC)" self.REG_RESET = 0 self.REG_ASIC_RESET = 1 self.REG_ASIC_SPIPROG = 2 self.REG_SEL_ASIC = 7 self.REG_SEL_CH = 7 self.REG_FESPI_BASE = 0x250 self.REG_ADCSPI_BASE = 0x200 self.REG_FESPI_RDBACK_BASE = 0x278 self.REG_ADCSPI_RDBACK_BASE = 0x228 self.REG_HS = 17 self.REG_LATCHLOC1_4 = 4 self.REG_LATCHLOC1_4_data = 0x07060707 self.REG_LATCHLOC5_8 = 14 self.REG_LATCHLOC5_8_data = 0x06060606 self.REG_CLKPHASE = 6 self.REG_CLKPHASE_data = 0xe1 self.REG_EN_CALI = 16 self.ADC_TESTPATTERN = [ 0x12, 0x345, 0x678, 0xf1f, 0xad, 0xc01, 0x234, 0x567, 0x89d, 0xeca, 0xff0, 0x123, 0x456, 0x789, 0xabc, 0xdef ] self.NASICS = 8 #initialize FEMB UDP object self.femb = FEMB_UDP() self.adc_reg = ADC_ASIC_REG_MAPPING() self.fe_reg = FE_ASIC_REG_MAPPING()
def __init__(self): #declare board specific registers self.REG_RESET = 0 self.REG_ASIC_RESET = 1 self.REG_ASIC_SPIPROG = 2 self.REG_SEL_CH = 7 #added 3/14/18 self.REG_ADCSPI_BASE = 0x200 #512 Dec self.REG_ADCSPI_RDBACK_BASE = 0x250 #592 Dec self.REG_HS = 17 # self.REG_TEST_PULSE = 5 # self.REG_TEST_PULSE_FREQ = 500 # self.REG_TEST_PULSE_DLY = 80 # self.REG_TEST_PULSE_AMPL = 0 % 32 self.REG_EN_CALI = 16 self.ADC_TESTPATTERN = [ 0x12, 0x345, 0x678, 0xf1f, 0xad, 0xc01, 0x234, 0x567, 0x89d, 0xeca, 0xff0, 0x123, 0x456, 0x789, 0xabc, 0xdef ] #initialize FEMB UDP object self.femb = FEMB_UDP() self.adc_reg = ADC_ASIC_REG_MAPPING() self.fe_reg = FE_ASIC_REG_MAPPING() self.REG_LATCHLOC1_4_data = settings.LATCHLOC_data self.REG_CLKPHASE_data = settings.CLKPHASE_data self.WIB_RESET = 1 self.BPS = 13 #Bytes per sample self.selected_chip = 0 self.selected_chn = None self.NASICS = 1
def reset(self, iTrace=None): self.femb = FEMB_UDP() self.figure.clf() self.subgs = [None] * 16 self.ax = [None] * 16 self.plot = [None] * 16 # 4x4 grid, one cell per channel self.gs = gridspec.GridSpec(4, 4) self.gs.update(wspace=0.2, hspace=0.2) # 1 plots per channel for row in range(4): for col in range(4): self.subgs[col + 4 * row] = gridspec.GridSpecFromSubplotSpec( 1, 1, subplot_spec=self.gs[col + 4 * row], hspace=0.0) self.ax[col + 4 * row] = self.figure.add_subplot( self.subgs[col + 4 * row][0]) self.ax[col + 4 * row].tick_params(axis='x', colors='black', labelsize='medium') self.ax[col + 4 * row].tick_params(axis='y', colors='black', labelsize='smaller') if iTrace is None: self.ani = animation.FuncAnimation(self.figure, self.plotData, interval=1000, blit=True) else: self.plotData(0, iTrace) self.canvas.draw()
def __init__(self): super().__init__() #declare board specific registers self.FEMB_VER = "adctest" self.REG_RESET = 0 self.REG_ASIC_RESET = 1 self.REG_ASIC_SPIPROG = 2 self.REG_SEL_ASIC = 7 self.REG_SEL_CH = 7 self.REG_FESPI_BASE = 592 self.REG_ADCSPI_BASE = 512 self.REG_FESPI_RDBACK_BASE = 632 self.REG_ADCSPI_RDBACK_BASE = 552 self.REG_HS = 17 self.REG_LATCHLOC = 4 self.REG_CLKPHASE = 6 #Latch latency 0x6666666f Phase 0xffff0055 self.ADC_TESTPATTERN = [ 0x12, 0x345, 0x678, 0xf1f, 0xad, 0xc01, 0x234, 0x567, 0x89d, 0xeca, 0xff0, 0x123, 0x456, 0x789, 0xabc, 0xdef ] self.NASICS = 1 self.FUNCGENINTER = RigolDG4000("/dev/usbtmc1", 1) self.POWERSUPPLYINTER = RigolDP800("/dev/usbtmc0", ["CH1"]) self.F2DEFAULT = 0 self.CLKDEFAULT = "fifo" #initialize FEMB UDP object self.femb = FEMB_UDP() self.adc_reg = ADC_ASIC_REG_MAPPING()
def __init__(self): #declare basic system parameters self.NFEMBS = 4 self.NASICS = 8 self.NASICCH = 16 #declare board specific registers self.FEMB_VER = "WIB_SBND" self.REG_RESET = 0 self.REG_ASIC_RESET = 1 self.REG_ASIC_SPIPROG = 2 self.REG_LATCHLOC_3_TO_0 = 4 self.REG_LATCHLOC_7_TO_4 = 14 self.REG_FPGA_TP_EN = 16 self.REG_ASIC_TP_EN = 16 self.REG_DAC_SELECT = 16 self.REG_TP = 5 self.CLK_SELECT = 6 self.CLK_SELECT2 = 15 self.REG_SEL_ASIC = 7 self.REG_SEL_ASIC_LSB = 8 self.REG_WIB_MODE = 8 self.REG_ADC_DISABLE = 8 self.REG_HS_DATA = 9 self.INT_TP_EN = 18 self.EXT_TP_EN = 18 #EXTERNAL CLOCK STUFF HERE self.REG_SPI_BASE = 512 self.REG_SPI_RDBACK_BASE = 592 self.fembNum = 0 #initialize FEMB UDP object self.femb = FEMB_UDP() self.femb.UDP_PORT_WREG = 32000 #WIB PORTS self.femb.UDP_PORT_RREG = 32001 self.femb.UDP_PORT_RREGRESP = 32002 #ASIC config variables self.feasicLeakage = 0 #0 = 500pA, 1 = 100pA self.feasicLeakagex10 = 0 #0 = pA, 1 = pA*10 self.feasicAcdc = 0 #AC = 0, DC = 1 self.feasicEnableTestInput = 1 #0 = disabled, 1 = enabled self.feasicBaseline = 0 #0 = 200mV, 1 = 900mV self.feasicGain = 1 #4.7,7.8,14,25 self.feasicShape = 3 #0.5,1,2,3 self.feasicBuf = 0 #0 = OFF, 1 = ON
def __init__(self, filedir="data"): self.femb = FEMB_UDP() self.filename = "output_write_data.bin" self.numpacketsrecord = 100 self.run = 0 self.runtype = 0 self.runversion = 0 self.date = int(datetime.datetime.today().strftime('%Y%m%d%H%M%S')) self.filedir = filedir
def reset(self): self.femb = FEMB_UDP() self.figure.clf() self.ax1 = self.figure.add_subplot(211) self.ax2 = self.figure.add_subplot(212) self.plot1 = self.ax1.plot([], []) self.plot2 = self.ax2.plot([], []) self.ani = animation.FuncAnimation(self.figure, self.plotData, interval=1000) #, blit=True) self.canvas.draw()
def __init__(self): self.NASICS = 4 #declare board specific registers self.REG_RESET = 0 self.REG_FEASIC_SPI = 5 self.REG_FESPI_BASE = 20 self.REG_FESPI_RDBACK_BASE = None self.REG_ADCSPI_RDBACK_BASE = None self.REG_HS = 17 self.REG_TEST_PULSE = 99 self.REG_TEST_PULSE_FREQ = 500 self.REG_TEST_PULSE_DLY = 80 self.REG_TEST_PULSE_AMPL = 0 % 32 self.REG_EN_CALI = 16 self.REG_RESET = 0 self.REG_DAC_VALUE = 1 self.REG_SET_DAC = 2 self.REG_START = 3 self.REG_SEL_ASIC = 4 self.REG_SEL_CH = 4 self.REG_ASIC_RESET = 5 self.REG_ASIC_SPIPROG = 5 self.REG_SAMPLE_STOP = 6 self.REG_TP_PERIOD_P = 7 self.REG_TP_PERIOD_N = 7 self.REG_TP_MODE = 9 self.REG_TST_SW = 12 self.REG_LED_CNTL = 13 self.REG_FESPI_BASE = 20 self.REG_FRAME_SIZE = 40 self.REG_DAC_ADC_EN = 60 self.REG_TST_SW = 12 self.plot = plot_functions() self.comm_settings = None #initialize FEMB UDP object self.femb = FEMB_UDP() self.fe_reg = FE_ASIC_REG_MAPPING() self.WIB_RESET = 1 self.BPS = 13 #Bytes per sample self.selected_chip = None self.selected_chn = None
def __init__(self): super().__init__() #declare board specific registers self.FEMB_VER = "35t" self.REG_RESET = 0 self.REG_ASIC_RESET = 1 self.REG_ASIC_SPIPROG = 2 self.REG_SEL_ASIC = 7 self.REG_SEL_CH = 7 self.REG_FESPI_BASE = 592 self.REG_ADCSPI_BASE = 512 self.REG_FESPI_RDBACK_BASE = 632 self.REG_ADCSPI_RDBACK_BASE = 552 self.REG_HS = 17 self.REG_LATCHLOC = 4 self.REG_CLKPHASE = 6 self.ADC_TESTPATTERN = [ 0x12, 0x345, 0x678, 0xf1f, 0xad, 0xc01, 0x234, 0x567, 0x89d, 0xeca, 0xff0, 0x123, 0x456, 0x789, 0xabc, 0xdef ] self.NASICS = 8 #initialize FEMB UDP object self.femb = FEMB_UDP() #initialiuze ASIC ch objects, specify SPI register number (firmware specific!!!) self.feasic_ch_list = [] for ch in range(0, 128, 1): chVal = int(ch) if (chVal < 0) or (chVal > 127): continue #seriously messy mapping between ch # and register bits regGrp = int((chVal % 64) / 16) regGrpLine = 7 - int((chVal % 16) / 2) regGrpBase = [27, 18, 9, 0] regNum = self.REG_FESPI_BASE + regGrpBase[regGrp] + regGrpLine regPos = (1 - chVal % 2) * 8 + int(chVal / 64) * 16 feasic_ch = FEASIC_CH_CONFIG(ch, regNum, regPos) self.feasic_ch_list.append(feasic_ch)
def __init__(self): #declare board specific registers self.FEMB_VER = "WIB_SBND" self.REG_RESET = 0 self.REG_ASIC_RESET = 1 self.REG_ASIC_SPIPROG = 2 self.REG_SEL_ASIC = 7 self.REG_SEL_ASIC_LSB = 8 self.REG_FESPI_BASE = 592 self.REG_ADCSPI_BASE = 512 self.REG_FESPI_RDBACK_BASE = 632 self.REG_ADCSPI_RDBACK_BASE = 552 self.fembNum = 0 #initialize FEMB UDP object self.femb = FEMB_UDP() self.femb.UDP_PORT_WREG = 32016 self.femb.UDP_PORT_RREG = 32017 self.femb.UDP_PORT_RREGRESP = 32018 #initialiuze ASIC ch objects, specify SPI register number (firmware specific!!!) self.feasic_ch_list = [] for ch in range(0, 128, 1): chVal = int(ch) if (chVal < 0) or (chVal > 127): continue #seriously messy mapping between ch # and register bits regGrp = int((chVal % 64) / 16) regGrpLine = 7 - int((chVal % 16) / 2) regGrpBase = [27, 18, 9, 0] regNum = self.REG_FESPI_BASE + regGrpBase[regGrp] + regGrpLine regPos = (1 - chVal % 2) * 8 + int(chVal / 64) * 16 feasic_ch = FEASIC_CH_CONFIG(ch, regNum, regPos) self.feasic_ch_list.append(feasic_ch)
def __init__(self): super().__init__() #declare board specific registers self.FEMB_VER = "quadasictest" self.NASICS = 4 self.NASICCH = 16 self.REG_RESET = 0 self.REG_DAC_VALUE = 1 self.REG_SET_DAC = 2 self.REG_START = 3 self.REG_SEL_ASIC = 4 self.REG_SEL_CH = 4 self.REG_ASIC_RESET = 5 self.REG_ASIC_SPIPROG = 5 self.REG_SAMPLE_STOP = 6 self.REG_TP_PERIOD_P = 7 self.REG_TP_PERIOD_N = 7 self.REG_TP_MODE = 9 self.REG_TST_SW = 12 self.REG_LED_CNTL = 13 self.REG_FESPI_BASE = 20 self.REG_FRAME_SIZE = 40 self.REG_DAC_ADC_EN = 60 self.feasicLeakage = 0 #0 = 500pA, 1 = 100pA self.feasicLeakagex10 = 0 #0 = pA, 1 = pA*10 self.feasicEnableTestInput = 0 #0 = disabled, 1 = enabled self.feasicBaseline = 0 #0 = 900mV, 1 = 200mV self.feasicGain = 0 #4.7,7.8,14,25 self.feasicShape = 1 #0.5,1,2,3 self.feasicAcdc = 0 #AC = 0, DC = 1 self.feasicBuf = 1 #0 = OFF, 1 = ON #initialize FEMB UDP object self.femb = FEMB_UDP()
def __init__(self): super().__init__() #declare board specific registers self.FEMB_VER = "adctest" self.REG_RESET = 0 self.REG_ASIC_RESET = 1 self.REG_ASIC_SPIPROG = 2 self.REG_SEL_ASIC = 7 self.REG_SEL_CH = 7 self.REG_FESPI_BASE = 592 self.REG_ADCSPI_BASE = 512 self.REG_FESPI_RDBACK_BASE = 632 self.REG_ADCSPI_RDBACK_BASE = 552 self.REG_HS = 17 self.REG_LATCHLOC = 4 self.REG_CLKPHASE = 6 self.ADC_TESTPATTERN = [ 0x12, 0x345, 0x678, 0xf1f, 0xad, 0xc01, 0x234, 0x567, 0x89d, 0xeca, 0xff0, 0x123, 0x456, 0x789, 0xabc, 0xdef ] self.NASICS = 1 #initialize FEMB UDP object self.femb = FEMB_UDP()
def __init__(self): #declare basic system parameters self.NFEMBS = 4 self.NASICS = 8 self.NASICCH = 16 #declare board specific registers self.FEMB_VER = "WIB_PROTODUNE" self.REG_RESET = 0 self.REG_ASIC_RESET = 1 self.REG_ASIC_SPIPROG = 2 self.REG_SOFT_ADC_RESET = 1 self.REG_LATCHLOC_3_TO_0 = 4 self.REG_LATCHLOC_7_TO_4 = 14 self.REG_FPGA_TP_EN = 16 self.REG_ASIC_TP_EN = 16 self.REG_DAC_SELECT = 16 self.REG_TP = 5 self.CLK_SELECT = 6 self.CLK_SELECT2 = 15 self.REG_SEL_ASIC = 7 self.REG_SEL_ASIC_LSB = 8 self.REG_WIB_MODE = 8 self.REG_ADC_DISABLE = 8 self.REG_HS_DATA = 9 self.REG_HS = 17 self.INT_TP_EN = 18 self.EXT_TP_EN = 18 self.REG_SPI_BASE = 0x200 self.REG_SPI_RDBACK_BASE = 0x250 #internal variables self.fembNum = 0 self.useExtAdcClock = True self.isRoomTemp = False self.maxSyncAttempts = 100 self.doReSync = True self.spiStatus = 0x0 self.syncStatus = 0x0 self.CLKSELECT_val_RT = 0xFF self.CLKSELECT2_val_RT = 0xFF self.CLKSELECT_val_CT = 0xEF self.CLKSELECT2_val_CT = 0xEF self.REG_LATCHLOC_3_TO_0_val = 0x04040404 self.REG_LATCHLOC_7_TO_4_val = 0x04040404 #initialize FEMB UDP object self.femb = FEMB_UDP() self.femb.UDP_IP = "192.168.121.1" self.femb.UDP_PORT_WREG = 32000 #WIB PORTS self.femb.UDP_PORT_RREG = 32001 self.femb.UDP_PORT_RREGRESP = 32002 self.femb.doReadBack = True #WIB register interface is unreliable #ASIC config variables self.feasicLeakage = 0 #0 = 500pA, 1 = 100pA self.feasicLeakagex10 = 0 #0 = pA, 1 = pA*10 self.feasicAcdc = 0 #AC = 0, DC = 1 self.feasicEnableTestInput = 0 #0 = disabled, 1 = enabled self.feasicBaseline = 0 #0 = 200mV, 1 = 900mV self.feasicGain = 2 #4.7,7.8,14,25 self.feasicShape = 1 #0.5,1,2,3 self.feasicBuf = 0 #0 = OFF, 1 = ON
def __init__(self,exitOnError=True): super().__init__(exitOnError=exitOnError) #declare board specific registers self.FEMB_VER = "adctestP1single" self.REG_RESET = 0 self.REG_ASIC_RESET = 1 self.REG_ASIC_SPIPROG = 2 self.REG_SEL_CH = 7 self.REG_HS = 17 self.REG_FESPI_BASE = 0x250 # 592 in decimal self.REG_ADCSPI_BASE = 0x200 # 512 in decimal self.REG_FESPI_RDBACK_BASE = 0x278 # 632 in decimal self.REG_ADCSPI_RDBACK_BASE = 0x228 # 552 in decimal self.REG_LATCHLOC1_4 = 4 self.REG_LATCHLOC5_8 = 14 self.REG_CLKPHASE = 6 self.REG_LATCHLOC1_4_data = 0x6 self.REG_LATCHLOC5_8_data = 0x0 self.REG_CLKPHASE_data = 0xfffc0000 self.REG_LATCHLOC1_4_data_1MHz = 0x5 self.REG_LATCHLOC5_8_data_1MHz = 0x0 self.REG_CLKPHASE_data_1MHz = 0xffff0000 self.REG_LATCHLOC1_4_data_cold = 0x6 self.REG_LATCHLOC5_8_data_cold = 0x0 self.REG_CLKPHASE_data_cold = 0xfffc0000 self.REG_LATCHLOC1_4_data_1MHz_cold = 0x4 self.REG_LATCHLOC5_8_data_1MHz_cold = 0x0 self.REG_CLKPHASE_data_1MHz_cold = 0xfffc0001 self.ADC_TESTPATTERN = [0x12, 0x345, 0x678, 0xf1f, 0xad, 0xc01, 0x234, 0x567, 0x89d, 0xeca, 0xff0, 0x123, 0x456, 0x789, 0xabc, 0xdef] ################################## # external clock control registers ################################## self.FPGA_FREQ_MHZ = 200 # frequency of FPGA clock in MHz self.REG_EXTCLK_RD_EN_OFF = 23 self.REG_EXTCLK_ADC_OFF = 21 self.REG_EXTCLK_ADC_WID = 22 self.REG_EXTCLK_MSB_OFF = 25 self.REG_EXTCLK_MSB_WID = 26 self.REG_EXTCLK_PERIOD = 20 self.REG_EXTCLK_LSB_FC_WID2 = 32 self.REG_EXTCLK_LSB_FC_OFF1 = 29 self.REG_EXTCLK_RD_EN_WID = 24 self.REG_EXTCLK_LSB_FC_WID1 = 30 self.REG_EXTCLK_LSB_FC_OFF2 = 31 self.REG_EXTCLK_LSB_S_WID = 28 self.REG_EXTCLK_LSB_S_OFF = 27 self.REG_EXTCLK_INV = 33 ################################## ################################## self.NASICS = 1 self.FUNCGENINTER = Keysight_33600A("/dev/usbtmc1",1) self.POWERSUPPLYINTER = RigolDP800("/dev/usbtmc0",["CH2","CH3","CH1"]) # turn on CH2 first self.F2DEFAULT = 0 self.CLKDEFAULT = "fifo" ## Firmware update related variables self.FIRMWAREPATH2MHZ = "/home/oper/Documents/CarlosForkedRepo/femb_python/femb_python/test_measurements/adc_clock_test/code/S_SKT_ADC_CHP_TST.sof" #self.FIRMWAREPATH1MHZ = "/opt/sw/releases/femb_firmware-0.1.0/adc_tester/S7_1M_SBND_FPGA.sof" self.FIRMWAREPROGEXE = "/opt/sw/intelFPGA/17.0/qprogrammer/bin/quartus_pgm" #self.FIRMWAREPROGCABLE = "USB-Blaster" self.FIRMWAREPROGCABLE = "USB-BlasterII" self.SAMPLERATE = 2e6 #initialize FEMB UDP object self.femb = FEMB_UDP() self.adc_reg = ADC_ASIC_REG_MAPPING()
def __init__(self, exitOnError=True): super().__init__(exitOnError=exitOnError) #declare board specific registers self.FEMB_VER = "adctestP1quad" self.REG_RESET = 0 # bit 0 system, 1 reg, 2 alg, 3 udp self.REG_PWR_CTRL = 1 # bit 0-3 pwr, 8-15 blue LEDs near buttons self.REG_ASIC_SPIPROG_RESET = 2 # bit 0 FE SPI, 1 ADC SPI, 4 FE ASIC RESET, 5 ADC ASIC RESET, 6 SOFT ADC RESET & SPI readback check # I zero out REG_ASIC_SPIPROG_RESET a lot because only transitions from 0 to 1 do anything self.REG_SEL_CH = 3 # bit 0-7 chip, 8-15 channel, 31 WIB mode self.REG_DAC1 = 4 # bit 0-15 DAC val, 16-19 tp mode select, 31 set dac self.REG_DAC2 = 5 # bit 0-15 tp period, 16-31 tp shift self.REG_FPGA_TST_PATT = 6 # bit 0-11 tst patt, 16 enable self.REG_ADC_CLK = 7 # bit 0-3 clk phase, 8 clk speed sel self.REG_LATCHLOC = 8 # bit 0-7 ADC1, 8-15 ADC2, 16-23 ADC3, 24-31 ADC4 self.REG_STOP_ADC = 9 # bit 0 stops sending convert, read ADC HEADER redundant with reg 2 self.REG_UDP_FRAME_SIZE = 63 # bits 0-11 self.REG_FIRMWARE_VERSION = 0xFF # 255 in decimal self.CONFIG_FIRMWARE_VERSION = 259 # this file is written for this self.REG_LATCHLOC_data_2MHz = 0x02020202 self.REG_LATCHLOC_data_1MHz = 0x0 self.REG_LATCHLOC_data_2MHz_cold = 0x02020202 self.REG_LATCHLOC_data_1MHz_cold = 0x0 self.REG_CLKPHASE_data_2MHz = 0x4 self.REG_CLKPHASE_data_1MHz = 0x0 self.REG_CLKPHASE_data_2MHz_cold = 0x4 self.REG_CLKPHASE_data_1MHz_cold = 0x0 self.DEFAULT_FPGA_TST_PATTERN = 0x12 self.ADC_TESTPATTERN = [ 0x12, 0x345, 0x678, 0xf1f, 0xad, 0xc01, 0x234, 0x567, 0x89d, 0xeca, 0xff0, 0x123, 0x456, 0x789, 0xabc, 0xdef ] # registers 64-88 are SPI to ASICs # 88 is last register besides 255 which is firmware version self.REG_FESPI_BASE = 84 # this configures all FE ASICs self.REG_ADCSPI_BASES = [64, 69, 74, 79] # for each chip self.REG_EXTCLK_INV = 10 self.REG_EXTCLK_BASES = [11, 20, 29, 38] # for each chip self.FPGA_FREQ_MHZ = 200 # frequency of FPGA clock in MHz self.REG_PLL_BASES = [17, 26, 35, 44] # for each chip self.NASICS = 4 #self.FUNCGENINTER = DummyFuncGen("","") self.FUNCGENINTER = Keysight_33600A("/dev/usbtmc0", 1) self.POWERSUPPLYINTER = DummyPowerSupply("", "") self.F2DEFAULT = 0 self.CLKDEFAULT = "fifo" self.SAMPLERATE = 2e6 #initialize FEMB UDP object self.femb = FEMB_UDP() self.adc_regs = [] for i in range(self.NASICS): self.adc_regs.append(ADC_ASIC_REG_MAPPING()) #self.defaultConfigFunc = lambda: self.configAdcAsic() self.defaultConfigFunc = lambda: self.configAdcAsic(clockMonostable= True)
def __init__(self): #set up UDP interface self.femb = FEMB_UDP()
def __init__(self, exitOnError=False): super().__init__(exitOnError=exitOnError) #declare board specific registers self.FEMB_VER = "adctestP1quad" self.REG_RESET = 0 # bit 0 system, 1 reg, 2 alg, 3 udp self.REG_PWR_CTRL = 1 # bit 0-3 pwr, 8-15 blue LEDs near buttons self.REG_ASIC_SPIPROG_RESET = 2 # bit 0 FE SPI, 1 ADC SPI, 4 FE ASIC RESET, 5 ADC ASIC RESET, 6 SOFT ADC RESET & SPI readback check self.REG_SEL_CH = 3 # bit 0-7 chip, 8-15 channel, 31 WIB mode self.REG_DAC1 = 4 # bit 0-15 DAC val, 16-19 tp mode select, 31 set dac self.REG_DAC2 = 5 # bit 0-15 tp period, 16-31 tp shift self.REG_FPGA_TST_PATT = 6 # bit 0-11 tst patt, 16 enable self.REG_ADC_CLK = 7 # bit 0-3 clk phase, 8 clk speed sel self.REG_LATCHLOC = 8 # bit 0-7 ADC1, 8-15 ADC2, 16-23 ADC3, 24-31 ADC4 self.REG_STOP_ADC = 9 # bit 0 stops sending convert, read ADC HEADER redundant with reg 2 self.REG_UDP_FRAME_SIZE = 63 # bits 0-11 self.REG_FIRMWARE_VERSION = 0xFF # 255 in decimal self.CONFIG_FIRMWARE_VERSION = 0x105 # this file is written for this self.REG_LATCHLOC_data_2MHz = 0x02010201 self.REG_LATCHLOC_data_1MHz = 0x0 self.REG_LATCHLOC_data_2MHz_cold = 0x02010201 self.REG_LATCHLOC_data_1MHz_cold = 0x0 self.REG_CLKPHASE_data_2MHz = 0x4 self.REG_CLKPHASE_data_1MHz = 0x1 self.REG_CLKPHASE_data_2MHz_cold = 0x0 #double check socket 1 value self.REG_CLKPHASE_data_1MHz_cold = 0x0 self.REG_HDR_ERROR_RESET = 47 self.REG_HDR_ERROR_BASES = [49, 51, 53, 55] # for each chip self.DEFAULT_FPGA_TST_PATTERN = 0x12 self.ADC_TESTPATTERN = [ 0x12, 0x345, 0x678, 0xf1f, 0xad, 0xc01, 0x234, 0x567, 0x89d, 0xeca, 0xff0, 0x123, 0x456, 0x789, 0xabc, 0xdef ] # registers 64-88 are SPI to ASICs # 88 is last register besides 255 which is firmware version self.REG_FESPI_BASE = 84 # this configures all FE ASICs self.REG_ADCSPI_BASES = [64, 69, 74, 79] # for each chip self.REG_EXTCLK_INV = 10 self.REG_EXTCLK_BASES = [11, 20, 29, 38] # for each chip self.FPGA_FREQ_MHZ = 200 # frequency of FPGA clock in MHz self.REG_PLL_BASES = [17, 26, 35, 44] # for each chip self.NASICS = 4 self.F2DEFAULT = 0 self.CLKDEFAULT = "fifo" self.isExternalClock = True #False = internal monostable, True = external self.is1MHzSAMPLERATE = False #True = 1MHz, False = 2MHz self.COLD = False self.enableTest = 0 self.doSpiWrite = True self.doReSync = True self.scanSyncSettings = True self.adcSyncStatus = False self.maxSyncAttempts = 10 self.numSyncTests = 25 #initialize FEMB UDP object self.femb = FEMB_UDP() #list of adc configuration register mappings self.adc_regs = ADC_ASIC_REG_MAPPING()
def __init__(self): #declare basic system parameters self.NFEMBS = 4 self.NASICS = 8 self.NASICCH = 16 #declare board specific registers self.FEMB_VER = "WIB_SBND" self.REG_RESET = 0 self.REG_ASIC_RESET = 1 self.REG_ASIC_SPIPROG = 2 self.REG_SOFT_ADC_RESET = 1 self.REG_LATCHLOC_3_TO_0 = 4 self.REG_LATCHLOC_7_TO_4 = 14 self.REG_FPGA_TP_EN = 16 self.REG_ASIC_TP_EN = 16 self.REG_DAC_SELECT = 16 self.REG_TP = 5 self.CLK_SELECT = 6 self.CLK_SELECT2 = 15 self.REG_SEL_ASIC = 7 self.REG_SEL_ASIC_LSB = 8 self.REG_WIB_MODE = 8 self.REG_ADC_DISABLE = 8 self.REG_HS_DATA = 9 self.REG_HS = 17 self.INT_TP_EN = 18 self.EXT_TP_EN = 18 self.REG_SPI_BASE = 0x200 self.REG_SPI_RDBACK_BASE = 0x250 self.REG_TEST_PAT = 3 self.REG_TEST_PAT_DATA = 0x01230000 #internal variables self.fembNum = 0 self.wibNum = 0 self.useExtAdcClock = True self.isRoomTemp = False self.doReSync = True self.spiStatus = 0x0 self.syncStatus = 0x0 self.CLKSELECT_val_RT = 0xFF self.CLKSELECT2_val_RT = 0xFF self.CLKSELECT_val_CT = 0xEF self.CLKSELECT2_val_CT = 0xEF self.REG_LATCHLOC_3_TO_0_val = 0x04040404 self.REG_LATCHLOC_7_TO_4_val = 0x04040404 self.fe_regs = [0x00000000]*(16+2)*8*8 self.fe_REGS = [0x00000000]*(8+1)*4 self.useLArIATmap = False #True #COTS shifts self.fe1_sft_RT = 0x00000000 self.fe2_sft_RT = 0x00000000 self.fe3_sft_RT = 0x00000000 self.fe4_sft_RT = 0x00000000 self.fe5_sft_RT = 0x00000000 self.fe6_sft_RT = 0x00000000 self.fe7_sft_RT = 0x00000000 self.fe8_sft_RT = 0x00000000 self.fe1_sft_CT = 0x00000000 self.fe2_sft_CT = 0x00000000 self.fe3_sft_CT = 0x00000000 self.fe4_sft_CT = 0x00000000 self.fe5_sft_CT = 0x00000000 self.fe6_sft_CT = 0x00000000 self.fe7_sft_CT = 0x00000000 self.fe8_sft_CT = 0x00000000 #COTS phases self.fe1_pha_RT = 0x00000000 self.fe2_pha_RT = 0x00000000 self.fe3_pha_RT = 0x00000000 self.fe4_pha_RT = 0x00000000 self.fe5_pha_RT = 0x00000000 self.fe6_pha_RT = 0x00000000 self.fe7_pha_RT = 0x00000000 self.fe8_pha_RT = 0x00000000 self.fe1_pha_CT = 0x00000000 self.fe2_pha_CT = 0x00000000 self.fe3_pha_CT = 0x00000000 self.fe4_pha_CT = 0x00000000 self.fe5_pha_CT = 0x00000000 self.fe6_pha_CT = 0x00000000 self.fe7_pha_CT = 0x00000000 self.fe8_pha_CT = 0x00000000 #initialize FEMB UDP object self.femb = FEMB_UDP() self.femb.UDP_PORT_WREG = 32000 #WIB PORTS self.femb.UDP_PORT_RREG = 32001 self.femb.UDP_PORT_RREGRESP = 32002 self.femb.doReadBack = False #WIB register interface is unreliable #ASIC config variables self.feasicLeakage = 0 #0 = 500pA, 1 = 100pA self.feasicLeakagex10 = 0 #0 = pA, 1 = pA*10 self.feasicAcdc = 0 #AC = 0, DC = 1 self.feasicBaseline = 0 #0 = 900mV, 1 = 200mV self.feasicEnableTestInput = 0 #0 = disabled, 1 = enabled self.feasicGain = 2 #4.7,7.8,14,25 self.feasicShape = 1 #0.5,1,2,3 self.feasicBuf = 1 #0 = OFF, 1 = ON #Read in LArIAT mapping if desired if self.useLArIATmap: self.cppfr = CPP_FILE_RUNNER() with open(self.cppfr.filename('configuration/configs/LArIAT_pin_mapping.map'), "rb") as fp: self.lariatMap = pickle.load(fp) #APA Mapping va = self.lariatMap va_femb = [] for vb in va: if int(vb[9]) in (0,1,2,3,4) : va_femb.append(vb) apa_femb_loc = [] for chn in range(128): for vb in va_femb: if int(vb[8]) == chn: if (vb[1].find("Co")) >= 0 :#collection wire chninfo = [ "X" + vb[0], vb[8], int(vb[6]), int(vb[7]), int(vb[9]), int(vb[10])] elif (vb[1].find("In")) >= 0 : #induction wire chninfo = [ "U" + vb[0], vb[8], int(vb[6]), int(vb[7]), int(vb[9]), int(vb[10])] apa_femb_loc.append(chninfo) for chn in range(128): fl_w = True fl_i = 0 for tmp in apa_femb_loc: if int(tmp[1]) == chn: fl_w = False break if (fl_w): chninfo = [ "V" + format(fl_i, "03d"), format(chn, "03d"), chn//16 , format(chn%15, "02d"), apa_femb_loc[0][4], apa_femb_loc[0][5]] apa_femb_loc.append(chninfo) fl_i = fl_i + 1 self.All_sort = [] self.X_sort = [] self.V_sort = [] self.U_sort = [] for i in range(128): for chn in apa_femb_loc: if int(chn[1][0:3]) == i : self.All_sort.append(chn) for chn in apa_femb_loc: if chn[0][0] == "X" and int(chn[0][1:3]) == i : self.X_sort.append(chn) for chn in apa_femb_loc: if chn[0][0] == "V" and int(chn[0][1:3]) == i : self.V_sort.append(chn) for chn in apa_femb_loc: if chn[0][0] == "U" and int(chn[0][1:3]) == i : self.U_sort.append(chn) self.WireDict = {} for line in self.All_sort: key = "wib{:d}_femb{:d}_chip{:d}_chan{:02d}".format(line[5],line[4],line[2],line[3]) self.WireDict[key] = line[0]