def top_odd_even(state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x,
z, xfifo, zfifo, flgs_i, update_i, res_o, update_o,
end_of_col, empty_r, full_r, enr_r, enw_r, dataout_r,
datain_r, empty_ro, full_ro, enr_ro, enw_ro, dataout_ro,
datain_ro, addr_in, del_ctn):
instance_Odd_Even_Fsm = Odd_Even_Fsm(state, clk, rst_fsm, addr_left,
muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i,
right_i, do_first, x, z, flgs_i,
update_i, res_o, update_o, end_of_col,
addr_in, xfifo, enr_r, enw_r, del_ctn)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr,
addr_in, muxsel_i, muxaddrsel, addr_left,
addr_sam, addr_rht, zfifo)
instance_signed2twoscomplement = signed2twoscomplement(clk, x, z)
instance_signed2twoscomplementfifo = signed2twoscomplement(
clk, xfifo, zfifo)
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i,
clk, res_o, update_o)
instance_pc_in = fifo(clk, empty_r, full_r, enr_r, enw_r, dataout_r,
datain_r)
instance_pc_out = fifo(clk, empty_ro, full_ro, enr_ro, enw_ro, dataout_ro,
datain_ro)
#instance_pd_read = pc_read(clk, data_in, toLift_Step, we_in, addr_in, muxsel_i, datactn_in, datactn, pc_data_in, pc_data_rdy )
return instances()
def top_odd_even(state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x, z, xfifo,
zfifo, flgs_i, update_i, res_o, update_o, end_of_col, empty_r, full_r,
enr_r, enw_r, dataout_r, datain_r , empty_ro, full_ro, enr_ro, enw_ro,
dataout_ro, datain_ro, addr_in, del_ctn):
instance_Odd_Even_Fsm = Odd_Even_Fsm (state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht, muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x, z, flgs_i, update_i, res_o, update_o, end_of_col, addr_in, xfifo, enr_r, enw_r, del_ctn)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr, addr_in, muxsel_i, muxaddrsel, addr_left, addr_sam, addr_rht,zfifo)
instance_signed2twoscomplement = signed2twoscomplement(clk, x, z)
instance_signed2twoscomplementfifo = signed2twoscomplement(clk, xfifo, zfifo)
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i, clk, res_o, update_o)
instance_pc_in = fifo(clk, empty_r, full_r, enr_r, enw_r, dataout_r, datain_r)
instance_pc_out = fifo(clk, empty_ro, full_ro, enr_ro, enw_ro, dataout_ro, datain_ro)
#instance_pd_read = pc_read(clk, data_in, toLift_Step, we_in, addr_in, muxsel_i, datactn_in, datactn, pc_data_in, pc_data_rdy )
return instances()
def chose_industry_corr(self):
ind_corr = self.chose_industry().T.corr()
industry = self.get_all_industry()
ff_max = fifo.fifo(10, 0)
ff_min = fifo.fifo(10, 1)
for i in range(110):
for j in range(110):
if i >= j:
continue
if ind_corr[industry[i]][industry[j]] > ff_max.min().k:
ff_max.insert(ind_corr[industry[i]][industry[j]],
[industry[i], industry[j]])
if ind_corr[industry[i]][industry[j]] < ff_min.max().k:
ff_min.insert(ind_corr[industry[i]][industry[j]],
[industry[i], industry[j]])
print(ff_max.ff)
print(ff_min.ff)
def main():
header()
select = st.selectbox(label='Escolha o que deseja visualizar',
options=options,
format_func=lambda x: display[x])
st.write("---------------")
if select == 0:
st.write('Algoritmo: **FIFO**')
fifo()
if select == 1:
st.write('Algoritmo: **LRU**')
lru()
if select == 2:
st.write('Algoritmo: **Ótimo**')
otimo()
def __init__(self):
self.gcycle = 0
#self.t
self.DEVCPS = 0
self.DEVCPM = 0
self.minute_cpsf = fifo.fifo(
60) # this FIFO contains the last 60 DEVCPS samples ("1 minute")
self.multimin_cpmf = fifo.fifo(
15) # this FIFO contains multiple minutes
#self.logif = fifo.dFifo(1) # temporary sizing
#self.cp15mf = fifo.numFifo(4*24)
self.avrcounts = 0 # counts accumulated over the arbitrary averaging period
self.avrcycles = 0
self.avrdt = 0 # (running) averaging time period
self.avrcpm_dt = 0.0 # result of average in CPM
self.avrcpm_cyc = 0.0
self.avrreldev = 0.0 # relative uncertainty of average based on number of counts, 1/sqrt(counts)
self.logblocknum = 0
self.logcyc = 0 #cycles since the last logfile write
self.lccounts = 0.0 # counts since the last logfile write
def run(select="both", frames=3, pages=20, verbose="no"):
if select == "fifo":
chain = load()
average = 0
for i in chain:
w = fifo(i, frames, pages, verbose=verbose)
print("\nPage faults for second chance FIFO:", w, end='')
average += w
average /= len(chain)
print("\nAverage page faults for second chance FIFO", average)
with open("output_fifo.csv", "a") as f:
f.write("\nAverage page faults for FIFO " + str(average))
elif select == "lru":
chain = load()
average = 0
for i in chain:
w = lru(i, frames, pages, verbose)
print("\nPage faults for LRU:", w, end='')
average += w
average /= len(chain)
print("\nAverage page faults for LRU", average)
with open("output_lru.csv", "a") as f:
f.write("\nAverage page faults for LRU " + str(average))
else:
chain = load()
average_fifo = average_lru = 0
for i in chain:
average_fifo += fifo(i, frames, pages, verbose=verbose)
average_lru += lru(i, frames, pages, verbose=verbose)
average_fifo /= len(chain)
average_lru /= len(chain)
print("\nAverage page faults for second chance FIFO", average_fifo)
with open("output_fifo.csv", "a") as f:
f.write("\nAverage page faults for FIFO " + str(average_fifo))
print("\nAverage page faults for LRU", average_lru)
with open("output_lru.csv", "a") as f:
f.write("\nAverage page faults for LRU " + str(average_lru))
def login (self, callback):
self.login_callback = callback
self.buffer = ''
self.set_terminator (None)
address = self.server_address
if type(address) == type(''):
self.create_socket (socket.AF_UNIX, socket.SOCK_STREAM)
else:
self.create_socket (socket.AF_INET, socket.SOCK_STREAM)
self._connected = 0
self.connect (address)
self.auth = self.AS_LOGIN
self.state = self.PS_HEADER
self.query_fifo = fifo()
def __init__ (self, address=('idb', 3001)):
asynchat.async_chat.__init__ (self)
if type(address) is type(''):
family = socket.AF_UNIX
else:
family = socket.AF_INET
self.create_socket (family, socket.SOCK_STREAM)
self.address = address
self.request_fifo = fifo.fifo()
self.buffer = []
self.pstate = self.STATE_LENGTH
self.set_terminator (8)
self._connected = 0
self.connect (self.address)
def page_fault(algorithm, pages, frames, results):
if algorithm not in results:
if algorithm == "FIFO":
results[algorithm] = fifo(pages, frames)
elif algorithm == "LRU":
results[algorithm] = lru(pages, frames)
elif algorithm == "LFU":
results[algorithm] = lfu(pages, frames)
elif algorithm == "OPT":
results[algorithm] = opt(pages, frames)
elif algorithm == "RAND":
results[algorithm] = rand(pages, frames)
elif algorithm == "MFU":
results[algorithm] = mfu(pages, frames)
elif algorithm == "MRU":
results[algorithm] = mru(pages, frames)
else:
return -1
return results[algorithm]
def case_fifo(timestamp):
# generate list of calls and pages
global list_of_calls, list_of_frames
list_of_calls = generate_calls(cfg["FIFO"]["CALLS_RANGE"],
cfg["FIFO"]["CALLS_VALUE_RANGE"])
list_of_frames = generate_frames(cfg['FIFO']['FRAMES_RANGE'])
reason = 'FIFO_CALLS'
if cfg["SUB"]["USE_FIFO_TO_LRU"]:
reason = "FIFO_&_LRU_CALLS"
# save generated calls
if cfg["EXE"]["TXT"]:
save_calls(reason, list_of_calls, timestamp)
# execute the algorithm
fifo_result = fifo(list_of_calls, list_of_frames)
# save results
if cfg["EXE"]["TXT"]:
save_pages('FIFO_DONE', list_of_calls, fifo_result, timestamp)
# make a plot
if cfg["EXE"]["GRAPHS"]:
frames_plot('FIFO', list_of_calls, fifo_result, timestamp)
def __init__(self):
self.distance = 0
self.callsign = callsign
self.mc_callsign = mc_callsign
self.sstv_mode = "Robot36"
self.calculate_az_el = True
'''
datetime -> io_handler -> camera_handler -> image'
'''
self.io = io_handler()
'''
callsign -> fifo -> encoder'
variables -> fifo' -> encoder'
datetime -> fifo'
'''
self.fifo = fifo(callsign=self.callsign, mc_callsign=self.mc_callsign)
self.fifo.set_master_io(self.io) # Rule [1]
self.io.set_master_fifo(self.fifo) # Rule [1]
'''
mode -> camera_handler -> image'
'''
self.io.set_camera_handler(mode=self.sstv_mode) # Rule [2]
self.io.set_serial_handler() # Rule [2]
'''
main -> tcom_handler'
'''
self.task = tcom_handler(main=self,
callsign=self.callsign,
fifo=self.fifo,
io=self.io,
mode=self.sstv_mode)
self.tracker = Tracker(latitude='6.2405 S',
longitude='106.9501 E',
master_io=self.io)
self.dopFreq = ''
import fifo
import lru
import re
alg = None
num = None
while (alg != 'c' and alg != 'f' and alg != 'l'):
print('>> Which paging alg? [c]lock, [f]ifo, or [l]ru:')
alg = input()
while (not isinstance(num, int)):
print('>> Number of Pages in memory (int):')
num = input()
try:
num = int(num)
except ValueError:
print('Try an integer!')
num = None
print('>> References (space separated - "A B A C B"):')
refs = input()
refs = re.split('\s+', refs.strip())
if alg == 'c':
clock.clock(refs, num)
elif alg == 'f':
fifo.fifo(refs, num)
elif alg == 'l':
lru.lru(refs, num)
# test prints a test run of each algorithm with a given input and frame count.
def test(input, frames, doPrint):
print 'Optimal', optimal.optimal(input[:], frames, doPrint)
print 'FIFO', fifo.fifo(input, frames, doPrint)
print 'LRU', lru.lru(input,frames, doPrint)
print 'LFU', lfu.lfu(input, frames, doPrint)
print 'Weighted', weight.weight(input, frames, 4, 1, doPrint)
# Run algorithms for 3 and 4 frames on a basic input and print the results.
doPrint = True # Whether or not to print results to the console.
input = [1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5] # List that the algorithms will run on.
frames = 3 # Number of frames for the pages list.
while frames < 5:
print 'Page faults: {}\n'.format(optimal.optimal(input, frames, doPrint))
print 'Page faults: {}\n'.format(fifo.fifo(input, frames, doPrint))
print 'Page faults: {}\n'.format(lru.lru(input,frames, doPrint))
print 'Page faults: {}\n'.format(lfu.lfu(input, frames, doPrint))
# Run Weighted with increasing frequency multipliers.
i = 1 # Loop variable, and frequency multiplier for Weighted.
while i < 10:
print 'Page faults: {}\n'.format(weight.weight(input, frames, i, 1, doPrint))
i += 1
frames += 1
# Get input data.
input = [] # Reset input.
def tb(state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x, z,xfifo,
zfifo, flgs_i, update_i, res_o, update_o, end_of_col, empty_r, full_r,
enr_r, enw_r, dataout_r, datain_r, empty_ro, full_ro, enr_ro, enw_ro,
dataout_ro, datain_ro, addr_in, del_ctn ):
instance_Odd_Even_Fsm = Odd_Even_Fsm (state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht, muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x, z, flgs_i, update_i, res_o, update_o, end_of_col, addr_in, xfifo, enr_r, enw_r, del_ctn)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr, addr_in, muxsel_i, muxaddrsel, addr_left, addr_sam, addr_rht,zfifo)
instance_signed2twoscomplement = signed2twoscomplement(clk, x, z)
instance_signed2twoscomplementfifo = signed2twoscomplement(clk, xfifo, zfifo)
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i, clk, res_o, update_o)
instance_pc_in = fifo(clk, empty_r, full_r, enr_r, enw_r, dataout_r, datain_r)
instance_pc_out = fifo(clk, empty_ro, full_ro, enr_ro, enw_ro, dataout_ro, datain_ro)
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
rst_fsm.next = 0
yield clk.posedge
muxsel_i.next = 0
yield clk.posedge
enr_r.next = 0
yield clk.posedge
enw_r.next = 0
yield clk.posedge
datain_r.next = m[0][0]
yield clk.posedge
enw_r.next = 1
yield clk.posedge
for j in range(1,255):
k = 0
if (full_r == 0):
datain_r.next = m[j][k]
yield clk.posedge
#print ("%d %d %d %d %d") % (now(), j, enw_r, full_r, m[j][k])
enw_r.next = 0
yield clk.posedge
muxsel_i.next = 0
yield clk.posedge
rst_fsm.next = 1
yield clk.posedge
print ("%d muxsel_i %d rst_fsm %d") % (now(), muxsel_i, rst_fsm)
while (end_of_col == 0):
print ("time %d flgs %d left %d sam %d right %d ") % (now(), flgs_i, left_i, sam_i, right_i)
print ("time %d addr %d din %d we %d ") % (now(), addr, din, we)
yield clk.posedge
print ("%d ") % (now())
print "end of col"
muxsel_i.next = 1
yield clk.posedge
rst_fsm.next = 0
yield clk.posedge
addr_in.next = 0
yield clk.posedge
we_in.next = 0
m[0][k] = dout
datain_ro.next= m[0][k]
yield clk.posedge
print ("%d data to ram %d %d") % (now(), datain_ro, addr_in)
addr_in.next = addr_in + 1
yield clk.posedge
enw_ro.next = 1
yield clk.posedge
for j in range(1,254):
m[0][k] = dout
datain_ro.next= m[j][k]
yield clk.posedge
addr_in.next = addr_in + 1
print ("%d data to ram %d %d") % (now(), datain_ro, addr_in)
yield clk.posedge
enw_ro.next = 1
yield clk.posedge
raise StopSimulation
return instances()
def test(input, frames, doPrint): print 'Optimal', optimal.optimal(input[:], frames, doPrint) print 'FIFO', fifo.fifo(input, frames, doPrint) print 'LRU', lru.lru(input,frames, doPrint) print 'LFU', lfu.lfu(input, frames, doPrint) print 'Weighted', weight.weight(input, frames, 4, 1, doPrint)
def __init__(self):
self.mon = threading.RLock()
self.cv = threading.Condition(self.mon)
self.queue = fifo.fifo()
def cosim_dut(self, cosim_name, fifo_args, whitebox_args):
"""Get the ``Cosimulation`` object.
:param cosim_name: The name of the cosimulation.
:param fifo_args: A dictionary of args to pass to the FIFOs.
:param whitebox_args: A dictionary of args to pass to the Whitebox Peripheral.
:returns: A `myhdl.Cosimulation` object.
"""
bus_pclk = self.bus.pclk
bus_paddr = self.bus.paddr
bus_psel = self.bus.psel
bus_penable = self.bus.penable
bus_pwrite = self.bus.pwrite
bus_pwdata = self.bus.pwdata
bus_pslverr = self.bus.pslverr
bus_pready = self.bus.pready
bus_prdata = self.bus.prdata
clearn = ResetSignal(0, 0, async=True)
fifo_depth = fifo_args['depth']
tx_fifo_re = Signal(bool(False))
tx_fifo_rclk = self.dac_clock
tx_fifo_rdata = Signal(intbv(0)[32:])
tx_fifo_we = Signal(bool(False))
tx_fifo_wclk = self.bus.pclk
tx_fifo_wdata = Signal(intbv(0)[32:])
tx_fifo_full = Signal(bool(False))
tx_fifo_afull = Signal(bool(False))
tx_fifo_empty = Signal(bool(True))
tx_fifo_aempty = Signal(bool(True))
tx_fifo_afval = Signal(intbv(fifo_depth - 1)[10:])
tx_fifo_aeval = Signal(intbv(0)[10:])
tx_fifo_wack = Signal(bool(False))
tx_fifo_dvld = Signal(bool(False))
tx_fifo_overflow = Signal(bool(False))
tx_fifo_underflow = Signal(bool(False))
tx_fifo_rdcnt = Signal(intbv(0, min=0, max=fifo_depth + 1))
tx_fifo_wrcnt = Signal(intbv(fifo_depth, min=0, max=fifo_depth + 1))
tx_fifo_signals = (
clearn,
tx_fifo_re,
tx_fifo_rclk,
tx_fifo_rdata,
tx_fifo_we,
tx_fifo_wclk,
tx_fifo_wdata,
tx_fifo_full,
tx_fifo_afull,
tx_fifo_empty,
tx_fifo_aempty,
tx_fifo_afval,
tx_fifo_aeval,
tx_fifo_wack,
tx_fifo_dvld,
tx_fifo_overflow,
tx_fifo_underflow,
tx_fifo_rdcnt,
tx_fifo_wrcnt)
tx_fifo = fifo(*tx_fifo_signals, **fifo_args)
rx_fifo_depth = fifo_args['depth']
rx_fifo_re = Signal(bool(False))
rx_fifo_rclk = self.bus.pclk
rx_fifo_rdata = Signal(intbv(0)[32:])
rx_fifo_we = Signal(bool(False))
rx_fifo_wclk = self.dac_clock
rx_fifo_wdata = Signal(intbv(0)[32:])
rx_fifo_full = Signal(bool(False))
rx_fifo_afull = Signal(bool(False))
rx_fifo_empty = Signal(bool(True))
rx_fifo_aempty = Signal(bool(True))
rx_fifo_afval = Signal(intbv(fifo_depth - 1)[10:])
rx_fifo_aeval = Signal(intbv(0)[10:])
rx_fifo_wack = Signal(bool(False))
rx_fifo_dvld = Signal(bool(False))
rx_fifo_overflow = Signal(bool(False))
rx_fifo_underflow = Signal(bool(False))
rx_fifo_rdcnt = Signal(intbv(0, min=0, max=fifo_depth + 1))
rx_fifo_wrcnt = Signal(intbv(fifo_depth, min=0, max=fifo_depth + 1))
rx_fifo_signals = (
clearn,
rx_fifo_re,
rx_fifo_rclk,
rx_fifo_rdata,
rx_fifo_we,
rx_fifo_wclk,
rx_fifo_wdata,
rx_fifo_full,
rx_fifo_afull,
rx_fifo_empty,
rx_fifo_aempty,
rx_fifo_afval,
rx_fifo_aeval,
rx_fifo_wack,
rx_fifo_dvld,
rx_fifo_overflow,
rx_fifo_underflow,
rx_fifo_rdcnt,
rx_fifo_wrcnt)
rx_fifo = fifo(*rx_fifo_signals, **fifo_args)
config_file = tempfile.NamedTemporaryFile(delete=False)
config_file.write('+define+COSIM_NAME="%s"' % (cosim_name,))
config_file.close()
cmd = 'iverilog -o %s.v -c %s whitebox.v whitebox_reset.v /home/testa/whitebox/hdl/cosim_whitebox.v' % (cosim_name, config_file.name)
os.system(cmd)
fir_coeff_ram_addr = self.fir_coeff_ram.port['a'].addr
fir_coeff_ram_din0 = self.fir_coeff_ram.port['a'].din[0]
fir_coeff_ram_din1 = self.fir_coeff_ram.port['a'].din[1]
fir_coeff_ram_width0 = self.fir_coeff_ram.port['a'].width0
fir_coeff_ram_width1 = self.fir_coeff_ram.port['a'].width1
fir_coeff_ram_pipe = self.fir_coeff_ram.port['a'].pipe
fir_coeff_ram_wmode = self.fir_coeff_ram.port['a'].wmode
fir_coeff_ram_blk = self.fir_coeff_ram.port['a'].blk
fir_coeff_ram_wen = self.fir_coeff_ram.port['a'].wen
fir_coeff_ram_clk = self.fir_coeff_ram.port['a'].clk
fir_coeff_ram_dout0 = self.fir_coeff_ram.port['a'].dout[0]
fir_coeff_ram_dout1 = self.fir_coeff_ram.port['a'].dout[1]
fir_load_coeff_ram_addr = self.fir_coeff_ram.port['b'].addr
fir_load_coeff_ram_din0 = self.fir_coeff_ram.port['b'].din[0]
fir_load_coeff_ram_din1 = self.fir_coeff_ram.port['b'].din[1]
fir_load_coeff_ram_width0 = self.fir_coeff_ram.port['b'].width0
fir_load_coeff_ram_width1 = self.fir_coeff_ram.port['b'].width1
fir_load_coeff_ram_pipe = self.fir_coeff_ram.port['b'].pipe
fir_load_coeff_ram_wmode = self.fir_coeff_ram.port['b'].wmode
fir_load_coeff_ram_blk = self.fir_coeff_ram.port['b'].blk
fir_load_coeff_ram_wen = self.fir_coeff_ram.port['b'].wen
fir_load_coeff_ram_clk = self.fir_coeff_ram.port['b'].clk
fir_load_coeff_ram_dout0 = self.fir_coeff_ram.port['b'].dout[0]
fir_load_coeff_ram_dout1 = self.fir_coeff_ram.port['b'].dout[1]
fir_delay_line_i_ram_addr = self.fir_delay_line_i_ram.port['a'].addr
fir_delay_line_i_ram_din = self.fir_delay_line_i_ram.port['a'].din
fir_delay_line_i_ram_width0 = self.fir_delay_line_i_ram.port['a'].width0
fir_delay_line_i_ram_width1 = self.fir_delay_line_i_ram.port['a'].width1
fir_delay_line_i_ram_pipe = self.fir_delay_line_i_ram.port['a'].pipe
fir_delay_line_i_ram_wmode = self.fir_delay_line_i_ram.port['a'].wmode
fir_delay_line_i_ram_blk = self.fir_delay_line_i_ram.port['a'].blk
fir_delay_line_i_ram_wen = self.fir_delay_line_i_ram.port['a'].wen
fir_delay_line_i_ram_clk = self.fir_delay_line_i_ram.port['a'].clk
fir_delay_line_i_ram_dout = self.fir_delay_line_i_ram.port['a'].dout
fir_delay_line_q_ram_addr = self.fir_delay_line_q_ram.port['a'].addr
fir_delay_line_q_ram_din = self.fir_delay_line_q_ram.port['a'].din
fir_delay_line_q_ram_width0 = self.fir_delay_line_q_ram.port['a'].width0
fir_delay_line_q_ram_width1 = self.fir_delay_line_q_ram.port['a'].width1
fir_delay_line_q_ram_pipe = self.fir_delay_line_q_ram.port['a'].pipe
fir_delay_line_q_ram_wmode = self.fir_delay_line_q_ram.port['a'].wmode
fir_delay_line_q_ram_blk = self.fir_delay_line_q_ram.port['a'].blk
fir_delay_line_q_ram_wen = self.fir_delay_line_q_ram.port['a'].wen
fir_delay_line_q_ram_clk = self.fir_delay_line_q_ram.port['a'].clk
fir_delay_line_q_ram_dout = self.fir_delay_line_q_ram.port['a'].dout
whitebox_test = Cosimulation(
'vvp -m ./myhdl.vpi %s.v' % (cosim_name, ),
resetn=self.bus.presetn,
pclk=self.bus.pclk,
paddr=self.bus.paddr,
psel=self.bus.psel,
penable=self.bus.penable,
pwrite=self.bus.pwrite,
pwdata=self.bus.pwdata,
pready=self.bus.pready,
prdata=self.bus.prdata,
#pslverr=self.bus.pslverr,
clearn=clearn,
clear_enable=self.clear_enable,
dac_clock=self.dac_clock,
dac2x_clock=self.dac2x_clock,
dac_en=self.dac_en,
dac_data=self.dac_data,
adc_idata=self.adc_idata,
adc_qdata=self.adc_qdata,
tx_status_led=self.tx_status_led,
tx_dmaready=self.tx_dmaready,
rx_status_led=self.rx_status_led,
rx_dmaready=self.rx_dmaready,
tx_fifo_re=tx_fifo_re,
tx_fifo_rclk=tx_fifo_rclk,
tx_fifo_rdata=tx_fifo_rdata,
tx_fifo_we=tx_fifo_we,
tx_fifo_wclk=tx_fifo_wclk,
tx_fifo_wdata=tx_fifo_wdata,
tx_fifo_full=tx_fifo_full,
tx_fifo_afull=tx_fifo_afull,
tx_fifo_empty=tx_fifo_empty,
tx_fifo_aempty=tx_fifo_aempty,
tx_fifo_afval=tx_fifo_afval,
tx_fifo_aeval=tx_fifo_aeval,
tx_fifo_wack=tx_fifo_wack,
tx_fifo_dvld=tx_fifo_dvld,
tx_fifo_overflow=tx_fifo_overflow,
tx_fifo_underflow=tx_fifo_underflow,
tx_fifo_rdcnt=tx_fifo_rdcnt,
tx_fifo_wrcnt=tx_fifo_wrcnt,
rx_fifo_re=rx_fifo_re,
rx_fifo_rclk=rx_fifo_rclk,
rx_fifo_rdata=rx_fifo_rdata,
rx_fifo_we=rx_fifo_we,
rx_fifo_wclk=rx_fifo_wclk,
rx_fifo_wdata=rx_fifo_wdata,
rx_fifo_full=rx_fifo_full,
rx_fifo_afull=rx_fifo_afull,
rx_fifo_empty=rx_fifo_empty,
rx_fifo_aempty=rx_fifo_aempty,
rx_fifo_afval=rx_fifo_afval,
rx_fifo_aeval=rx_fifo_aeval,
rx_fifo_wack=rx_fifo_wack,
rx_fifo_dvld=rx_fifo_dvld,
rx_fifo_overflow=rx_fifo_overflow,
rx_fifo_underflow=rx_fifo_underflow,
rx_fifo_rdcnt=rx_fifo_rdcnt,
rx_fifo_wrcnt=rx_fifo_wrcnt,
fir_coeff_ram_addr=fir_coeff_ram_addr,
fir_coeff_ram_din0=fir_coeff_ram_din0,
fir_coeff_ram_din1=fir_coeff_ram_din1,
fir_coeff_ram_width0=fir_coeff_ram_width0,
fir_coeff_ram_width1=fir_coeff_ram_width1,
fir_coeff_ram_pipe=fir_coeff_ram_pipe,
fir_coeff_ram_wmode=fir_coeff_ram_wmode,
fir_coeff_ram_blk=fir_coeff_ram_blk,
fir_coeff_ram_wen=fir_coeff_ram_wen,
fir_coeff_ram_clk=fir_coeff_ram_clk,
fir_coeff_ram_dout0=fir_coeff_ram_dout0,
fir_coeff_ram_dout1=fir_coeff_ram_dout1,
fir_load_coeff_ram_addr=fir_load_coeff_ram_addr,
fir_load_coeff_ram_din0=fir_load_coeff_ram_din0,
fir_load_coeff_ram_din1=fir_load_coeff_ram_din1,
fir_load_coeff_ram_width0=fir_load_coeff_ram_width0,
fir_load_coeff_ram_width1=fir_load_coeff_ram_width1,
fir_load_coeff_ram_pipe=fir_load_coeff_ram_pipe,
fir_load_coeff_ram_wmode=fir_load_coeff_ram_wmode,
fir_load_coeff_ram_blk=fir_load_coeff_ram_blk,
fir_load_coeff_ram_wen=fir_load_coeff_ram_wen,
fir_load_coeff_ram_clk=fir_load_coeff_ram_clk,
fir_load_coeff_ram_dout0=fir_load_coeff_ram_dout0,
fir_load_coeff_ram_dout1=fir_load_coeff_ram_dout1,
fir_delay_line_i_ram_addr=fir_delay_line_i_ram_addr,
fir_delay_line_i_ram_din=fir_delay_line_i_ram_din,
fir_delay_line_i_ram_width0=fir_delay_line_i_ram_width0,
fir_delay_line_i_ram_width1=fir_delay_line_i_ram_width1,
fir_delay_line_i_ram_pipe=fir_delay_line_i_ram_pipe,
fir_delay_line_i_ram_wmode=fir_delay_line_i_ram_wmode,
fir_delay_line_i_ram_blk=fir_delay_line_i_ram_blk,
fir_delay_line_i_ram_wen=fir_delay_line_i_ram_wen,
fir_delay_line_i_ram_clk=fir_delay_line_i_ram_clk,
fir_delay_line_i_ram_dout=fir_delay_line_i_ram_dout,
fir_delay_line_q_ram_addr=fir_delay_line_q_ram_addr,
fir_delay_line_q_ram_din=fir_delay_line_q_ram_din,
fir_delay_line_q_ram_width0=fir_delay_line_q_ram_width0,
fir_delay_line_q_ram_width1=fir_delay_line_q_ram_width1,
fir_delay_line_q_ram_pipe=fir_delay_line_q_ram_pipe,
fir_delay_line_q_ram_wmode=fir_delay_line_q_ram_wmode,
fir_delay_line_q_ram_blk=fir_delay_line_q_ram_blk,
fir_delay_line_q_ram_wen=fir_delay_line_q_ram_wen,
fir_delay_line_q_ram_clk=fir_delay_line_q_ram_clk,
fir_delay_line_q_ram_dout=fir_delay_line_q_ram_dout,
)
return tx_fifo, rx_fifo, self.fir_coeff_ram.rama, self.fir_coeff_ram.ramb, self.fir_delay_line_i_ram.ram, self.fir_delay_line_q_ram.ram, whitebox_test
def cosim_dut(self, cosim_name, fifo_args, whitebox_args):
"""Get the ``Cosimulation`` object.
:param cosim_name: The name of the cosimulation.
:param fifo_args: A dictionary of args to pass to the FIFOs.
:param whitebox_args: A dictionary of args to pass to the Whitebox Peripheral.
:returns: A `myhdl.Cosimulation` object.
"""
bus_pclk = self.bus.pclk
bus_paddr = self.bus.paddr
bus_psel = self.bus.psel
bus_penable = self.bus.penable
bus_pwrite = self.bus.pwrite
bus_pwdata = self.bus.pwdata
bus_pslverr = self.bus.pslverr
bus_pready = self.bus.pready
bus_prdata = self.bus.prdata
clearn = ResetSignal(0, 0, async=True)
fifo_depth = fifo_args['depth']
tx_fifo_re = Signal(bool(False))
tx_fifo_rclk = self.dac_clock
tx_fifo_rdata = Signal(intbv(0)[32:])
tx_fifo_we = Signal(bool(False))
tx_fifo_wclk = self.bus.pclk
tx_fifo_wdata = Signal(intbv(0)[32:])
tx_fifo_full = Signal(bool(False))
tx_fifo_afull = Signal(bool(False))
tx_fifo_empty = Signal(bool(True))
tx_fifo_aempty = Signal(bool(True))
tx_fifo_afval = Signal(intbv(fifo_depth - 1)[10:])
tx_fifo_aeval = Signal(intbv(0)[10:])
tx_fifo_wack = Signal(bool(False))
tx_fifo_dvld = Signal(bool(False))
tx_fifo_overflow = Signal(bool(False))
tx_fifo_underflow = Signal(bool(False))
tx_fifo_rdcnt = Signal(intbv(0, min=0, max=fifo_depth + 1))
tx_fifo_wrcnt = Signal(intbv(fifo_depth, min=0, max=fifo_depth + 1))
tx_fifo_signals = (clearn, tx_fifo_re, tx_fifo_rclk, tx_fifo_rdata,
tx_fifo_we, tx_fifo_wclk, tx_fifo_wdata,
tx_fifo_full, tx_fifo_afull, tx_fifo_empty,
tx_fifo_aempty, tx_fifo_afval, tx_fifo_aeval,
tx_fifo_wack, tx_fifo_dvld, tx_fifo_overflow,
tx_fifo_underflow, tx_fifo_rdcnt, tx_fifo_wrcnt)
tx_fifo = fifo(*tx_fifo_signals, **fifo_args)
rx_fifo_depth = fifo_args['depth']
rx_fifo_re = Signal(bool(False))
rx_fifo_rclk = self.bus.pclk
rx_fifo_rdata = Signal(intbv(0)[32:])
rx_fifo_we = Signal(bool(False))
rx_fifo_wclk = self.dac_clock
rx_fifo_wdata = Signal(intbv(0)[32:])
rx_fifo_full = Signal(bool(False))
rx_fifo_afull = Signal(bool(False))
rx_fifo_empty = Signal(bool(True))
rx_fifo_aempty = Signal(bool(True))
rx_fifo_afval = Signal(intbv(fifo_depth - 1)[10:])
rx_fifo_aeval = Signal(intbv(0)[10:])
rx_fifo_wack = Signal(bool(False))
rx_fifo_dvld = Signal(bool(False))
rx_fifo_overflow = Signal(bool(False))
rx_fifo_underflow = Signal(bool(False))
rx_fifo_rdcnt = Signal(intbv(0, min=0, max=fifo_depth + 1))
rx_fifo_wrcnt = Signal(intbv(fifo_depth, min=0, max=fifo_depth + 1))
rx_fifo_signals = (clearn, rx_fifo_re, rx_fifo_rclk, rx_fifo_rdata,
rx_fifo_we, rx_fifo_wclk, rx_fifo_wdata,
rx_fifo_full, rx_fifo_afull, rx_fifo_empty,
rx_fifo_aempty, rx_fifo_afval, rx_fifo_aeval,
rx_fifo_wack, rx_fifo_dvld, rx_fifo_overflow,
rx_fifo_underflow, rx_fifo_rdcnt, rx_fifo_wrcnt)
rx_fifo = fifo(*rx_fifo_signals, **fifo_args)
config_file = tempfile.NamedTemporaryFile(delete=False)
config_file.write('+define+COSIM_NAME="%s"' % (cosim_name, ))
config_file.close()
cmd = 'iverilog -o %s.v -c %s whitebox.v whitebox_reset.v /home/testa/whitebox/hdl/cosim_whitebox.v' % (
cosim_name, config_file.name)
os.system(cmd)
fir_coeff_ram_addr = self.fir_coeff_ram.port['a'].addr
fir_coeff_ram_din0 = self.fir_coeff_ram.port['a'].din[0]
fir_coeff_ram_din1 = self.fir_coeff_ram.port['a'].din[1]
fir_coeff_ram_width0 = self.fir_coeff_ram.port['a'].width0
fir_coeff_ram_width1 = self.fir_coeff_ram.port['a'].width1
fir_coeff_ram_pipe = self.fir_coeff_ram.port['a'].pipe
fir_coeff_ram_wmode = self.fir_coeff_ram.port['a'].wmode
fir_coeff_ram_blk = self.fir_coeff_ram.port['a'].blk
fir_coeff_ram_wen = self.fir_coeff_ram.port['a'].wen
fir_coeff_ram_clk = self.fir_coeff_ram.port['a'].clk
fir_coeff_ram_dout0 = self.fir_coeff_ram.port['a'].dout[0]
fir_coeff_ram_dout1 = self.fir_coeff_ram.port['a'].dout[1]
fir_load_coeff_ram_addr = self.fir_coeff_ram.port['b'].addr
fir_load_coeff_ram_din0 = self.fir_coeff_ram.port['b'].din[0]
fir_load_coeff_ram_din1 = self.fir_coeff_ram.port['b'].din[1]
fir_load_coeff_ram_width0 = self.fir_coeff_ram.port['b'].width0
fir_load_coeff_ram_width1 = self.fir_coeff_ram.port['b'].width1
fir_load_coeff_ram_pipe = self.fir_coeff_ram.port['b'].pipe
fir_load_coeff_ram_wmode = self.fir_coeff_ram.port['b'].wmode
fir_load_coeff_ram_blk = self.fir_coeff_ram.port['b'].blk
fir_load_coeff_ram_wen = self.fir_coeff_ram.port['b'].wen
fir_load_coeff_ram_clk = self.fir_coeff_ram.port['b'].clk
fir_load_coeff_ram_dout0 = self.fir_coeff_ram.port['b'].dout[0]
fir_load_coeff_ram_dout1 = self.fir_coeff_ram.port['b'].dout[1]
fir_delay_line_i_ram_addr = self.fir_delay_line_i_ram.port['a'].addr
fir_delay_line_i_ram_din = self.fir_delay_line_i_ram.port['a'].din
fir_delay_line_i_ram_width0 = self.fir_delay_line_i_ram.port[
'a'].width0
fir_delay_line_i_ram_width1 = self.fir_delay_line_i_ram.port[
'a'].width1
fir_delay_line_i_ram_pipe = self.fir_delay_line_i_ram.port['a'].pipe
fir_delay_line_i_ram_wmode = self.fir_delay_line_i_ram.port['a'].wmode
fir_delay_line_i_ram_blk = self.fir_delay_line_i_ram.port['a'].blk
fir_delay_line_i_ram_wen = self.fir_delay_line_i_ram.port['a'].wen
fir_delay_line_i_ram_clk = self.fir_delay_line_i_ram.port['a'].clk
fir_delay_line_i_ram_dout = self.fir_delay_line_i_ram.port['a'].dout
fir_delay_line_q_ram_addr = self.fir_delay_line_q_ram.port['a'].addr
fir_delay_line_q_ram_din = self.fir_delay_line_q_ram.port['a'].din
fir_delay_line_q_ram_width0 = self.fir_delay_line_q_ram.port[
'a'].width0
fir_delay_line_q_ram_width1 = self.fir_delay_line_q_ram.port[
'a'].width1
fir_delay_line_q_ram_pipe = self.fir_delay_line_q_ram.port['a'].pipe
fir_delay_line_q_ram_wmode = self.fir_delay_line_q_ram.port['a'].wmode
fir_delay_line_q_ram_blk = self.fir_delay_line_q_ram.port['a'].blk
fir_delay_line_q_ram_wen = self.fir_delay_line_q_ram.port['a'].wen
fir_delay_line_q_ram_clk = self.fir_delay_line_q_ram.port['a'].clk
fir_delay_line_q_ram_dout = self.fir_delay_line_q_ram.port['a'].dout
whitebox_test = Cosimulation(
'vvp -m ./myhdl.vpi %s.v' % (cosim_name, ),
resetn=self.bus.presetn,
pclk=self.bus.pclk,
paddr=self.bus.paddr,
psel=self.bus.psel,
penable=self.bus.penable,
pwrite=self.bus.pwrite,
pwdata=self.bus.pwdata,
pready=self.bus.pready,
prdata=self.bus.prdata,
#pslverr=self.bus.pslverr,
clearn=clearn,
clear_enable=self.clear_enable,
dac_clock=self.dac_clock,
dac2x_clock=self.dac2x_clock,
dac_en=self.dac_en,
dac_data=self.dac_data,
adc_idata=self.adc_idata,
adc_qdata=self.adc_qdata,
tx_status_led=self.tx_status_led,
tx_dmaready=self.tx_dmaready,
rx_status_led=self.rx_status_led,
rx_dmaready=self.rx_dmaready,
tx_fifo_re=tx_fifo_re,
tx_fifo_rclk=tx_fifo_rclk,
tx_fifo_rdata=tx_fifo_rdata,
tx_fifo_we=tx_fifo_we,
tx_fifo_wclk=tx_fifo_wclk,
tx_fifo_wdata=tx_fifo_wdata,
tx_fifo_full=tx_fifo_full,
tx_fifo_afull=tx_fifo_afull,
tx_fifo_empty=tx_fifo_empty,
tx_fifo_aempty=tx_fifo_aempty,
tx_fifo_afval=tx_fifo_afval,
tx_fifo_aeval=tx_fifo_aeval,
tx_fifo_wack=tx_fifo_wack,
tx_fifo_dvld=tx_fifo_dvld,
tx_fifo_overflow=tx_fifo_overflow,
tx_fifo_underflow=tx_fifo_underflow,
tx_fifo_rdcnt=tx_fifo_rdcnt,
tx_fifo_wrcnt=tx_fifo_wrcnt,
rx_fifo_re=rx_fifo_re,
rx_fifo_rclk=rx_fifo_rclk,
rx_fifo_rdata=rx_fifo_rdata,
rx_fifo_we=rx_fifo_we,
rx_fifo_wclk=rx_fifo_wclk,
rx_fifo_wdata=rx_fifo_wdata,
rx_fifo_full=rx_fifo_full,
rx_fifo_afull=rx_fifo_afull,
rx_fifo_empty=rx_fifo_empty,
rx_fifo_aempty=rx_fifo_aempty,
rx_fifo_afval=rx_fifo_afval,
rx_fifo_aeval=rx_fifo_aeval,
rx_fifo_wack=rx_fifo_wack,
rx_fifo_dvld=rx_fifo_dvld,
rx_fifo_overflow=rx_fifo_overflow,
rx_fifo_underflow=rx_fifo_underflow,
rx_fifo_rdcnt=rx_fifo_rdcnt,
rx_fifo_wrcnt=rx_fifo_wrcnt,
fir_coeff_ram_addr=fir_coeff_ram_addr,
fir_coeff_ram_din0=fir_coeff_ram_din0,
fir_coeff_ram_din1=fir_coeff_ram_din1,
fir_coeff_ram_width0=fir_coeff_ram_width0,
fir_coeff_ram_width1=fir_coeff_ram_width1,
fir_coeff_ram_pipe=fir_coeff_ram_pipe,
fir_coeff_ram_wmode=fir_coeff_ram_wmode,
fir_coeff_ram_blk=fir_coeff_ram_blk,
fir_coeff_ram_wen=fir_coeff_ram_wen,
fir_coeff_ram_clk=fir_coeff_ram_clk,
fir_coeff_ram_dout0=fir_coeff_ram_dout0,
fir_coeff_ram_dout1=fir_coeff_ram_dout1,
fir_load_coeff_ram_addr=fir_load_coeff_ram_addr,
fir_load_coeff_ram_din0=fir_load_coeff_ram_din0,
fir_load_coeff_ram_din1=fir_load_coeff_ram_din1,
fir_load_coeff_ram_width0=fir_load_coeff_ram_width0,
fir_load_coeff_ram_width1=fir_load_coeff_ram_width1,
fir_load_coeff_ram_pipe=fir_load_coeff_ram_pipe,
fir_load_coeff_ram_wmode=fir_load_coeff_ram_wmode,
fir_load_coeff_ram_blk=fir_load_coeff_ram_blk,
fir_load_coeff_ram_wen=fir_load_coeff_ram_wen,
fir_load_coeff_ram_clk=fir_load_coeff_ram_clk,
fir_load_coeff_ram_dout0=fir_load_coeff_ram_dout0,
fir_load_coeff_ram_dout1=fir_load_coeff_ram_dout1,
fir_delay_line_i_ram_addr=fir_delay_line_i_ram_addr,
fir_delay_line_i_ram_din=fir_delay_line_i_ram_din,
fir_delay_line_i_ram_width0=fir_delay_line_i_ram_width0,
fir_delay_line_i_ram_width1=fir_delay_line_i_ram_width1,
fir_delay_line_i_ram_pipe=fir_delay_line_i_ram_pipe,
fir_delay_line_i_ram_wmode=fir_delay_line_i_ram_wmode,
fir_delay_line_i_ram_blk=fir_delay_line_i_ram_blk,
fir_delay_line_i_ram_wen=fir_delay_line_i_ram_wen,
fir_delay_line_i_ram_clk=fir_delay_line_i_ram_clk,
fir_delay_line_i_ram_dout=fir_delay_line_i_ram_dout,
fir_delay_line_q_ram_addr=fir_delay_line_q_ram_addr,
fir_delay_line_q_ram_din=fir_delay_line_q_ram_din,
fir_delay_line_q_ram_width0=fir_delay_line_q_ram_width0,
fir_delay_line_q_ram_width1=fir_delay_line_q_ram_width1,
fir_delay_line_q_ram_pipe=fir_delay_line_q_ram_pipe,
fir_delay_line_q_ram_wmode=fir_delay_line_q_ram_wmode,
fir_delay_line_q_ram_blk=fir_delay_line_q_ram_blk,
fir_delay_line_q_ram_wen=fir_delay_line_q_ram_wen,
fir_delay_line_q_ram_clk=fir_delay_line_q_ram_clk,
fir_delay_line_q_ram_dout=fir_delay_line_q_ram_dout,
)
return tx_fifo, rx_fifo, self.fir_coeff_ram.rama, self.fir_coeff_ram.ramb, self.fir_delay_line_i_ram.ram, self.fir_delay_line_q_ram.ram, whitebox_test
def __init__(self):
self.mon = threading.RLock()
self.cv = threading.Condition(self.mon)
self.queue = fifo.fifo()
# -*- coding: utf-8 -*-
"""
@Author: Xingqi Tang
@Created: 2018/5/16 18:50
@Name: page_replacement
@Project: neu_curriculum
"""
import fifo
import lru
import rand_page
series_size = 20
random_size = 7
if __name__ == "__main__":
access_series = rand_page.random_list(0, random_size, series_size)
fifo.fifo(3, access_series)
lru.lru(access_series)
def testbench(state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x, z,
xfifo, zfifo, flgs_i, update_i, res_o, update_o, end_of_col,
empty_r, full_r, enr_r, enw_r, dataout_r, datain_r, empty_ro,
full_ro, enr_ro, enw_ro, dataout_ro, datain_ro, addr_in,
del_ctn):
instance_Odd_Even_Fsm = Odd_Even_Fsm(state, clk, rst_fsm, addr_left,
muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i,
right_i, do_first, x, z, flgs_i,
update_i, res_o, update_o, end_of_col,
addr_in, xfifo, enr_r, enw_r, del_ctn)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr,
addr_in, muxsel_i, muxaddrsel, addr_left,
addr_sam, addr_rht, zfifo)
instance_signed2twoscomplement = signed2twoscomplement(clk, x, z)
instance_signed2twoscomplementfifo = signed2twoscomplement(
clk, xfifo, zfifo)
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i,
clk, res_o, update_o)
instance_pc_in = fifo(clk, empty_r, full_r, enr_r, enw_r, dataout_r,
datain_r)
instance_pc_out = fifo(clk, empty_ro, full_ro, enr_ro, enw_ro, dataout_ro,
datain_ro)
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
rst_fsm.next = 0
yield clk.posedge
muxsel_i.next = 0
yield clk.posedge
enr_r.next = 0
yield clk.posedge
enw_r.next = 0
yield clk.posedge
datain_r.next = m[0][0]
yield clk.posedge
enw_r.next = 1
yield clk.posedge
for j in range(1, 255):
k = 0
if (full_r == 0):
datain_r.next = m[j][k]
yield clk.posedge
#print ("%d %d %d %d %d") % (now(), j, enw_r, full_r, m[j][k])
enw_r.next = 0
yield clk.posedge
muxsel_i.next = 0
yield clk.posedge
rst_fsm.next = 1
yield clk.posedge
print("%d muxsel_i %d rst_fsm %d") % (now(), muxsel_i, rst_fsm)
while (end_of_col == 0):
print("time %d flgs %d left %d sam %d right %d ") % (
now(), flgs_i, left_i, sam_i, right_i)
print("time %d addr %d din %d we %d ") % (now(), addr, din, we)
yield clk.posedge
print("%d ") % (now())
print "end of col"
muxsel_i.next = 1
yield clk.posedge
rst_fsm.next = 0
yield clk.posedge
addr_in.next = 0
yield clk.posedge
we_in.next = 0
m[0][k] = dout
datain_ro.next = m[0][k]
yield clk.posedge
print("%d data to ram %d %d") % (now(), datain_ro, addr_in)
addr_in.next = addr_in + 1
yield clk.posedge
enw_ro.next = 1
yield clk.posedge
for j in range(1, 254):
m[0][k] = dout
datain_ro.next = m[j][k]
yield clk.posedge
addr_in.next = addr_in + 1
print("%d data to ram %d %d") % (now(), datain_ro, addr_in)
yield clk.posedge
enw_ro.next = 1
yield clk.posedge
raise StopSimulation
return instances()
