def test_end2end_cnv_w1a1_fold_and_tlastmarker():
model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_dataflow_model.onnx")
fc_layers = model.get_nodes_by_op_type("StreamingFCLayer_Batch")
# each tuple is (PE, SIMD, in_fifo_depth) for a layer
folding = [
(16, 3, 128),
(32, 32, 128),
(16, 32, 128),
(16, 32, 128),
(4, 32, 81),
(1, 32, 2),
(1, 4, 2),
(1, 8, 128),
(5, 1, 3),
]
for fcl, (pe, simd, ififodepth) in zip(fc_layers, folding):
fcl_inst = getCustomOp(fcl)
fcl_inst.set_nodeattr("PE", pe)
fcl_inst.set_nodeattr("SIMD", simd)
fcl_inst.set_nodeattr("inFIFODepth", ififodepth)
swg_layers = model.get_nodes_by_op_type("ConvolutionInputGenerator")
for i in range(len(swg_layers)):
swg_inst = getCustomOp(swg_layers[i])
simd = folding[i][1]
swg_inst.set_nodeattr("SIMD", simd)
model = model.transform(InsertDWC())
model = model.transform(InsertFIFO())
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(AnnotateResources("estimate"))
model.save(build_dir + "/end2end_cnv_w1a1_folded.onnx")
def test_end2end_mobilenet_build():
model = load_test_checkpoint_or_skip(build_dir +
"/end2end_mobilenet_fifodepth.onnx")
model = model.transform(
VitisBuild(
test_fpga_part,
target_clk_ns,
test_platform,
strategy=VitisOptStrategy.PERFORMANCE_BEST,
))
model.save(build_dir + "/end2end_mobilenet_build.onnx")
model = model.transform(AnnotateResources("synth"))
model.save(build_dir + "/end2end_mobilenet_final.onnx")
def test_build(self, topology, wbits, abits, kind):
if kind == "alveo" and ("VITIS_PATH" not in os.environ):
pytest.skip("VITIS_PATH not set")
prev_chkpt_name = get_checkpoint_name(topology, wbits, abits, "ipgen_" + kind)
model = load_test_checkpoint_or_skip(prev_chkpt_name)
cfg = get_build_env(kind, target_clk_ns)
model = model.transform(cfg["build_fxn"])
model = model.transform(AnnotateResources("synth"))
synth_dct = eval(model.get_metadata_prop("res_total_top_synth"))
for (k, v) in synth_dct.items():
update_dashboard_data(topology, wbits, abits, k, v)
update_dashboard_data(topology, wbits, abits, "board", cfg["board"])
model.save(get_checkpoint_name(topology, wbits, abits, "build_" + kind))
def test_end2end_mobilenet_gen_hls_ip():
model = load_test_checkpoint_or_skip(
build_dir + "/end2end_mobilenet_dataflow_model.onnx")
start = time.time()
model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
model = model.transform(HLSSynthIP())
model = model.transform(ReplaceVerilogRelPaths())
end = time.time()
elapsed_time = end - start
f = open(build_dir + "/end2end_mobilenet_ipgen_time.txt", "w+")
f.write("Execution time in seconds: " + str(elapsed_time))
f.close()
model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_mobilenet_ipgen.onnx")
def test_end2end_tfc_w1a2_fold_and_tlastmarker():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_dataflow_model.onnx")
fc_layers = model.get_nodes_by_op_type("StreamingFCLayer_Batch")
# (PE, SIMD, in_fifo_depth, out_fifo_depth, ramstyle) for each layer
config = [
(16, 49, 16, 64, "block"),
(8, 8, 64, 64, "auto"),
(8, 8, 64, 64, "auto"),
(10, 8, 64, 10, "distributed"),
]
for fcl, (pe, simd, ififo, ofifo, ramstyle) in zip(fc_layers, config):
fcl_inst = getCustomOp(fcl)
fcl_inst.set_nodeattr("PE", pe)
fcl_inst.set_nodeattr("SIMD", simd)
fcl_inst.set_nodeattr("inFIFODepth", ififo)
fcl_inst.set_nodeattr("outFIFODepth", ofifo)
fcl_inst.set_nodeattr("ram_style", ramstyle)
model = model.transform(InsertDWC())
model = model.transform(InsertFIFO())
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(AnnotateResources("estimate"))
model.save(build_dir + "/end2end_tfc_w1a2_folded.onnx")
def test_end2end_tfc_w1a2_synth_pynq_project():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_pynq_project.onnx")
model = model.transform(SynthPYNQProject())
model = model.transform(AnnotateResources("synth"))
model.save(build_dir + "/end2end_tfc_w1a2_synth.onnx")
def test_end2end_tfc_w1a2_gen_hls_ip():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_folded.onnx")
model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
model = model.transform(HLSSynthIP())
model = model.transform(AnnotateResources("hls"))
model.save(build_dir + "/end2end_tfc_w1a2_ipgen.onnx")