def open_device(self): ivp = self.initial_vidpid vp = self.fpgalink_vidpid print("Attempting to open connection to FPGALink device", vp, "...") try: handle = fl.flOpen(self.fpgalink_vidpid) except fl.FLException as ex: if not ivp: raise FLException( "Could not open FPGALink device at {0} and" " no initial VID:PID was supplied".format(vp)) print("Loading firmware into %s..." % ivp) fl.flLoadStandardFirmware(ivp, vp) print("Awaiting renumeration...") if not fl.flAwaitDevice(vp, 600): raise fl.FLException( "FPGALink device did not renumerate properly" " as {0}".format(vp)) print("Attempting to open connection to FPGALink device", vp, "again...") handle = fl.flOpen(vp) # Only Nero capable hardware support doing programming. assert fl.flIsNeroCapable(handle) print("Cable connection opened.") return handle
def ids(vp, argList): """ Handles opening connection to FPGA board when flOpen fails initially. Also loads standard firmware using device id Args: vp(): vendor ID and product ID argList(namespace): populated namespace object Returns: An opaque reference to an internal structure representing the connection. This must be freed at some later time by a call to \c flClose(), or a resource-leak will ensue. """ if argList.i: ivp = argList.i[0] print("Loading firmware into {}...".format(ivp)) fl.flLoadStandardFirmware(ivp, vp) # Long delay for renumeration # TODO: fix this hack. The timeout value specified in flAwaitDevice() below doesn't seem to work time.sleep(3) print("Awaiting renumeration...") if ( not fl.flAwaitDevice(vp, 10000) ): raise fl.FLException("FPGALink device did not renumerate properly as {}".format(vp)) print("Attempting to open connection to FPGALink device {} again...".format(vp)) return fl.flOpen(vp) else: raise fl.FLException("Could not open FPGALink device at {} and no initial VID:PID was supplied".format(vp))
def __init__(self): FPGABusBase.__init__(self) import fl fl.flInitialise(0) self.handle = fl.flOpen(options.USB_DEVICE_ID) fl.flSelectConduit(self.handle, 1)
def openComm(config): argList = getArgs() handle = fl.FLHandle() try: fpga_vid_pid_did = argList['fpga_vid_pid_did'] try: handle = fl.flOpen(fpga_vid_pid_did) except fl.FLException as ex: fpga_vid_pid = argList['fpga_vid_pid'] fl.flLoadStandardFirmware(fpga_vid_pid, fpga_vid_pid_did) #might need to add delay here if not fl.flAwaitDevice(fpga_vid_pid, 10000): raise fl.FLException('FPGALink device did not renumerate properly') handle = fl.flOpen(fpga_vid_pid_did) isNeroCapable = fl.flIsNeroCapable(handle) isCommCapable = fl.flIsCommCapable(handle, 1) fl.flSelectConduit(handle, 1) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) return (fpga, handle, Optimizer(handle, fpga, config)) else: return None #open comm failed
def ids(vp, argList): if argList.i: ivp = argList.i[0] print("Loading firmware into {}...".format(ivp)) fl.flLoadStandardFirmware(ivp, vp) # Long delay for renumeration # TODO: fix this hack. The timeout value specified in flAwaitDevice() below doesn't seem to work time.sleep(3) print("Awaiting renumeration...") if ( not fl.flAwaitDevice(vp, 10000) ): raise fl.FLException("FPGALink device did not renumerate properly as {}".format(vp)) print("Attempting to open connection to FPGALink device {} again...".format(vp)) return fl.flOpen(vp) else: raise fl.FLException("Could not open FPGALink device at {} and no initial VID:PID was supplied".format(vp))
def initComTest(self): """ Test intial connection capabilities to FPGA board over USB. Returns: results(list): list of strings representing reports of passed and failed tests. """ results = [] fl.flInitialise(self.debug_level) #initializes library if fl.flIsDeviceAvailable(self.vid_pid_did): #checks if fpga is available results.append('P','USB bus with: ', self.vid_pid_did,' was found.') try: handle = fl.flOpen(self.vid_pid_did) #opens connection to FPGA board results.append('P','Successfully opened connection to FPGA board.') if fl.flIsNeroCapable(handle): #checks if device is Nero capable results.append('P', 'Device is Nero capable.') else: results.append('F', 'Device is not Nero capable.') if fl.flIsCommCapable(handle, self.conduit): #checks if FPGA board is capable of communication results.append('P','FPGA board supports functions: flIsFPGARunning(), flReadChannel(), flWriteChannel(), flSetAsyncWriteChunkSize(), flWriteChannelAsync(), flFlushAsyncWrites(), \c flAwaitAsyncWrites(), \c flReadChannelAsyncSubmit(),flReadChannelAsyncAwait().') try: fl.flSelectConduit(handle, self.conduit) #selects given conduit results.append('P','Selected conduit ', self.conduit) if fl.flIsFPGARunning(handle): #checks if board is ready to acccept commands results.append('P','FPGA board is ready to accept commands.') except: results.append('F','Conduit was out of range or device did not respond.') else: results.append('F','FPGA board cannot communicate.') fl.flClose(handle) #closes connection to FPGA board to avoid errors results.append('P','Connection to the FPGA board was closed.') except: results.append('F','Connection to FPGA board failed.') else: results.append('F','The VID:PID:DID ', self.vid_pid_did,' is invalid or no USB buses were found.') return results
def main(): argList = get_args() print (argList) handle = fl.FLHandle() try: fl.flInitialise(0) vp = argList.v[0] print("Attempting to open connection to FPGALink device {}...".format(vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: handle = ids(vp, argList) # if ( argList.d ): # print("Configuring ports...") # rb = "{:0{}b}".format(fl.flMultiBitPortAccess(handle, argList.d[0]), 32) # print("Readback: 28 24 20 16 12 8 4 0\n {} {} {} {} {} {} {} {}".format( # rb[0:4], rb[4:8], rb[8:12], rb[12:16], rb[16:20], rb[20:24], rb[24:28], rb[28:32])) # fl.flSleep(100) if argList.c: isNeroCapable, isCommCapable = conduit_selection(int(argList.c[0])) else: isNeroCapable, isCommCapable = conduit_selection() jtag_chain(isNeroCapable, argList, vp, handle) configure(argList, isNeroCapable, handle, vp) if argList.f and not isCommCapable: raise fl.FLException("Data file load requested but device at {} does not support CommFPGA".format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) # define channels writechannel = 0x02 statuschannel = 0x05 resetchannel = 0x08 if argList.ppm: M = int(eval(argList.ppm[0])) print ("Setting PPM order to",M) fpga.setPPM_M(M) writedelay,num_bytes,trackingbyte = fpga.setModulatorParams(M) if not argList.f: fpga.setTrackingMode(writechannel,trackingbyte,M) if argList.txdel: delay = int(eval(argList.txdel[0])) print ("Setting transmitter loopback delay to %i (0x%X)"%(delay,delay)) fpga.setTXdelay(delay) if argList.dac: dacval = int(eval(argList.dac[0])) print ("Setting DAC value to %i (0x%X)"%(dacval,dacval)) fpga.writeDAC(dacval) if argList.prbs: # dacval = int(eval(argList.dac[0])) # print ("Setting DAC value to %i (0x%X)"%(dacval,dacval)) print ("Enabling PRBS") fpga.usePRBS() else: print ("Disabling PRBS") fpga.usePRBS(False) if argList.peak: obslength = float(argList.peak) print ("Measuring peak power...") peakDAC = fpga.binSearchPeak(M,target=1.0/M,obslength=obslength) print (" DAC = %i"%peakDAC) if argList.ser: obslength = float(argList.ser) print ("Measuring slot error rate...") cycles,errors,ones,ser = fpga.measureSER(obslength=obslength) print (" cycles = 0x%-12X"%(cycles)) print (" errors = 0x%-12X"%(errors)) print (" ones = 0x%-12X target=0x%-12X"%(ones,cycles/M)) print (" SlotER = %e"%(ser)) data_to_write(argList, fpga, writechannel, resetchannel, statuschannel, writedelay, vp, M, num_bytes) except fl.FLException as ex: print(ex) finally: fl.flClose(handle)
def NODECTRLmain(): argList = get_args() handle = fl.FLHandle() try: fl.flInitialise(0) vp = argList.v[0] print("Attempting to open connection to FPGALink device {}...".format(vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: handle = ids(vp, argList) if argList.c: isNeroCapable, isCommCapable = conduit_selection(int(argList.c[0])) else: isNeroCapable, isCommCapable = conduit_selection() jtag_chain(isNeroCapable, argList, vp, handle) configure(argList, isNeroCapable, handle, vp) if argList.f and not isCommCapable: raise fl.FLException("Data file load requested but device at {} does not support CommFPGA".format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) # define channels ##must update these channels writechannel = 0x02 statuschannel = 0x05 resetchannel = 0x08 writedelay,num_bytes,trackingbyte = fpga.setModulatorParams(M) if argList.ppm: M = int(eval(argList.ppm[0])) print ("Setting PPM order to: ",M) fpga.setPPM_M(M) if not argList.f: fpga.setTrackingMode(writechannel,trackingbyte,M) if argList.txdel: delay = int(eval(argList.txdel[0])) print ("Setting transmitter loopback delay to %i (0x%X)"%(delay,delay)) fpga.setTXdelay(delay) if argList.dac: dacval = int(eval(argList.dac[0])) print ("Setting DAC value to %i (0x%X)"%(dacval,dacval)) fpga.writeDAC(dacval) if argList.prbs: print ("Enabling PRBS") fpga.usePRBS() else: print ("Disabling PRBS") fpga.usePRBS(False) if argList.peak: obslength = float(argList.peak) print ("Measuring peak power...") peakDAC = fpga.binSearchPeak(M,target=1.0/M,obslength=obslength) print (" DAC = %i"%peakDAC) if argList.ser: obslength = float(argList.ser) print ("Measuring slot error rate...") cycles,errors,ones,ser = fpga.measureSER(obslength=obslength) print (" cycles = 0x%-12X"%(cycles)) print (" errors = 0x%-12X"%(errors)) print (" ones = 0x%-12X target=0x%-12X"%(ones,cycles/M)) print (" SlotER = %e"%(ser)) data_to_write(argList, fpga, writechannel, resetchannel, statuschannel, writedelay, vp, M, num_bytes) #alg testing goes here, but alg is not up to date!! #opt_alg(argList, fpga) except fl.FLException as ex: print(ex) finally: fl.flClose(handle)
def SPImain(): argList = get_args() handle = fl.FLHandle() try: fl.flInitialise(0) vp = argList.v[0] print("Attempting to open connection to FPGALink device {}...".format(vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: if argList.i: ivp = argList.i[0] print("Loading firmware into {}...".format(ivp)) fl.flLoadStandardFirmware(ivp, vp) mem_map = tester(ivp, vp) # Long delay for renumeration # TODO: fix this hack. The timeout value specified in flAwaitDevice() below doesn't seem to work time.sleep(3) print("Awaiting renumeration...") if not fl.flAwaitDevice(vp, 10000): raise fl.FLException("FPGALink device did not renumerate properly as {}".format(vp)) print("Attempting to open connection to FPGALink device {} again...".format(vp)) handle = fl.flOpen(vp) else: raise fl.FLException("Could not open FPGALink device at {} and no initial VID:PID was supplied".format(vp)) # if ( argList.d ): # print("Configuring ports...") # rb = "{:0{}b}".format(fl.flMultiBitPortAccess(handle, argList.d[0]), 32) # print("Readback: 28 24 20 16 12 8 4 0\n {} {} {} {} {} {} {} {}".format( # rb[0:4], rb[4:8], rb[8:12], rb[12:16], rb[16:20], rb[20:24], rb[24:28], rb[28:32])) # fl.flSleep(100) conduit = 1 if argList.c: conduit = int(argList.c[0]) isNeroCapable = fl.flIsNeroCapable(handle) isCommCapable = fl.flIsCommCapable(handle, conduit) fl.flSelectConduit(handle, conduit) if argList.f and not(isCommCapable): raise fl.FLException("Data file load requested but device at {} does not support CommFPGA".format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) opt = Optimizer(handle, fpga) #Test setting LD Bias to 0.150A (channels 26, 27) #opt.setCurrent(0.150) #this section of code looks like setLaserCurrent() curr = 0.150 code = curr/(4.096*1.1*((1/6.81)+(1/16500)))*4096 first_byte, second_byte = opt.code2bytes(code) spi_data = [first_byte, second_byte] update_SPI(handle, [26,27], spi_data) #Test reading LD Bias (channels 64 and 65) rx_bias = read_SPI(handle, [mem_map.getAddress('CC3a'), mem_map.getAddress('CC3b')]) for r in rx_bias: print "Bias bytes read: ", r print (rx_bias[1]*256 + rx_bias[0])/4096 * (4.096*1.1*((1/6.81)+(1/16500))) #Test writing/reading to LD Temp #TODO Constants are estimated; may need to verify with vendor R_known = 10000 Vcc = 0.8 B = 3900 R_0 = 10000 T_0 = 25 #writing temp 35C T = 35 V_set = Vcc/(((m.exp(B/T)*(R_0 * m.exp(-B/T_0)))/R_known)+1) V_code = opt.voltage2code(V_set) #convert voltage to code fb, sb = opt.code2byte(V_code) #convert code to bytes update_SPI(handle, [mem_map.getAddress('LTSa'),mem_map.getAddress('LTSb')], [fb, sb]) #reading temp bytes__meas = read_SPI(handle, [mem_map.getAddress('LTMa'),mem_map.getAddress('LTMb')]) #read ADC value code_meas = bytes_meas[1]*256 + bytes_meas[0] #convert bytes to double V_meas = opt.code2voltage(code_meas) #convert ADC to voltage
import fl fl.flInitialise(0) handle = fl.flOpen("1D50:602B:0002") fl.flSelectConduit(handle,1) def read(a,b): return fl.flReadChannel(handle,a,b) def write(a,b): fl.flWriteChannel(handle,a,b) def aread(a,b): fl.flReadChannelAsyncSubmit(handle,a,b) return fl.flReadChannelAsyncAwait(handle) def awrite(a,b): fl.flWriteChannel(handle,a,b)
VID_PID = "1d50:602b:0002" PROG_CONFIG = "D0D2D3D4" CONDUIT = 1 BYTE_ARRAY = b"\xCA\xFE\xBA\xBE" conn = fl.FLHandle() try: fl.flInitialise(0) if ( not fl.flIsDeviceAvailable(VID_PID) ): print("Loading firmware...") fl.flLoadStandardFirmware("04b4:8613", VID_PID) print("Awaiting...") fl.flAwaitDevice(VID_PID, 600) conn = fl.flOpen(VID_PID) fl.flSingleBitPortAccess(conn, 3, 7, fl.PIN_LOW) print("flMultiBitPortAccess() returned {:032b}".format( fl.flMultiBitPortAccess(conn, "D7+"))) fl.flSleep(100) print("flGetFirmwareID(): {:04X}".format(fl.flGetFirmwareID(conn))) print("flGetFirmwareVersion(): {:08X}".format(fl.flGetFirmwareVersion(conn))) print("flIsNeroCapable(): {}".format(fl.flIsNeroCapable(conn))) print("flIsCommCapable(): {}".format(fl.flIsCommCapable(conn, CONDUIT))) fl.progOpen(conn, PROG_CONFIG) print("progGetPort(): {") (port, bit) = fl.progGetPort(conn, fl.LP_MISO) print(" MISO: {:c}{}".format(ord('A')+port, bit))
) parser.add_argument("-q", action="store", nargs=1, metavar="<jtagPorts>", help="query the JTAG chain") parser.add_argument("-p", action="store", nargs=1, metavar="<config>", help="program a device") parser.add_argument( "-c", action="store", nargs=1, metavar="<conduit>", help="which comm conduit to choose (default 0x01)" ) parser.add_argument("-f", action="store", nargs=1, metavar="<dataFile>", help="binary data to write to channel 0") argList = parser.parse_args() handle = fl.FLHandle() try: fl.flInitialise(0) vp = argList.v[0] print("Attempting to open connection to FPGALink device {}...".format(vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: if argList.i: ivp = argList.i[0] print("Loading firmware into {}...".format(ivp)) fl.flLoadStandardFirmware(ivp, vp) print("Awaiting renumeration...") if not fl.flAwaitDevice(vp, 600): raise fl.FLException("FPGALink device did not renumerate properly as {}".format(vp)) print("Attempting to open connection to FPGALink device {} again...".format(vp)) handle = fl.flOpen(vp) else: raise fl.FLException("Could not open FPGALink device at {} and no initial VID:PID was supplied".format(vp))
# along with this program. If not, see <http://www.gnu.org/licenses/>. # Read the JEDEC ID from the flash chip on the Lattice IceBlink40 board. This # example demonstrates the usage of the bit-level I/O and SPI functions. The # board has MISO=PB3, MOSI=PB2, SS=PB0, SCK=PB1, CRESET=PB6 & POWER=C2. # import fl VID_PID = "1D50:602B:0001" PROG_CONFIG = "B3B2B0B1" handle = fl.FLHandle() try: fl.flInitialise(0) # Connect, reset the board, open SPI interface & get SS port: handle = fl.flOpen(VID_PID) fl.flMultiBitPortAccess(handle, "B6-,C2-") # RESET low & cut the power fl.flSleep(10) fl.flSingleBitPortAccess(handle, 2, 2, fl.PIN_HIGH) # power on in RESET fl.progOpen(handle, PROG_CONFIG) (port, bit) = fl.progGetPort(handle, fl.LP_SS) fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_HIGH) # Send JEDEC device-id command, retrieve three bytes back fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_LOW) fl.spiSend(handle, b"\x9F", fl.SPI_MSBFIRST) bs = fl.spiRecv(handle, 3, fl.SPI_MSBFIRST) print("JEDEC ID: {}".format(" ".join(["{:02X}".format(b) for b in bs]))) fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_HIGH) # Close SPI interface, release reset and close connection
def main(): argList = get_args() print(argList) handle = fl.FLHandle() try: fl.flInitialise(0) vp = argList.v[0] print("Attempting to open connection to FPGALink device {}...".format( vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: handle = ids(vp, argList) if argList.c: isNeroCapable, isCommCapable = conduit_selection(int(argList.c[0])) else: isNeroCapable, isCommCapable = conduit_selection() jtag_chain(isNeroCapable, argList, vp, handle) configure(argList, isNeroCapable, handle, vp) if argList.f and not isCommCapable: raise fl.FLException( "Data file load requested but device at {} does not support CommFPGA" .format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) if argList.ppm: M = int(eval(argList.ppm[0])) print("Setting PPM order to: ", M) fpga.setPPM_M(M) if argList.txdel: delay = int(eval(argList.txdel[0])) print("Setting transmitter loopback delay to %i (0x%X)" % (delay, delay)) fpga.setTXdelay(delay) if argList.dac: dacval = int(eval(argList.dac[0])) print("Setting DAC value to %i (0x%X)" % (dacval, dacval)) fpga.writeDAC(dacval) if argList.prbs: print("Enabling PRBS") fpga.usePRBS() else: print("Disabling PRBS") fpga.usePRBS(False) if argList.peak: obslength = float(argList.peak) print("Measuring peak power...") peakDAC = fpga.binSearchPeak(M, target=1.0 / M, obslength=obslength) print(" DAC = %i" % peakDAC) #alg testing goes here, but alg is not up to date!! opt_alg(argList, fpga) except fl.FLException as ex: print(ex) finally: fl.flClose(handle)
# along with this program. If not, see <http://www.gnu.org/licenses/>. # Read the JEDEC ID from the flash chip on the Lattice IceBlink40 board. This # example demonstrates the usage of the bit-level I/O and SPI functions. The # board has MISO=PB3, MOSI=PB2, SS=PB0, SCK=PB1, CRESET=PB6 & POWER=C2. # import fl VID_PID = "1D50:602B:0001" PROG_CONFIG = "B3B2B0B1" handle = fl.FLHandle() try: fl.flInitialise(0) # Connect, reset the board, open SPI interface & get SS port: handle = fl.flOpen(VID_PID) fl.flMultiBitPortAccess(handle, "B6-,C2-") # RESET low & cut the power fl.flSleep(10) fl.flSingleBitPortAccess(handle, 2, 2, fl.PIN_HIGH) # power on in RESET fl.progOpen(handle, PROG_CONFIG) (port, bit) = fl.progGetPort(handle, fl.LP_SS) fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_HIGH) # Send JEDEC device-id command, retrieve three bytes back fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_LOW) fl.spiSend(handle, b"\x9F", fl.SPI_MSBFIRST) bs = fl.spiRecv(handle, 3, fl.SPI_MSBFIRST) print("JEDEC ID: {}".format( " ".join(["{:02X}".format(b) for b in bs]))) fl.flSingleBitPortAccess(handle, port, bit, fl.PIN_HIGH)
def SPImain(): argList = getArgs() handle = fl.FLHandle() try: fl.flInitialise(0) vp = argList['fpga_vid_pid_did'] print("Attempting to open connection to FPGALink device {}...".format(vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: ivp = argList['fpga_vid_pid'] print("Loading firmware into {}...".format(ivp)) fl.flLoadStandardFirmware(ivp, vp) mem_map = mmap.Tester(ivp, vp) # Long delay for renumeration # TODO: fix this hack. The timeout value specified in flAwaitDevice() below doesn't seem to work time.sleep(3) print("Awaiting renumeration...") if not fl.flAwaitDevice(vp, 10000): raise fl.FLException("FPGALink device did not renumerate properly as {}".format(vp)) print("Attempting to open connection to FPGALink device {} again...".format(vp)) handle = fl.flOpen(vp) # if ( argList.d ): # print("Configuring ports...") # rb = "{:0{}b}".format(fl.flMultiBitPortAccess(handle, argList.d[0]), 32) # print("Readback: 28 24 20 16 12 8 4 0\n {} {} {} {} {} {} {} {}".format( # rb[0:4], rb[4:8], rb[8:12], rb[12:16], rb[16:20], rb[20:24], rb[24:28], rb[28:32])) # fl.flSleep(100) conduit = 1 isNeroCapable = fl.flIsNeroCapable(handle) isCommCapable = fl.flIsCommCapable(handle, conduit) fl.flSelectConduit(handle, conduit) if argList['dataToWrite'] != None and not(isCommCapable): raise fl.FLException("Data file load requested but device at {} does not support CommFPGA".format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) opt = Optimizer(handle, fpga) #Test setting LD Bias to 0.150A (channels 26, 27) #opt.setCurrent(0.150) #this section of code looks like setLaserCurrent() curr = 0.150 code = curr/(4.096*1.1*((1/6.81)+(1/16500)))*4096 first_byte, second_byte = opt.code2bytes(code) spi_data = [first_byte, second_byte] updateSPI(handle, [mem_map.getAddress('LCCa'), mem_map.getAddress('LCCb')], spi_data) #Test reading LD Bias (channels 64 and 65) rx_bias = readSPI(handle, [mem_map.getAddress('CC3a'), mem_map.getAddress('CC3b')]) for r in rx_bias: print ("Bias bytes read: ", r) print (rx_bias[1]*256 + rx_bias[0])/4096 * (4.096*1.1*((1/6.81)+(1/16500))) #Test writing/reading to LD Temp #TODO Constants are estimated; may need to verify with vendor R_known = 10000 Vcc = 0.8 B = 3900 R_0 = 10000 T_0 = 25 #writing temp 35C T = 35 V_set = Vcc/(((m.exp(B/T)*(R_0 * m.exp(-B/T_0)))/R_known)+1) V_code = opt.voltage2code(V_set) #convert voltage to code fb, sb = opt.code2byte(V_code) #convert code to bytes updateSPI(handle, [mem_map.getAddress('LTSa'),mem_map.getAddress('LTSb')], [fb, sb]) #reading temp bytes__meas = readSPI(handle, [mem_map.getAddress('LTMa'),mem_map.getAddress('LTMb')]) #read ADC value code_meas = bytes_meas[1]*256 + bytes_meas[0] #convert bytes to double V_meas = opt.code2voltage(code_meas) #convert ADC to voltage R_t = R_known * (Vcc/V_meas - 1) T = B/m.log(R_t/R_0 * m.exp(-B/T_0)) print ("Temp read: ", T) #Test reading from RTD A = 3.81e-3 #from datasheet B = -6.02e-7 #from datasheet R_t0 = 1000 T_bm = readSPI(handle, [mem_map.getAddress('TE1a'),mem_map.getAddress('TE1b')]) #temp code measured T_cm = 256*T_bm[1] + T_bm[0] #convert bytes to double T_meas = opt.code2voltage(T_cm) #convert ADC to voltage R_T = R_known * (Vcc/T_meas - 1) C = 1 -( R_T/R_t0) T_R = (-A + (A**2-(4*B*C))**0.5) / (2*B) print ("RTD temp: ", T_R)
numDev = len(os.listdir(usbDevPath)) if numDev >= 4: break except: pass time.sleep(0.25) timeoutCounter += 1 print("Found %d USB devices" % numDev) try: print("Initializing FPGALink library...") fl.flInitialise(3) print("Attempting to open connection to FPGALink device {}...".format(vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: print(ex) print("Loading standard firmware into RAM {}...".format(ivp)) fl.flLoadStandardFirmware(ivp, vp) time.sleep(3) fl.flAwaitDevice(vp, 10000) print("Attempting to open connection to FPGALink device {} again...".format(vp)) handle = fl.flOpen(vp) conduit = 1 isNeroCapable = fl.flIsNeroCapable(handle) isCommCapable = fl.flIsCommCapable(handle, conduit) fl.flSelectConduit(handle, conduit) if ( isNeroCapable ):
An opaque reference to an internal structure representing the connection. This must be freed at some later time by a call to \c flClose(), or a resource-leak will ensue. """ if argList.i: ivp = argList.i[0] print("Loading firmware into {}...".format(ivp)) fl.flLoadStandardFirmware(ivp, vp) # Long delay for renumeration # TODO: fix this hack. The timeout value specified in flAwaitDevice() below doesn't seem to work time.sleep(3) print("Awaiting renumeration...") if ( not fl.flAwaitDevice(vp, 10000) ): raise fl.FLException("FPGALink device did not renumerate properly as {}".format(vp)) print("Attempting to open connection to FPGALink device {} again...".format(vp)) return fl.flOpen(vp) else: raise fl.FLException("Could not open FPGALink device at {} and no initial VID:PID was supplied".format(vp)) def conduit_selection(argList_c=1): """ Selects conduit and checks if the FPGA board is nero capable and capable of communication. Args: argList_c(int): comm conduit to chose Returns: (tuple): booleans indicating if device is nero capable and comm capable """ isNeroCapable = fl.flIsNeroCapable(handle) isCommCapable = fl.flIsCommCapable(handle, conduit) fl.flSelectConduit(handle, conduit)