예제 #1
0
파일: i2s.py 프로젝트: scryver/fpga
def Serial2Parallel(sdata, start, dout, sclk):

    M = len(dout)
    assert M > 2
    buf = create_signals(M)
    en = create_signals(M - 1)

    shift_msb = ff.dff_set(en[M - 2], False, start, sclk)
    buf_msb = ff.dffe(buf[M - 1], sdata, start, sclk)

    shifts = [ff.dff_reset(en[M - 3 - i], en[M - 2 - i], sclk, start)
              for i in range(M - 2)]
    bufs = [ff.dffe_rst(buf[M - 2 - i], sdata, en[M - 2 - i], sclk, start)
            for i in range(M - 1)]

    if dout.min < 0:
        @always(sclk.posedge)
        def logic():
            if start:
                t = intbv(0, _nrbits=M)
                for i in range(M):
                    t[i] = buf[i]
                dout.next = t.signed()
    else:
        @always(sclk.posedge)
        def logic():
            if start:
                t = intbv(0, _nrbits=M)
                for i in range(M):
                    t[i] = buf[i]
                dout.next = t

    return shift_msb, shifts, buf_msb, bufs, logic
예제 #2
0
    def bench_async():
        q, d = create_signals(2, 8)
        p_rst = create_signals(1)
        clock, reset = create_clock_reset(rst_active=False, rst_async=True)

        dffa_inst = ff.dff_reset(q, d, clock, reset)

        clock_gen = clocker(clock)

        @always(clock.negedge)
        def stimulus():
            if reset and p_rst:
                assert d == q

            p_rst.next = reset
            d.next = randrange(2)

        @instance
        def reset_gen():
            yield delay(5)
            reset.next = 1

            while True:
                yield delay(randrange(500, 1000))
                reset.next = 0
                yield delay(randrange(80, 140))
                reset.next = 1

        return dffa_inst, clock_gen, stimulus, reset_gen
예제 #3
0
def Serial2Parallel(sdata, start, dout, sclk):

    M = len(dout)
    assert M > 2
    buf = create_signals(M)
    en = create_signals(M - 1)

    shift_msb = ff.dff_set(en[M - 2], False, start, sclk)
    buf_msb = ff.dffe(buf[M - 1], sdata, start, sclk)

    shifts = [
        ff.dff_reset(en[M - 3 - i], en[M - 2 - i], sclk, start)
        for i in range(M - 2)
    ]
    bufs = [
        ff.dffe_rst(buf[M - 2 - i], sdata, en[M - 2 - i], sclk, start)
        for i in range(M - 1)
    ]

    if dout.min < 0:

        @always(sclk.posedge)
        def logic():
            if start:
                t = intbv(0, _nrbits=M)
                for i in range(M):
                    t[i] = buf[i]
                dout.next = t.signed()
    else:

        @always(sclk.posedge)
        def logic():
            if start:
                t = intbv(0, _nrbits=M)
                for i in range(M):
                    t[i] = buf[i]
                dout.next = t

    return shift_msb, shifts, buf_msb, bufs, logic
예제 #4
0
    def bench_sync():
        q, d = create_signals(2, 8)
        p_rst = create_signals(1)
        clock, reset = create_clock_reset()

        dffa_inst = ff.dff_reset(q, d, clock, reset)

        clock_gen = clocker(clock)

        @always(clock.negedge)
        def stimulus():
            if not p_rst:
                assert d == q
            # print("CLK DOWN | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
            #       q, clock))

            d.next = randrange(2)

        @always(clock.posedge)
        def reset_buf_dly():
            # print("CLK UP   | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
            #       q, clock))
            p_rst.next = reset

        @instance
        def reset_gen():
            yield delay(5)
            reset.next = 0

            while True:
                yield delay(randrange(500, 1000))
                reset.next = 1
                yield delay(randrange(80, 140))
                reset.next = 0

        return dffa_inst, clock_gen, stimulus, reset_gen, reset_buf_dly
예제 #5
0
    def bench_sync():
        q, d = create_signals(2, 8)
        p_rst = create_signals(1)
        clock, reset = create_clock_reset()

        dffa_inst = ff.dff_reset(q, d, clock, reset)

        clock_gen = clocker(clock)

        @always(clock.negedge)
        def stimulus():
            if not p_rst:
                assert d == q
            # print("CLK DOWN | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
            #       q, clock))

            d.next = randrange(2)

        @always(clock.posedge)
        def reset_buf_dly():
            # print("CLK UP   | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
            #       q, clock))
            p_rst.next = reset

        @instance
        def reset_gen():
            yield delay(5)
            reset.next = 0

            while True:
                yield delay(randrange(500, 1000))
                reset.next = 1
                yield delay(randrange(80, 140))
                reset.next = 0

        return dffa_inst, clock_gen, stimulus, reset_gen, reset_buf_dly