def bench_async():
q, d = create_signals(2, 8)
p_rst = create_signals(1)
clock, reset = create_clock_reset(rst_active=False, rst_async=True)
dffa_inst = ff.dff_reset(q, d, clock, reset)
clock_gen = clocker(clock)
@always(clock.negedge)
def stimulus():
if reset and p_rst:
assert d == q
p_rst.next = reset
d.next = randrange(2)
@instance
def reset_gen():
yield delay(5)
reset.next = 1
while True:
yield delay(randrange(500, 1000))
reset.next = 0
yield delay(randrange(80, 140))
reset.next = 1
return dffa_inst, clock_gen, stimulus, reset_gen
def bench_async():
q, d = create_signals(2, 8)
p_rst = create_signals(1)
clock, reset = create_clock_reset(rst_active=False, rst_async=True)
dffa_inst = ff.dff(clock, d, q, reset=reset)
clock_gen = clocker(clock)
@always(clock.negedge)
def stimulus():
if reset and p_rst:
assert d == q
p_rst.next = reset
d.next = randrange(2)
@instance
def reset_gen():
yield delay(5)
reset.next = 1
while True:
yield delay(randrange(500, 1000))
reset.next = 0
yield delay(randrange(80, 140))
reset.next = 1
return dffa_inst, clock_gen, stimulus, reset_gen
def convert_multiplier():
BITS = 35
a, b = create_signals(2, BITS, signed=True, delay=None)
p = create_signals(1, 2 * BITS, signed=True, delay=None)
clk, rst = create_clock_reset()
toVHDL(mult.Multiplier35Bit, a, b, p, clk, rst)
def convert_multiplier():
BITS = 35
a, b = create_signals(2, BITS, signed=True, delay=None)
p = create_signals(1, 2 * BITS, signed=True, delay=None)
clk, rst = create_clock_reset()
toVHDL(mult.Multiplier35Bit, a, b, p, clk, rst)
def convert_three_port_multiplier():
BITS = 35
a, b, c, d, e, f = create_signals(6, BITS, signed=True, delay=None)
load = create_signals(1, (0, 4))
clk_ena = create_signals(1)
clk, rst = create_clock_reset()
ab_rdy, cd_rdy, ef_rdy = create_signals(3)
ab, cd, ef = create_signals(3, 2 * BITS, signed=True, delay=None)
toVHDL(mult.ThreePortMultiplier35Bit, a, b, c, d, e, f, load, clk_ena, clk, rst, ab, ab_rdy, cd, cd_rdy, ef, ef_rdy)
def convert_addressable_multiplier():
BITS = 35
ADDRESSES = 3
a, b = create_signals(2, BITS, signed=True, delay=None)
p = create_signals(1, 2 * BITS, signed=True, delay=None)
address_in, address_out = create_signals(2, (0, ADDRESSES + 1), mod=True)
ce = create_signals(1)
clk, rst = create_clock_reset()
toVHDL(mult.AddressableMultiplier35Bit, a, b, p, address_in, address_out, ce, clk, rst)
def convert_three_port_multiplier():
BITS = 35
a, b, c, d, e, f = create_signals(6, BITS, signed=True, delay=None)
load = create_signals(1, (0, 4))
clk_ena = create_signals(1)
clk, rst = create_clock_reset()
ab_rdy, cd_rdy, ef_rdy = create_signals(3)
ab, cd, ef = create_signals(3, 2 * BITS, signed=True, delay=None)
toVHDL(mult.ThreePortMultiplier35Bit, a, b, c, d, e, f, load, clk_ena, clk,
rst, ab, ab_rdy, cd, cd_rdy, ef, ef_rdy)
def convert_addressable_multiplier():
BITS = 35
ADDRESSES = 3
a, b = create_signals(2, BITS, signed=True, delay=None)
p = create_signals(1, 2 * BITS, signed=True, delay=None)
address_in, address_out = create_signals(2, (0, ADDRESSES + 1), mod=True)
ce = create_signals(1)
clk, rst = create_clock_reset()
toVHDL(mult.AddressableMultiplier35Bit, a, b, p, address_in, address_out,
ce, clk, rst)
def convert_shared_multiplier():
# @TODO (michiel): This fails
inputs = create_signals(6, 35, signed=True, delay=None)
load = create_signals(1, 2, delay=None)
p_sigs = create_signals(3, 2 * 35, signed=True, delay=None)
p_rdys = create_signals(3, delay=None)
ce = create_signals(1)
clk, rst = create_clock_reset()
left, right = create_signals(2, 32, signed=True, delay=None)
toVHDL(mult.SharedMultiplier, inputs[:3], inputs[3:], load, ce, clk, rst, p_sigs, p_rdys)
def convert_shared_multiplier():
# @TODO (michiel): This fails
inputs = create_signals(6, 35, signed=True, delay=None)
load = create_signals(1, 2, delay=None)
p_sigs = create_signals(3, 2 * 35, signed=True, delay=None)
p_rdys = create_signals(3, delay=None)
ce = create_signals(1)
clk, rst = create_clock_reset()
left, right = create_signals(2, 32, signed=True, delay=None)
toVHDL(mult.SharedMultiplier, inputs[:3], inputs[3:], load, ce, clk, rst,
p_sigs, p_rdys)
def bench():
M = 8
load, dout_msb, dout_lsb = create_signals(3)
clock, reset = create_clock_reset()
din = Signal(intbv(0, min=0, max=2**M))
dut = p2s.p2s_msb(din, load, dout_msb, clock, reset)
dut2 = p2s.p2s_lsb(din, load, dout_lsb, clock, reset)
clockgen = clocker(clock)
def input_gen():
for i in range(2**M):
yield i
@instance
def input_switch():
yield clock.negedge
a = input_gen()
for i in range(2**M):
din.next = next(a)
for k in range(M):
yield clock.negedge
load.next = k == 0
@instance
def check():
yield clock.negedge
reset.next = False
for j in range(2**M):
yield load.negedge
o_msb = intbv(0, min=din.min, max=din.max)
o_lsb = intbv(0, min=din.min, max=din.max)
for k in range(M):
yield clock.negedge
o_msb[M - 1 - k] = dout_msb
o_lsb[k] = dout_lsb
# print(j, o_msb, o_lsb)
# assert j == o_msb == o_lsb
raise StopSimulation
return dut, dut2, clockgen, input_switch, check
def bench():
M = 8
load, dout_msb, dout_lsb = create_signals(3)
clock, reset = create_clock_reset()
din = Signal(intbv(0, min=0, max=2**M))
dut = p2s.p2s_msb(din, load, dout_msb, clock, reset)
dut2 = p2s.p2s_lsb(din, load, dout_lsb, clock, reset)
clockgen = clocker(clock)
def input_gen():
for i in range(2 ** M):
yield i
@instance
def input_switch():
yield clock.negedge
a = input_gen()
for i in range(2 ** M):
din.next = next(a)
for k in range(M):
yield clock.negedge
load.next = k == 0
@instance
def check():
yield clock.negedge
reset.next = False
for j in range(2 ** M):
yield load.negedge
o_msb = intbv(0, min=din.min, max=din.max)
o_lsb = intbv(0, min=din.min, max=din.max)
for k in range(M):
yield clock.negedge
o_msb[M - 1 - k] = dout_msb
o_lsb[k] = dout_lsb
# print(j, o_msb, o_lsb)
# assert j == o_msb == o_lsb
raise StopSimulation
return dut, dut2, clockgen, input_switch, check
def bench():
BITS = 35
MAX = 2**BITS // 2
a, b = create_signals(2, BITS, signed=True)
p = create_signals(1, 2 * BITS, signed=True)
clk, rst = create_clock_reset()
address_in, address_out = create_signals(2, 3, mod=True)
pipeline = {i: (0, 0, 0, 0)
for i in range(len(address_in))} # Check pipeline
mult_inst = mult.AddressableMultiplier35Bit(a, b, p, address_in,
address_out, clk, rst)
clock_gen = clocker(clk)
@instance
def stimulus():
yield clk.negedge
rst.next = False
while True:
yield clk.negedge
a.next = randrange(-MAX, MAX)
b.next = randrange(-MAX, MAX)
address_in.next = address_in + 1
check_address, check_a, check_b, check_p = pipeline[int(
address_out)]
# print('-' * 20)
# print(address_out, address_in)
# print('-' * 20)
# print(pipeline)
# print('-' * 20)
assert check_address == address_out and check_p == p
pipeline[int(address_in)] = int(address_in), int(a), int(
b), int(a * b)
return mult_inst, clock_gen, stimulus
def bench():
BITS = 35
MAX = 2 ** BITS // 2
a, b = create_signals(2, BITS, signed=True)
p = create_signals(1, 2 * BITS, signed=True)
clk, rst = create_clock_reset()
address_in, address_out = create_signals(2, 3, mod=True)
pipeline = {i: (0, 0, 0, 0) for i in range(len(address_in))} # Check pipeline
mult_inst = mult.AddressableMultiplier35Bit(a, b, p, address_in, address_out, clk, rst)
clock_gen = clocker(clk)
@instance
def stimulus():
yield clk.negedge
rst.next = False
while True:
yield clk.negedge
a.next = randrange(-MAX, MAX)
b.next = randrange(-MAX, MAX)
address_in.next = address_in + 1
check_address, check_a, check_b, check_p = pipeline[int(address_out)]
# print('-' * 20)
# print(address_out, address_in)
# print('-' * 20)
# print(pipeline)
# print('-' * 20)
assert check_address == address_out and check_p == p
pipeline[int(address_in)] = int(address_in), int(a), int(b), int(a * b)
return mult_inst, clock_gen, stimulus
def bench_sync():
q, d = create_signals(2, 8)
p_rst = create_signals(1)
clock, reset = create_clock_reset()
dffa_inst = ff.dff_reset(q, d, clock, reset)
clock_gen = clocker(clock)
@always(clock.negedge)
def stimulus():
if not p_rst:
assert d == q
# print("CLK DOWN | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
# q, clock))
d.next = randrange(2)
@always(clock.posedge)
def reset_buf_dly():
# print("CLK UP | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
# q, clock))
p_rst.next = reset
@instance
def reset_gen():
yield delay(5)
reset.next = 0
while True:
yield delay(randrange(500, 1000))
reset.next = 1
yield delay(randrange(80, 140))
reset.next = 0
return dffa_inst, clock_gen, stimulus, reset_gen, reset_buf_dly
def bench_sync():
q, d = create_signals(2, 8)
p_rst = create_signals(1)
clock, reset = create_clock_reset()
dffa_inst = ff.dff_reset(q, d, clock, reset)
clock_gen = clocker(clock)
@always(clock.negedge)
def stimulus():
if not p_rst:
assert d == q
# print("CLK DOWN | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
# q, clock))
d.next = randrange(2)
@always(clock.posedge)
def reset_buf_dly():
# print("CLK UP | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
# q, clock))
p_rst.next = reset
@instance
def reset_gen():
yield delay(5)
reset.next = 0
while True:
yield delay(randrange(500, 1000))
reset.next = 1
yield delay(randrange(80, 140))
reset.next = 0
return dffa_inst, clock_gen, stimulus, reset_gen, reset_buf_dly
def bench():
BITS = 35
MAX = 2**(BITS - 1)
# The input signals
# The numbers to multiply. a * b and c * d
a, b, c, d, e, f = create_signals(6, BITS, signed=True)
# The load signal, max = number of inputs signals + 1
# A value of 0 will not load anything.
load = create_signals(1, 2)
# The output signals
# The multiplied output signals
p_ab, p_cd, p_ef = create_signals(3, 2 * BITS, signed=True)
ab_ready, cd_ready, ef_ready = create_signals(3)
p_sigs = create_signals(3, 2 * BITS, signed=True)
p_rdys = create_signals(3)
# Test bench global clock and reset
clk, rst = create_clock_reset()
# Test bench check values
pipeline1 = []
pipeline2 = []
pipeline3 = []
mult_inst = mult.ThreePortMultiplier35Bit(a, b, c, d, e, f, load, clk,
rst, p_ab, ab_ready, p_cd,
cd_ready, p_ef, ef_ready)
mult_inst2 = mult.SharedMultiplier([a, c, e], [b, d, f], load, clk,
rst, p_sigs, p_rdys)
clock_gen = clocker(clk)
# Loader
@instance
def loader():
i = 0
while True:
yield clk.negedge
if i < 5:
load.next = 0
elif i < 10:
load.next = 1
elif i < 15:
load.next = 2
elif i < 20:
load.next = 3
i += 1
i %= 20
def string_mult(a, b):
return "| {:5.2e} * {:5.2e} = {:5.2e}".format(
*map(float, (a, b, a * b)))
@instance
def stimulus():
yield clk.negedge
rst.next = False
while True:
yield clk.negedge
a.next = randrange(-MAX, MAX)
b.next = randrange(-MAX, MAX)
c.next = randrange(-MAX, MAX)
d.next = randrange(-MAX, MAX)
e.next = randrange(-MAX, MAX)
f.next = randrange(-MAX, MAX)
# check_address, check_a, check_b, check_p = pipeline[int(address_out)]
print('-' * 20)
print(load, string_mult(a, b), string_mult(c, d),
string_mult(e, f))
print('-' * 20)
if ab_ready:
print("AB: {:5.2e}".format(float(p_ab)))
if cd_ready:
print("CD: {:5.2e}".format(float(p_cd)))
if ef_ready:
print("EF: {:5.2e}".format(float(p_ef)))
print('-' * 20)
if p_rdys[0]:
print("AB2: {:5.2e}".format(float(p_sigs[0])))
if p_rdys[1]:
print("CD2: {:5.2e}".format(float(p_sigs[1])))
if p_rdys[2]:
print("EF2: {:5.2e}".format(float(p_sigs[2])))
print('-' * 20)
# assert check_address == address_out and check_p == p
# pipeline[int(address_in)] = int(address_in), int(a), int(b), int(a * b)
return mult_inst, mult_inst2, clock_gen, loader, stimulus
def bench():
BITS = 35
MAX = 2 ** (BITS - 1)
# The input signals
# The numbers to multiply. a * b and c * d
a, b, c, d, e, f = create_signals(6, BITS, signed=True)
# The load signal, max = number of inputs signals + 1
# A value of 0 will not load anything.
load = create_signals(1, 2)
# The output signals
# The multiplied output signals
p_ab, p_cd, p_ef = create_signals(3, 2 * BITS, signed=True)
ab_ready, cd_ready, ef_ready = create_signals(3)
p_sigs = create_signals(3, 2 * BITS, signed=True)
p_rdys = create_signals(3)
# Test bench global clock and reset
clk, rst = create_clock_reset()
# Test bench check values
pipeline1 = []
pipeline2 = []
pipeline3 = []
mult_inst = mult.ThreePortMultiplier35Bit(a, b, c, d, e, f, load,
clk, rst,
p_ab, ab_ready,
p_cd, cd_ready,
p_ef, ef_ready)
mult_inst2 = mult.SharedMultiplier([a, c, e], [b, d, f], load, clk, rst,
p_sigs, p_rdys)
clock_gen = clocker(clk)
# Loader
@instance
def loader():
i = 0
while True:
yield clk.negedge
if i < 5:
load.next = 0
elif i < 10:
load.next = 1
elif i < 15:
load.next = 2
elif i < 20:
load.next = 3
i += 1
i %= 20
def string_mult(a, b):
return "| {:5.2e} * {:5.2e} = {:5.2e}".format(*map(float, (a, b, a * b)))
@instance
def stimulus():
yield clk.negedge
rst.next = False
while True:
yield clk.negedge
a.next = randrange(-MAX, MAX)
b.next = randrange(-MAX, MAX)
c.next = randrange(-MAX, MAX)
d.next = randrange(-MAX, MAX)
e.next = randrange(-MAX, MAX)
f.next = randrange(-MAX, MAX)
# check_address, check_a, check_b, check_p = pipeline[int(address_out)]
print('-' * 20)
print(load, string_mult(a, b), string_mult(c, d), string_mult(e, f))
print('-' * 20)
if ab_ready:
print("AB: {:5.2e}".format(float(p_ab)))
if cd_ready:
print("CD: {:5.2e}".format(float(p_cd)))
if ef_ready:
print("EF: {:5.2e}".format(float(p_ef)))
print('-' * 20)
if p_rdys[0]:
print("AB2: {:5.2e}".format(float(p_sigs[0])))
if p_rdys[1]:
print("CD2: {:5.2e}".format(float(p_sigs[1])))
if p_rdys[2]:
print("EF2: {:5.2e}".format(float(p_sigs[2])))
print('-' * 20)
# assert check_address == address_out and check_p == p
# pipeline[int(address_in)] = int(address_in), int(a), int(b), int(a * b)
return mult_inst, mult_inst2, clock_gen, loader, stimulus
def convert_async_dff():
q, d = create_signals(2, 4)
clk, rst = create_clock_reset(rst_async=True)
converter = CustomVHDL()
converter(ff.dff, q, d, clk, rst)
def convert_async_dff():
q, d = create_signals(2, 4)
clk, rst = create_clock_reset(rst_async=True)
converter = CustomVHDL()
converter(ff.dff, q, d, clk, rst)
def convert_p2s_msb():
i, o = create_signals(2, 8, signed=True)
load = create_signals(1)
clk, rst = create_clock_reset()
toVHDL(p2s.p2s_msb, i, load, o, clk, rst)
def convert_p2s_msb():
i, o = create_signals(2, 8, signed=True)
load = create_signals(1)
clk, rst = create_clock_reset()
toVHDL(p2s.p2s_msb, i, load, o, clk, rst)
