def test_value_type_message(self):
spec = ControllerSpec(8, 8)
opcode = int('1010', 2)
value = int('1100110011001100', 2)
expected = int('10101100110011001100', 2)
message = spec.value_type_message(opcode, value)
self.assertEquals(message, expected)
with self.assertRaises(ValueError):
value = int('11111111111111111', 2)
message = spec.value_type_message(opcode, value)
def test_value_type_message(self):
spec = ControllerSpec(8, 8)
opcode = int('1010', 2)
value = int('1100110011001100', 2)
expected = int('10101100110011001100', 2)
message = spec.value_type_message(opcode, value)
self.assertEquals(message, expected)
with self.assertRaises(ValueError):
value = int('11111111111111111', 2)
message = spec.value_type_message(opcode, value)
def test_addr_type_message(self):
spec = ControllerSpec(8, 8)
opcode = int('1010', 2)
address = int('10111111', 2)
data = int('11111111', 2)
expected = int('10101011111111111111', 2)
message = spec.addr_type_message(opcode, address, data)
self.assertEquals(message, expected)
with self.assertRaises(ValueError):
data = int('111111111', 2)
message = spec.addr_type_message(opcode, address, data)
def test_message_classification(self):
spec = ControllerSpec(1,1)
# Test one from within the set
self.assertTrue(spec.is_addr_type_response(
spec.opcode_res_read_success))
self.assertFalse(spec.is_value_type_response(
spec.opcode_res_read_success))
# Test one from outside the set
self.assertFalse(spec.is_addr_type_command(
spec.opcode_cmd_step))
self.assertTrue(spec.is_value_type_command(
spec.opcode_cmd_step))
def test_addr_type_message(self):
spec = ControllerSpec(8, 8)
opcode = int('1010', 2)
address = int('10111111', 2)
data = int('11111111', 2)
expected = int('10101011111111111111', 2)
message = spec.addr_type_message(opcode, address, data)
self.assertEquals(message, expected)
with self.assertRaises(ValueError):
data = int('111111111', 2)
message = spec.addr_type_message(opcode, address, data)
def test_parse(self):
spec = ControllerSpec(8, 8)
message = int('10101100110011110000', 2)
parsed_opcode = spec.parse_opcode(message)
self.assertEquals(parsed_opcode, int('1010', 2))
parsed_addr = spec.parse_addr(message)
self.assertEquals(parsed_addr, int('11001100', 2))
parsed_data = spec.parse_data(message)
self.assertEquals(parsed_data, int('11110000', 2))
parsed_value = spec.parse_value(message)
self.assertEquals(parsed_value, int('1100110011110000', 2))
def setUp(self):
self.spec = ControllerSpec(self.WIDTH_ADDR, self.WIDTH_DATA)
# input signals
self.opcode_cmd = Signal(intbv(0)[self.spec.width_opcode:0])
self.rx_ready = Signal(False)
self.tx_ready = Signal(False)
self.cycle_autonomous = Signal(False)
self.reset = ResetSignal(True, active=False, async=False)
# output signals
self.rx_next = Signal(False)
self.opcode_res = Signal(intbv(0)[self.spec.width_message:0])
self.nop = Signal(False)
self.exp_wen = Signal(False)
self.exp_reset = ResetSignal(True, active=self.EXP_RESET_ACTIVE,
async=False)
self.cycle_start = Signal(False)
self.cycle_pause = Signal(False)
self.cycle_step = Signal(False)
self.control = ControllerControl(spec=self.spec, reset=self.reset,
opcode_cmd=self.opcode_cmd, opcode_res=self.opcode_res,
rx_ready=self.rx_ready,
rx_next=self.rx_next,
tx_ready=self.tx_ready, nop=self.nop,
exp_wen=self.exp_wen, exp_reset=self.exp_reset,
cycle_autonomous=self.cycle_autonomous,
cycle_start=self.cycle_start, cycle_pause=self.cycle_pause,
cycle_step=self.cycle_step,
exp_reset_active=self.EXP_RESET_ACTIVE)
def test_width_and_index_attrs(self):
width_data = 12
width_addr = 22
width_opcode = 4
width_value = 34
width_message = 38
width_message_bytes = 5
spec = ControllerSpec(width_addr, width_data)
self.assertEquals(spec.width_opcode, width_opcode,
'_WIDTH_OPCODE constant has changed')
self.assertEquals(spec.width_data, width_data)
self.assertEquals(spec.width_addr, width_addr)
self.assertEquals(spec.width_value, width_value)
self.assertEquals(spec.width_message, width_message)
self.assertEquals(spec.width_message_bytes, width_message_bytes)
self.assertEquals(spec.index_opcode_high, 37)
self.assertEquals(spec.index_opcode_low, 34)
self.assertEquals(spec.index_addr_high, 33)
self.assertEquals(spec.index_addr_low, 12)
self.assertEquals(spec.index_data_high, 11)
self.assertEquals(spec.index_data_low, 0)
self.assertEquals(spec.index_value_high, 33)
self.assertEquals(spec.index_value_low, 0)
def setUp(self):
self.spec = ControllerSpec(self.WIDTH_ADDR, self.WIDTH_DATA)
# Input signals
self.clk = Signal(False)
self.reset = ResetSignal(True, active=False, async=False)
self.rx_fifo_data_read = Signal(intbv(0)[8:0])
self.rx_fifo_empty = Signal(False)
self.receive_next = Signal(False)
# Output signals
self.message = Signal(intbv(0)[self.spec.width_message:0])
self.rx_fifo_dequeue = Signal(False)
self.message_ready = Signal(False)
self.clockgen = ClockGen(self.clk, self.HALF_PERIOD)
self.receiver = MessageReceiver(
spec=self.spec,
clk=self.clk,
reset=self.reset,
rx_fifo_data_read=self.rx_fifo_data_read,
rx_fifo_empty=self.rx_fifo_empty,
rx_fifo_dequeue=self.rx_fifo_dequeue,
message=self.message,
message_ready=self.message_ready,
receive_next=self.receive_next)
def test_cmd_opcodes_unique(self):
spec = ControllerSpec(1, 1)
cmd_opcodes = [
spec.opcode_cmd_read, spec.opcode_cmd_write, spec.opcode_cmd_reset,
spec.opcode_cmd_step, spec.opcode_cmd_start, spec.opcode_cmd_pause,
spec.opcode_cmd_status
]
self.assertEquals(len(set(cmd_opcodes)), len(cmd_opcodes))
def test_cmd_opcodes_defined(self):
spec = ControllerSpec(1, 1)
self.assertIsInstance(spec.opcode_cmd_read, int)
self.assertIsInstance(spec.opcode_cmd_write, int)
self.assertIsInstance(spec.opcode_cmd_reset, int)
self.assertIsInstance(spec.opcode_cmd_step, int)
self.assertIsInstance(spec.opcode_cmd_start, int)
self.assertIsInstance(spec.opcode_cmd_pause, int)
self.assertIsInstance(spec.opcode_cmd_status, int)
def setUp(self):
self.spec = ControllerSpec(self.WIDTH_ADDR, self.WIDTH_DATA)
#input signals
self.opcode_res = Signal(intbv(0)[self.spec.width_opcode:0])
self.addr = Signal(intbv(0)[self.spec.width_addr:0])
self.data = Signal(intbv(0)[self.spec.width_data:0])
self.nop = Signal(False)
self.tx_ready = Signal(False)
self.cycle_count = Signal(intbv(0)[self.spec.width_value:0])
# Output signals
self.tx_next = Signal(False)
self.tx_msg = Signal(intbv(0)[self.spec.width_message:0])
self.response_compose = ControllerResponseCompose(spec=self.spec,
opcode_res=self.opcode_res, addr=self.addr, data=self.data,
nop=self.nop, cycle_count=self.cycle_count,
tx_ready=self.tx_ready, tx_next=self.tx_next,
tx_msg=self.tx_msg)
def setUp(self):
self.spec = ControllerSpec(width_addr=self.WIDTH_ADDR,
width_data=self.WIDTH_DATA)
# Input signals
self.clk = Signal(False)
self.reset = ResetSignal(True, active=False, async=False)
self.rx_msg = Signal(intbv(0)[self.spec.width_message:0])
self.rx_ready = Signal(False)
self.tx_ready = Signal(True)
self.exp_data_read = Signal(intbv(0)[self.spec.width_data:0])
# Output signals
self.rx_next = Signal(False)
self.tx_msg = Signal(intbv(0)[self.spec.width_message:0])
self.tx_next = Signal(False)
self.exp_addr = Signal(intbv(0)[self.spec.width_addr:0])
self.exp_data_write = Signal(intbv(0)[self.spec.width_data:0])
self.exp_wen = Signal(False)
self.exp_reset = ResetSignal(not self.EXP_RESET_ACTIVE,
active=self.EXP_RESET_ACTIVE,
async=False)
self.exp_clk_en = Signal(False)
self.clockgen = ClockGen(clk=self.clk, half_period=self.HALF_PERIOD)
self.controller = Controller(spec=self.spec,
clk=self.clk,
reset=self.reset,
rx_msg=self.rx_msg,
rx_next=self.rx_next,
rx_ready=self.rx_ready,
tx_msg=self.tx_msg,
tx_next=self.tx_next,
tx_ready=self.tx_ready,
exp_addr=self.exp_addr,
exp_data_write=self.exp_data_write,
exp_data_read=self.exp_data_read,
exp_wen=self.exp_wen,
exp_reset=self.exp_reset,
exp_clk_en=self.exp_clk_en,
exp_reset_active=self.EXP_RESET_ACTIVE)
self.mock_experiment = MockExperimentSetup(
self.clk, self.reset, self.exp_addr, self.exp_data_write,
self.exp_data_read, self.exp_wen, self.exp_reset, self.exp_clk_en,
self.MEM_INIT)
def test_res_opcodes_unique(self):
spec = ControllerSpec(1, 1)
res_opcodes = [
spec.opcode_res_read_success, spec.opcode_res_read_error_mode,
spec.opcode_res_write_success, spec.opcode_res_write_error_mode,
spec.opcode_res_reset_success, spec.opcode_res_step_success,
spec.opcode_res_step_error_mode, spec.opcode_res_start_success,
spec.opcode_res_start_error_mode, spec.opcode_res_pause_success,
spec.opcode_res_pause_error_mode, spec.opcode_res_status
]
self.assertEquals(len(set(res_opcodes)), len(res_opcodes))
def test_res_opcodes_defined(self):
spec = ControllerSpec(1, 1)
self.assertIsInstance(spec.opcode_res_read_success, int)
self.assertIsInstance(spec.opcode_res_read_error_mode, int)
self.assertIsInstance(spec.opcode_res_write_success, int)
self.assertIsInstance(spec.opcode_res_write_error_mode, int)
self.assertIsInstance(spec.opcode_res_reset_success, int)
self.assertIsInstance(spec.opcode_res_step_success, int)
self.assertIsInstance(spec.opcode_res_step_error_mode, int)
self.assertIsInstance(spec.opcode_res_start_success, int)
self.assertIsInstance(spec.opcode_res_start_error_mode, int)
self.assertIsInstance(spec.opcode_res_pause_success, int)
self.assertIsInstance(spec.opcode_res_pause_error_mode, int)
self.assertIsInstance(spec.opcode_res_status, int)
def test_message_classification(self):
spec = ControllerSpec(1, 1)
# Test one from within the set
self.assertTrue(
spec.is_addr_type_response(spec.opcode_res_read_success))
self.assertFalse(
spec.is_value_type_response(spec.opcode_res_read_success))
# Test one from outside the set
self.assertFalse(spec.is_addr_type_command(spec.opcode_cmd_step))
self.assertTrue(spec.is_value_type_command(spec.opcode_cmd_step))
def setUp(self):
self.spec = ControllerSpec(width_addr=32, width_data=8)
# Input signals
self.clk = Signal(False)
self.reset = ResetSignal(True, active=False, async=False)
self.rx = Signal(False)
self.rx_next = Signal(False)
self.uart_rx_baud_tick = Signal(False)
# Output signals
self.rx_msg = Signal(intbv(0)[self.spec.width_message:0])
self.rx_ready = Signal(False)
self.clockgen = ClockGen(clk=self.clk, half_period=self.HALF_PERIOD)
self.component_rx = BoardComponentRx(spec=self.spec, clk=self.clk,
reset=self.reset, rx=self.rx, rx_msg=self.rx_msg,
rx_ready=self.rx_ready, rx_next=self.rx_next,
uart_rx_baud_tick=self.uart_rx_baud_tick,
uart_rx_baud_div=self.UART_RX_BAUD_DIV)
def _generate_vhdl(output_dir, width_addr, width_data, top_level_file_name, \
exp_reset_active):
toVHDL.std_logic_ports = True
toVHDL.name = os.path.splitext(top_level_file_name)[0]
toVHDL.directory = output_dir
toVHDL.use_clauses = \
'''
Library UNISIM;
use UNISIM.vcomponents.all;
use work.pck_myhdl_090.all;
'''
spec = ControllerSpec(width_addr, width_data)
clk = Signal(False)
reset = ResetSignal(not _RESET_ACTIVE, active=_RESET_ACTIVE, async=False)
rx = Signal(False)
tx = Signal(False)
exp_addr = Signal(intbv(0)[width_addr:0])
exp_din = Signal(intbv(0)[width_data:0])
exp_dout = Signal(intbv(0)[width_data:0])
exp_wen = Signal(False)
exp_reset = Signal(False)
exp_clk = Signal(False)
exp_clk_en = Signal(False)
toVHDL(BoardComponent,
spec=spec,
clk=clk,
reset=reset,
rx=rx,
tx=tx,
exp_addr=exp_addr,
exp_data_write=exp_din,
exp_data_read=exp_dout,
exp_wen=exp_wen,
exp_reset=exp_reset,
exp_clk=exp_clk,
exp_clk_en=exp_clk_en,
exp_reset_active=exp_reset_active,
baudrate=_UART_BAUDRATE)
def setUp(self):
self.spec = ControllerSpec(self.WIDTH_ADDR, self.WIDTH_DATA)
#input signals
self.clk = Signal(False)
self.reset = ResetSignal(True, active=False, async=False)
self.start = Signal(False)
self.pause = Signal(False)
self.step = Signal(False)
#output signals
self.autonomous = Signal(False)
self.cycle_count = Signal(intbv(0)[self.spec.width_value:0])
self.exp_clk_en = Signal(False)
#instances
self.clockgen = ClockGen(self.clk, self.HALF_PERIOD)
self.cycle_control = ControllerCycleControl(spec=self.spec,
clk=self.clk, reset=self.reset, start=self.start,
pause=self.pause, step=self.step,
cycle_autonomous=self.autonomous,
cycle_count=self.cycle_count, exp_clk_en=self.exp_clk_en)
def test_parse(self):
spec = ControllerSpec(8, 8)
message = int('10101100110011110000', 2)
parsed_opcode = spec.parse_opcode(message)
self.assertEquals(parsed_opcode, int('1010', 2))
parsed_addr = spec.parse_addr(message)
self.assertEquals(parsed_addr, int('11001100', 2))
parsed_data = spec.parse_data(message)
self.assertEquals(parsed_data, int('11110000', 2))
parsed_value = spec.parse_value(message)
self.assertEquals(parsed_value, int('1100110011110000', 2))
def setUp(self):
self.spec = ControllerSpec(self.WIDTH_ADDR, self.WIDTH_DATA)
# Input signals
self.clk = Signal(False)
self.reset = ResetSignal(True, active=False, async=False)
self.message = Signal(intbv(0)[self.spec.width_message:0])
self.tx_fifo_full = Signal(False)
self.transmit_next = Signal(False)
# Output signals
self.tx_fifo_data_write = Signal(intbv(0)[8:0])
self.tx_fifo_enqueue = Signal(False)
self.ready = Signal(False)
self.clockgen = ClockGen(self.clk, self.HALF_PERIOD)
self.transmitter = MessageTransmitter(spec=self.spec, clk=self.clk,
reset=self.reset, tx_fifo_data_write=self.tx_fifo_data_write,
tx_fifo_full=self.tx_fifo_full,
tx_fifo_enqueue=self.tx_fifo_enqueue, message=self.message,
ready=self.ready, transmit_next=self.transmit_next)
def test_chr_start(self):
spec = ControllerSpec(8, 8)
self.assertEquals(spec.chr_start, 0x12)
class ControllerResponseComposeTestCase(TestCase):
WIDTH_ADDR = 32
WIDTH_DATA = 8
def setUp(self):
self.spec = ControllerSpec(self.WIDTH_ADDR, self.WIDTH_DATA)
#input signals
self.opcode_res = Signal(intbv(0)[self.spec.width_opcode:0])
self.addr = Signal(intbv(0)[self.spec.width_addr:0])
self.data = Signal(intbv(0)[self.spec.width_data:0])
self.nop = Signal(False)
self.tx_ready = Signal(False)
self.cycle_count = Signal(intbv(0)[self.spec.width_value:0])
# Output signals
self.tx_next = Signal(False)
self.tx_msg = Signal(intbv(0)[self.spec.width_message:0])
self.response_compose = ControllerResponseCompose(spec=self.spec,
opcode_res=self.opcode_res, addr=self.addr, data=self.data,
nop=self.nop, cycle_count=self.cycle_count,
tx_ready=self.tx_ready, tx_next=self.tx_next,
tx_msg=self.tx_msg)
def simulate(self, test_logic, duration=None):
sim = Simulation(self.response_compose, test_logic)
sim.run(duration, quiet=False)
def stop_simulation(self):
raise StopSimulation()
def assert_value_type_response(self, opcode_expected, value_expected):
opcode_actual = self.spec.parse_opcode(self.tx_msg.val)
value_actual = self.spec.parse_value(self.tx_msg.val)
self.assertEquals(opcode_actual, opcode_expected)
self.assertEquals(value_actual, value_expected)
def assert_addr_type_response(self, opcode_expected, addr_expected,
data_expected):
opcode_actual = self.spec.parse_opcode(self.tx_msg.val)
addr_actual = self.spec.parse_addr(self.tx_msg.val)
data_actual = self.spec.parse_data(self.tx_msg.val)
self.assertEquals(opcode_actual, opcode_expected)
self.assertEquals(addr_actual, addr_expected)
self.assertEquals(data_actual, data_expected)
def test_tx_next(self):
@instance
def test():
yield delay(1)
self.nop.next = True
self.tx_ready.next = False
yield delay(1)
self.assertFalse(self.tx_next)
self.nop.next = True
self.tx_ready.next = True
yield delay(1)
self.assertFalse(self.tx_next)
self.nop.next = False
self.tx_ready.next = False
yield delay(1)
self.assertFalse(self.tx_next)
self.nop.next = False
self.tx_ready.next = True
yield delay(1)
self.assertTrue(self.tx_next)
self.stop_simulation()
self.simulate(test)
def test_tx_msg(self):
@instance
def test():
self.nop.next = False
self.tx_ready.next = True
# read success
self.addr.next = 23
self.data.next = 3
self.opcode_res.next = self.spec.opcode_res_read_success
yield delay(10)
self.assert_addr_type_response(self.spec.opcode_res_read_success,
23, 3)
# read error
self.opcode_res.next = self.spec.opcode_res_read_error_mode
yield delay(1)
self.assert_addr_type_response(
self.spec.opcode_res_read_error_mode, 23, 0)
# write success
self.addr.next = 26
self.data.next = 6
self.opcode_res.next = self.spec.opcode_res_write_success
yield delay(10)
self.assert_addr_type_response(self.spec.opcode_res_write_success,
26, 6)
# read error
self.opcode_res.next = self.spec.opcode_res_write_error_mode
yield delay(1)
self.assert_addr_type_response(
self.spec.opcode_res_write_error_mode, 26, 0)
# reset success
self.opcode_res.next = self.spec.opcode_res_reset_success
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_reset_success, 0)
# Step success
self.cycle_count.next = 34523
self.opcode_res.next = self.spec.opcode_res_step_success
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_step_success, 34524)
# Step error
self.opcode_res.next = self.spec.opcode_res_step_error_mode
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_step_error_mode, 0)
# Start success
self.cycle_count.next = 3523
self.opcode_res.next = self.spec.opcode_res_start_success
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_start_success, 3523)
# Start error
self.opcode_res.next = self.spec.opcode_res_start_error_mode
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_start_error_mode, 0)
# Pause success
self.cycle_count.next = 823
self.opcode_res.next = self.spec.opcode_res_pause_success
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_pause_success, 823)
# Pause error
self.opcode_res.next = self.spec.opcode_res_pause_error_mode
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_pause_error_mode, 0)
# Status
self.cycle_count.next = 11823
self.opcode_res.next = self.spec.opcode_res_status
yield delay(1)
self.assert_value_type_response(
self.spec.opcode_res_status, 11823)
self.stop_simulation()
self.simulate(test)
def test_constructor(self):
with self.assertRaises(ValueError):
spec = ControllerSpec(0, 1)
with self.assertRaises(ValueError):
spec = ControllerSpec(1, 0)
class ControllerTestCase(TestCase):
HALF_PERIOD = 5
WIDTH_ADDR = 32
WIDTH_DATA = 8
MEM_INIT = {3: 4, 4: 5, 5: 6}
EXP_RESET_ACTIVE = False
def setUp(self):
self.spec = ControllerSpec(width_addr=self.WIDTH_ADDR,
width_data=self.WIDTH_DATA)
# Input signals
self.clk = Signal(False)
self.reset = ResetSignal(True, active=False, async=False)
self.rx_msg = Signal(intbv(0)[self.spec.width_message:0])
self.rx_ready = Signal(False)
self.tx_ready = Signal(True)
self.exp_data_read = Signal(intbv(0)[self.spec.width_data:0])
# Output signals
self.rx_next = Signal(False)
self.tx_msg = Signal(intbv(0)[self.spec.width_message:0])
self.tx_next = Signal(False)
self.exp_addr = Signal(intbv(0)[self.spec.width_addr:0])
self.exp_data_write = Signal(intbv(0)[self.spec.width_data:0])
self.exp_wen = Signal(False)
self.exp_reset = ResetSignal(not self.EXP_RESET_ACTIVE,
active=self.EXP_RESET_ACTIVE,
async=False)
self.exp_clk_en = Signal(False)
self.clockgen = ClockGen(clk=self.clk, half_period=self.HALF_PERIOD)
self.controller = Controller(spec=self.spec,
clk=self.clk,
reset=self.reset,
rx_msg=self.rx_msg,
rx_next=self.rx_next,
rx_ready=self.rx_ready,
tx_msg=self.tx_msg,
tx_next=self.tx_next,
tx_ready=self.tx_ready,
exp_addr=self.exp_addr,
exp_data_write=self.exp_data_write,
exp_data_read=self.exp_data_read,
exp_wen=self.exp_wen,
exp_reset=self.exp_reset,
exp_clk_en=self.exp_clk_en,
exp_reset_active=self.EXP_RESET_ACTIVE)
self.mock_experiment = MockExperimentSetup(
self.clk, self.reset, self.exp_addr, self.exp_data_write,
self.exp_data_read, self.exp_wen, self.exp_reset, self.exp_clk_en,
self.MEM_INIT)
def simulate(self, test_logic, duration=None):
sim = Simulation(self.clockgen, self.controller, self.mock_experiment,
*test_logic)
sim.run(duration, quiet=False)
def stop_simulation(self):
raise StopSimulation()
def assert_value_type_response(self, opcode_expected, value_expected):
opcode_actual = self.spec.parse_opcode(self.tx_msg)
value_actual = self.spec.parse_value(self.tx_msg)
self.assertEquals(opcode_actual, opcode_expected)
self.assertEquals(value_actual, value_expected)
def assert_addr_type_response(self, opcode_expected, address_expected,
data_expected):
opcode_actual = self.spec.parse_opcode(self.tx_msg)
addr_actual = self.spec.parse_addr(self.tx_msg)
data_actual = self.spec.parse_data(self.tx_msg)
self.assertEquals(opcode_actual, opcode_expected)
self.assertEquals(addr_actual, addr_expected)
self.assertEquals(data_actual, data_expected)
def test_reset(self):
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.assertFalse(self.rx_next)
self.assertFalse(self.tx_next)
self.assertEquals(self.exp_reset, self.EXP_RESET_ACTIVE)
self.assertFalse(self.exp_wen)
self.assertFalse(self.exp_clk_en)
yield self.clk.negedge
self.assertFalse(self.exp_clk_en)
yield self.clk.negedge
self.assertFalse(self.exp_clk_en)
self.stop_simulation()
self.simulate([test])
def test_cmd_read(self):
opcode = self.spec.opcode_cmd_read
cmd1 = self.spec.addr_type_message(opcode, 3, 0)
cmd2 = self.spec.addr_type_message(opcode, 4, 0)
expected1 = self.spec.addr_type_message(
self.spec.opcode_res_read_success, 3, 4)
expected2 = self.spec.addr_type_message(
self.spec.opcode_res_read_success, 4, 5)
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.reset.next = not self.reset.active
yield self.clk.negedge
self.assertFalse(self.tx_next)
self.rx_msg.next = cmd1
self.rx_ready.next = True
self.tx_ready.next = True
yield delay(1)
self.assertTrue(self.rx_next)
yield self.clk.negedge
self.assertEquals(self.tx_msg, expected1)
self.assertTrue(self.tx_next)
self.rx_msg.next = cmd2
self.rx_ready.next = True
yield delay(1)
self.assertTrue(self.rx_next)
yield self.clk.negedge
self.assertEquals(self.tx_msg, expected2)
self.assertTrue(self.tx_next)
self.rx_ready.next = False
yield self.clk.negedge
self.assertFalse(self.tx_next)
self.stop_simulation()
self.simulate([test])
def test_cmd_write(self):
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.reset.next = not self.reset.active
self.rx_ready.next = True
self.rx_msg.next = self.spec.addr_type_message(
self.spec.opcode_cmd_write, 88, 9)
self.tx_ready.next = True
yield delay(1)
self.assertTrue(self.rx_next)
self.assertTrue(self.exp_wen)
self.assertEquals(self.exp_addr, 88)
yield self.clk.negedge
self.assertEquals(self.exp_data_read, 9)
self.assertTrue(self.tx_next)
self.assertEquals(self.exp_addr, 88)
self.rx_ready.next = False
yield delay(1)
self.assertFalse(self.rx_next)
self.assertFalse(self.exp_wen)
yield self.clk.negedge
self.assertFalse(self.tx_next)
self.stop_simulation()
self.simulate([test])
def test_cmd_reset(self):
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.reset.next = not self.reset.active
yield self.clk.negedge
self.assertEquals(self.exp_reset, not self.EXP_RESET_ACTIVE)
self.rx_msg.next = self.spec.value_type_message(
self.spec.opcode_cmd_reset, 0)
self.rx_ready.next = True
self.tx_ready.next = True
yield delay(1)
self.assertEquals(self.exp_reset, self.EXP_RESET_ACTIVE)
yield self.clk.negedge
self.assertEquals(
self.tx_msg,
self.spec.value_type_message(
self.spec.opcode_res_reset_success, 0))
self.stop_simulation()
self.simulate([test])
def test_cmd_step(self):
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.reset.next = not self.reset.active
self.rx_ready.next = False
self.tx_ready.next = True
yield self.clk.posedge
yield delay(1)
self.assertFalse(self.exp_clk_en)
self.rx_msg.next = self.spec.value_type_message(
self.spec.opcode_cmd_step, 0)
self.rx_ready.next = True
yield delay(1)
self.assertFalse(self.exp_clk_en)
yield self.clk.negedge
yield delay(1)
self.assertTrue(self.exp_clk_en)
self.assertFalse(self.tx_next)
yield self.clk.posedge
yield delay(1)
self.assertTrue(self.exp_clk_en)
self.assertTrue(self.tx_next)
self.rx_ready.next = False
yield self.clk.negedge
yield delay(1)
self.assertFalse(self.exp_clk_en)
self.stop_simulation()
self.simulate([test])
def test_cmd_start_pause(self):
@instance
def test():
self.reset.next = self.reset.active
yield self.clk.negedge
self.reset.next = not self.reset.active
self.rx_ready.next = False
self.tx_ready.next = True
self.stop_simulation()
self.simulate([test])
from myhdl import toVHDL, toVerilog, Signal, ResetSignal, intbv
from fpgaedu import ControllerSpec
from fpgaedu.hdl import (BaudGen, UartRx, UartTx, BaudGenRxLookup, Rom, Fifo,
Controller)
from fpgaedu.hdl import nexys4
from fpgaedu.hdl.testexperiment._experiment_setup import ExperimentSetup
# Instance constants
_CLK_FREQ = 100000000
_UART_BAUDRATE = 9600
_UART_RX_DIV = 16
_UART_DATA_BITS = 8
_UART_STOP_BITS = 1
_WIDTH_DATA = 8
_WIDTH_ADDR = 32
_SPEC = ControllerSpec(_WIDTH_ADDR, _WIDTH_DATA)
_EXP_RESET_ACTIVE = True
_WIDTH_COUNT = 8
# toVHDL() constants
_STD_LOGIC_PORTS = True
_OUTPUT_DIRECTORY = './vhdl/'
# Signals
_CLK = Signal(False)
_RESET = ResetSignal(True, active=False, async=False)
_ENABLE = Signal(False)
_COUNT = Signal(intbv()[_WIDTH_COUNT:0])
_UART_RX = Signal(False)
class FpgaEduShell(cmd.Cmd):
intro = 'Welcome to the fpgaedu shell'
prompty = '(fpgaedu)'
connection = None
spec = ControllerSpec(1, 8)
def do_list_ports(self, arg):
ports = comports()
if len(ports) <= 0:
print('no com ports found on system')
for port in ports:
print(port.name)
def postloop(self):
self.do_disconnect()
def do_connect(self, arg):
try:
self.connection = serial.Serial(arg, baudrate=BAUDRATE)
print('Started connection')
except serial.SerialException:
try:
self.connection = serial.Serial('/dev/' + arg,
baudrate=BAUDRATE)
except serial.SerialException:
print('Unable to open the specified port')
def do_disconnect(self, arg):
if self.connection is serial.Serial:
self.connection.close()
del self.connection
def do_read(self, arg):
readparser = FpgaEduArgumentParser()
readparser.add_argument('addr', type=int)
try:
n = readparser.parse_args(arg.split())
except FpgaEduArgumentError as err:
return
self.write_addr_type_cmd(self.spec.opcode_cmd_read, n.addr, 0)
self.read_res()
def do_write(self, arg):
writeparser = FpgaEduArgumentParser()
writeparser.add_argument('addr', type=int)
writeparser.add_argument('data', type=int)
try:
n = writeparser.parse_args(arg.split())
except FpgaEduArgumentError as err:
return
self.write_addr_type_cmd(self.spec.opcode_cmd_write, n.addr, n.data)
self.read_res()
pass
def do_reset(self, arg):
self.write_value_type_cmd(self.spec.opcode_cmd_reset, 0)
self.read_res()
def do_step(self, arg):
self.write_value_type_cmd(self.spec.opcode_cmd_step, 0)
self.read_res()
def do_start(self, arg):
self.write_value_type_cmd(self.spec.opcode_cmd_start, 0)
self.read_res()
def do_pause(self, arg):
self.write_value_type_cmd(self.spec.opcode_cmd_pause, 0)
self.read_res()
def do_status(self, arg):
self.write_value_type_cmd(self.spec.opcode_cmd_status, 0)
self.read_res()
def write_addr_type_cmd(self, opcode, addr, data):
cmd = struct.pack('>BBIBB', self.spec.chr_start, opcode, addr, data,
self.spec.chr_stop)
print('sending address-type command')
print(repr(cmd))
self.connection.write(cmd)
def write_value_type_cmd(self, opcode, value):
cmd = struct.pack('>BBIBB', self.spec.chr_start, opcode, 0, value,
self.spec.chr_stop)
print('sending value-type command')
print(repr(cmd))
self.connection.write(cmd)
def read_res(self):
message = [None for i in range(6)]
if self.connection:
self.connection.timeout = 0.1
esc = False
message = bytes(0)
#read start byte
while True:
res = self.connection.read(1)
if not esc and res == bytes([self.spec.chr_start]):
break
if not esc and res == bytes([self.spec.chr_esc]):
esc = True
else:
esc = False
#read message bytes
while True:
res = self.connection.read(1)
if not esc and res == bytes([self.spec.chr_start]):
message = bytes(0)
elif not esc and res == bytes([self.spec.chr_stop]):
break
else:
message += res
if not esc and res == bytes([self.spec.chr_esc]):
esc = True
else:
esc = False
print(repr(message))
opcode = int.from_bytes(message[0:1], byteorder='big')
addr = int.from_bytes(message[1:5], byteorder='big')
data = int.from_bytes(message[5:6], byteorder='big')
value = int.from_bytes(message[1:6], byteorder='big')
if opcode == self.spec.opcode_res_read_success:
print('read success: addr=%s, data=%s' % (addr, data))
elif opcode == self.spec.opcode_res_read_error_mode:
print('read error: controller in autonomous mode')
elif opcode == self.spec.opcode_res_write_success:
print('write success: addr=%s, data=%s' % (addr, data))
elif opcode == self.spec.opcode_res_write_error_mode:
print('write error: controller in autonomous mode')
elif opcode == self.spec.opcode_res_reset_success:
print('reset success')
elif opcode == self.spec.opcode_res_step_success:
print('step success: cycle count=%s' % value)
elif opcode == self.spec.opcode_res_step_error_mode:
print('step error: controller in autonomous mode')
elif opcode == self.spec.opcode_res_start_success:
print('start success: cycle count at start=%s' % value)
elif opcode == self.spec.opcode_res_start_error_mode:
print('start error: already in autonomous mode')
elif opcode == self.spec.opcode_res_pause_success:
print('pause success: cycle_count=%s' % value)
elif opcode == self.spec.opcode_res_pause_error_mode:
print('pause error: already in manual mode')
elif opcode == self.spec.opcode_res_status:
print('status: cycle count=%s' % value)
else:
print('unable to read response: not connected')
def test_chr_esc(self):
spec = ControllerSpec(8, 8)
self.assertEquals(spec.chr_esc, 0x7D)
def test_chr_stop(self):
spec = ControllerSpec(8, 8)
self.assertEquals(spec.chr_stop, 0x13)
