예제 #1
0
 def createCircuit(self, prs, input, output):
     self.prs = prs
     print "======== Creating Circuit Structure ==========="
     print "IO_LIST: ", input, output
     self.internals = []
     self.circuitDict = self.getSignalDict(prs)
     for line in prs:
         print "LineExpr : ", line
         line = func.trim(
             func.concatList(
                 func.concatList(
                     func.concatList(
                         line.split('#')[0:]).split('[')[1]).split(']')[0]))
         print "Line: ", line
         signalName = self.getSignalName(line)
         print 'Signal :', signalName
         if ('+' in line):
             self.circuitDict[signalName]['SET'].append(
                 self.getExprList(line))
         elif ('-' in line):
             self.circuitDict[signalName]['RESET'].append(
                 self.getExprList(line))
         else:
             self.circuitDict[signalName]['COMB'].append(
                 self.getExprList(line))
         if (signalName not in input and signalName not in output
                 and signalName not in self.internals):
             self.internals.append(signalName)
     for i, v in self.circuitDict.iteritems():
         for j, k in v.iteritems():
             print 'SignalDict  :', i, j, k
예제 #2
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	def getSignalDict(self, prs):
		circuitDict = dict([])
		for line in prs:
			print 'line:', line
			line = func.trim(func.concatList(func.concatList(func.concatList(line.split('#')[0:]).split('[')[1]).split(']')[0]))
			print 'line:', line
			signalName = self.getSignalName(line)
			circuitDict[signalName] = {'SET': [], 'RESET': [], 'COMB':[]}			
		return circuitDict
예제 #3
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 def getSignalDict(self, prs):
     circuitDict = dict([])
     for line in prs:
         print 'line:', line
         line = func.trim(
             func.concatList(
                 func.concatList(
                     func.concatList(
                         line.split('#')[0:]).split('[')[1]).split(']')[0]))
         print 'line:', line
         signalName = self.getSignalName(line)
         circuitDict[signalName] = {'SET': [], 'RESET': [], 'COMB': []}
     return circuitDict
예제 #4
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 def getFanInList(self, sig):
     FI = []
     for i, v in self.circuitDict[sig].iteritems():
         for j in v:
             #print 'from circuitDict :', j, v
             for k in j:
                 if ('~' in k):
                     #print 'True'
                     dum_sig = func.concatList(k.split('~')[1])
                 else:
                     dum_sig = k
                 if (dum_sig not in FI):
                     FI.append(dum_sig)
     return FI
예제 #5
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	def getFanInList( self, sig ):
		FI = []
		for i, v in self.circuitDict[sig].iteritems():
			for j in v :
				#print 'from circuitDict :', j, v
				for k in j:
					if('~' in k):
						#print 'True'
						dum_sig = func.concatList(k.split('~')[1])
					else:
						dum_sig = k 
					if(dum_sig not in FI):
						FI.append(dum_sig)
		return FI
예제 #6
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	def createCircuit(self, prs, input, output):
		self.prs = prs
		print "======== Creating Circuit Structure ==========="
		print "IO_LIST: " , input, output
		self.internals=[]
		self.circuitDict = self.getSignalDict(prs)
		for line in prs:
			print "LineExpr : ", line
			line = func.trim(func.concatList(func.concatList(func.concatList(line.split('#')[0:]).split('[')[1]).split(']')[0]))
			print "Line: ", line
			signalName = self.getSignalName(line)
			print 'Signal :', signalName
			if('+' in line):
				self.circuitDict[signalName]['SET'].append(self.getExprList(line))
			elif('-' in line):
				self.circuitDict[signalName]['RESET'].append(self.getExprList(line))
			else:
				self.circuitDict[signalName]['COMB'].append(self.getExprList(line))		
			if(signalName not in input  and signalName not in output and signalName not in self.internals):
				self.internals.append(signalName)
		for i,v in self.circuitDict.iteritems():
			for j, k in v.iteritems():
				print 'SignalDict  :', i, j, k
예제 #7
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 def cktFanInList(self, sig):
     fiList = []
     if (sig in self.nodeSet):  ## internaly created signal
         FI = self.nodeSet[sig][1]
         dum_sig = ''
         for i in FI:
             if ('~' in i):
                 dum_sig = func.concatList(i.split('~')[1])
             else:
                 dum_sig = i
             if (dum_sig not in fiList):
                 fiList.append(dum_sig)
     else:
         for i, v in self.circuitStruct[sig].iteritems():
             for j in v.keys():
                 if (j not in fiList):
                     fiList.append(j)
     return fiList
예제 #8
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	def cktFanInList( self, sig):
		fiList = []
		if(sig in self.nodeSet): ## internaly created signal
			FI = self.nodeSet[sig][1]
			dum_sig = ''
			for i in FI:
				if('~' in i):
					dum_sig = func.concatList(i.split('~')[1])
				else:
					dum_sig = i
				if(dum_sig not in fiList):
					fiList.append(dum_sig)
		else:
			for i, v in self.circuitStruct[sig].iteritems():
				for j in v.keys():
					if(j not in fiList):
						fiList.append(j)
		return fiList
예제 #9
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    def verifyCge(self, inputs, outputs, internals, init_state, sgList, sgl):
        self.inputs = inputs
        self.outputs = outputs
        #self.internals = internals
        print 'self:', self.internals
        for i in internals:
            if (i not in self.internals):
                self.internals.append(i)
        print 'self2:', self.internals
        self.init_state = init_state
        retResult = dict([])
        for i in self.internals:
            self.init_state[
                i] = '0'  ## this is an assumption that initially all internal signals are zero
        print 'New init state:', self.init_state
        self.allSignals = inputs + outputs + self.internals
        self.outputsExt = dict([])
        self.extSignals = inputs + outputs
        self.outSignals = outputs + self.internals
        self.StateSequence = self.getStateSequence(sgl)
        self.currentState = dict([])
        implState = dict([])
        #for pre, post in self.StateSequence.iteritems():
        #	print 'PRE: ', pre+'   ', post
        implSG = self.find_implSG(sgList, sgl)
        print 'Result of impl:', implSG[0]
        if (len(implSG) == 1):
            return 'DeadLock'
        print "============ FAILSTATE ================"
        for i, v in implSG[2].iteritems():
            print i, ': ==> :', v, '\n'
        print "============ TRANSSET =================\n\n"
        for i in implSG[1]:
            print 'here: ', i
        implState = dict([])
        vecDict = dict([])
        cgeDict = dict([])
        implSet = implSG[1]
        for i in implSG[1]:
            #print i[0], '  :  ',i[1],'  :  ',i[2]
            for j in range(0, len(self.allSignals)):
                implState[self.allSignals[j]] = i[0][j]
            print 'ImplState: ', implState
            if (tuple(i[0]) not in vecDict):
                vecDict[tuple(i[0])] = implState
            if (len(self.getExcitedSignals(implState, 1).keys()) != 0):
                retResult = self.extend_state(implState)
                print 'Got external excitations:', implState
                if (tuple(i[0]) not in cgeDict):
                    print 'noMatch :', retResult, tuple(i[0])
                    cgeDict[tuple(i[0])] = retResult
            else:
                retResult['noExcitation'] = 1
                #for k in self.outputs:
                #retResult[k] = implState[k]
                #retResult[k] = 0
            #print 'RetResult: ', retResult

        for i, v in cgeDict.iteritems():
            print '================ CGE_DICT ======================'
            print i, '   ', v
            print '=============== end cge dict ==================='

        for keyset, valset in self.StateSequence.iteritems():
            s = keyset
            sigTransList = []
            print 'key:', keyset, '\nval:', valset
            for el in valset:
                if ('+' in el[0]):
                    sigTransList.append(el[0].split('+')[0])
                elif ('-' in el[0]):
                    sigTransList.append(el[0].split('-')[0])
                else:
                    sigTransList.append(el[0])
            print 'MakesigTransList:', sigTransList
            print '\n state', keyset
            for i in cgeDict.keys():
                print '\ncgedictKeys', i
                s = func.concatList(i)[0:len(keyset)]
                print 'Concat string:', s
                if (keyset == func.concatList(i)[0:len(keyset)]):
                    ###---- Match the output signals ------
                    for sigout in self.outputs:
                        print '\n keyset', keyset, sigout, cgeDict[i]
                        if (sigout not in sigTransList
                                and sigout not in cgeDict[i]):
                            print 'Mark PassVacuous:', sigout
                            print 'sigTransList:', sigTransList
                        elif (sigout not in sigTransList
                              and sigout in cgeDict[i]):
                            print 'Mark Fail', sigout
                            print 'cgeDict', cgeDict[i]
                            print 'sigTransList:', sigTransList
                        elif (sigout in sigTransList
                              and sigout not in cgeDict[i]):
                            print 'Mark Fail', sigout, cgeDict[i]
                            print 'cgeDict', cgeDict[i]
                            print 'sigTransList:', sigTransList
                        elif (sigout in sigTransList and sigout in cgeDict[i]):
                            print 'Mark Pass', sigout
                            print 'sigTransList:', sigTransList
                else:
                    print 'Unable to match', keyset

        self.reverifyCge_and_stabeStates(inputs, outputs, internals,
                                         init_state, sgList, sgl)
예제 #10
0
	def verifyCge( self, inputs, outputs, internals, init_state, sgList, sgl ):
		self.inputs = inputs
		self.outputs = outputs
		#self.internals = internals
		print 'self:', self.internals
		for i in internals:
			if(i not in self.internals):
				self.internals.append(i)
		print 'self2:', self.internals
		self.init_state = init_state
		retResult = dict([])
		for i in self.internals:
			self.init_state[i] = '0' ## this is an assumption that initially all internal signals are zero
		print 'New init state:', self.init_state
		self.allSignals = inputs+outputs+self.internals
		self.outputsExt = dict([])
		self.extSignals = inputs+outputs
		self.outSignals = outputs+self.internals
		self.StateSequence = self.getStateSequence(sgl)
		self.currentState = dict([])
		implState = dict([])
		#for pre, post in self.StateSequence.iteritems():
		#	print 'PRE: ', pre+'   ', post
		implSG = self.find_implSG( sgList, sgl );
		print 'Result of impl:', implSG[0]
		if(len(implSG)==1):
			return 'DeadLock'
		print "============ FAILSTATE ================"
		for i, v in implSG[2].iteritems():
			print i, ': ==> :',v, '\n'
		print "============ TRANSSET =================\n\n"
		for i in implSG[1]:
			print 'here: ', i
		implState = dict([])
		vecDict = dict([])
		cgeDict = dict([])
		implSet = implSG[1]
		for i in implSG[1]:
			#print i[0], '  :  ',i[1],'  :  ',i[2]
			for j in range(0,len(self.allSignals)):
				implState[self.allSignals[j]] = i[0][j]
			print 'ImplState: ', implState
			if(tuple(i[0]) not in vecDict):
				vecDict[tuple(i[0])] = implState
			if(len(self.getExcitedSignals(implState,1).keys())!=0):
				retResult = self.extend_state(implState)
				print 'Got external excitations:', implState
				if( tuple(i[0]) not in cgeDict):
					print 'noMatch :', retResult, tuple(i[0])
					cgeDict[tuple(i[0])] = retResult
			else:
				retResult['noExcitation']=1
				#for k in self.outputs:
					#retResult[k] = implState[k]
					#retResult[k] = 0
			#print 'RetResult: ', retResult

					
		for i, v in cgeDict.iteritems():
			print '================ CGE_DICT ======================'
			print i, '   ', v
			print '=============== end cge dict ==================='
			
		
		for keyset, valset in self.StateSequence.iteritems():
			s = keyset
			sigTransList = []
			print 'key:' , keyset, '\nval:', valset
			for el in valset:
				if('+' in el[0]):
					sigTransList.append(el[0].split('+')[0])
				elif('-' in el[0]):
					sigTransList.append(el[0].split('-')[0])
				else:
					sigTransList.append(el[0])
			print 'MakesigTransList:', sigTransList
			print '\n state', keyset
			for i in cgeDict.keys():
				print '\ncgedictKeys', i
				s = func.concatList(i)[0:len(keyset)]
				print 'Concat string:', s
				if(keyset == func.concatList(i)[0:len(keyset)]):
					###---- Match the output signals ------
					for sigout in self.outputs:
						print '\n keyset', keyset, sigout, cgeDict[i]
						if(sigout not in sigTransList  and sigout not in cgeDict[i]):
							print 'Mark PassVacuous:',sigout
							print 'sigTransList:', sigTransList
						elif(sigout not in sigTransList and sigout in cgeDict[i]):
							print 'Mark Fail', sigout
							print 'cgeDict', cgeDict[i]
							print 'sigTransList:', sigTransList
						elif(sigout in sigTransList and sigout not in cgeDict[i]):
							print 'Mark Fail', sigout, cgeDict[i]
							print 'cgeDict', cgeDict[i]
							print 'sigTransList:', sigTransList
						elif(sigout in sigTransList and sigout in cgeDict[i]):
							print 'Mark Pass', sigout
							print 'sigTransList:', sigTransList
				else:
					print 'Unable to match', keyset
					
		self.reverifyCge_and_stabeStates( inputs, outputs, internals, init_state, sgList, sgl)