예제 #1
0
파일: opencores.py 프로젝트: Limb/fusesoc
    def fetch(self, local_dir, core_name):
        logger.debug('fetch() *Entered*')
        status = self.status(local_dir)

        if status == 'empty':
            try:
                self._checkout(local_dir)
                return True
            except RuntimeError:
                raise
        elif status == 'modified':
            self.clean_cache()
            try:
                self._checkout(local_dir)
                return True
            except RuntimeError:
                raise
        elif status == 'outofdate':
            self._update()
            return True
        elif status == 'downloaded':
            return False
        else:
            pr_warn("Provider status is: '" + status + "'. This shouldn't happen")
            return False
예제 #2
0
파일: core.py 프로젝트: tmd-set/fusesoc
    def export(self, dst_dir):
        if os.path.exists(dst_dir):
            shutil.rmtree(dst_dir)

        src_dir = self.files_root

        #FIXME: Separate tb_files to an own directory tree (src/tb/core_name ?)
        src_files = []

        for s in section.SECTION_MAP:
            obj = getattr(self, s)
            if obj:
                src_files += obj.export()

        dirs = list(set(map(os.path.dirname,src_files)))
        for d in dirs:
            if not os.path.exists(os.path.join(dst_dir, d)):
                os.makedirs(os.path.join(dst_dir, d))

        for f in src_files:
            if(os.path.exists(os.path.join(src_dir, f))):
                shutil.copyfile(os.path.join(src_dir, f), 
                                os.path.join(dst_dir, f))
            else:
                utils.pr_warn('File %s does not exist' %
                        os.path.join(src_dir, f))
예제 #3
0
    def _write_tcl_file(self):
        tcl_file = open(os.path.join(self.work_root, self.system.name+'.tcl'),'w')
        tcl_file.write("project_new " + self.system.name + " -overwrite\n")
        tcl_file.write("set_global_assignment -name FAMILY " + self.system.backend.family + '\n')
        tcl_file.write("set_global_assignment -name DEVICE " + self.system.backend.device + '\n')
        # default to 'orpsoc_top' if top_module entry is missing
        top_module = 'orpsoc_top'
        if self.system.backend.top_module:
            top_module = self.system.backend.top_module
        tcl_file.write("set_global_assignment -name TOP_LEVEL_ENTITY " + top_module + '\n')

        for key, value in self.vlogparam.items():
            tcl_file.write("set_parameter -name {} {}\n".format(key, value))
        (src_files, incdirs) = self._get_fileset_files(['synth', 'quartus'])

        for f in src_files:
            if f.file_type in ["verilogSource",
		               "verilogSource-95",
                               "verilogSource-2001",
		               "verilogSource-2005"]:
                _type = 'VERILOG_FILE'
            elif f.file_type in ["systemVerilogSource",
			         "systemVerilogSource-3.0",
			         "systemVerilogSource-3.1",
			         "systemVerilogSource-3.1a"]:
                _type = 'SYSTEMVERILOG_FILE'
            elif f.file_type in ['vhdlSource',
                                 'vhdlSource-87',
                                 'vhdlSource-93',
                                 'vhdlSource-2008']:
                _type = 'VHDL_FILE'
            else:
                _type = None
                _s = "{} has unknown file type '{}'"
                utils.pr_warn(_s.format(f.name,
                                  f.file_type))
            if _type:
                _s = "set_global_assignment -name {} {}\n"
                tcl_file.write(_s.format(_type,
                                         f.name))

        for include_dir in incdirs:
            tcl_file.write("set_global_assignment -name SEARCH_PATH " + include_dir + '\n')

        for f in self.system.backend.sdc_files:
            dst_dir = os.path.join(self.src_root, self.system.name)
            sdc_file = os.path.relpath(os.path.join(dst_dir, f.name) , self.work_root)
            tcl_file.write("set_global_assignment -name SDC_FILE " + sdc_file + '\n')

        # NOTE: The relative path _have_ to be used here, if the absolute path
        # is used, quartus_asm will fail with an error message that
        # sdram_io.pre.h can't be read or written.
        for f in self.qip_files:
            tcl_file.write("set_global_assignment -name QIP_FILE " +
                           os.path.relpath(f, self.work_root) + '\n')

        tcl_files = self.system.backend.tcl_files
        for f in tcl_files:
            tcl_file.write(open(os.path.join(self.system_root, f.name)).read())
        tcl_file.close()
예제 #4
0
파일: ghdl.py 프로젝트: andrzej-r/fusesoc
    def build(self):
        super(Ghdl, self).build()

        (src_files, incdirs) = self._get_fileset_files(['sim', 'ghdl'])

        cmd = 'ghdl'
        for f in src_files:
            args = ['-a']
            args += self.analyze_options[:]
            _supported = True
            if not f.logical_name:
                f.logical_name = 'work'
            if f.file_type == "vhdlSource":
                pass
            elif f.file_type == "vhdlSource-87":
                args += ['--std=87']
            elif f.file_type == "vhdlSource-93":
                args += ['--std=93']
            elif f.file_type == "vhdlSource-2008":
                args += ['--std=08']
            else:
                _s = "{} has unknown file type '{}'"
                pr_warn(_s.format(f.name,
                                  f.file_type))
                _supported = False
            if _supported:
                args += ['--work='+f.logical_name]
                args += [f.name]
                Launcher(cmd, args,
                         cwd      = self.sim_root,
                         errormsg = "Failed to analyze {}".format(f.name)).run()
예제 #5
0
파일: main.py 프로젝트: hoangt/fusesoc
def run(args):
    cm = CoreManager()
    config = Config()
    for cores_root in [config.cores_root,
                       config.systems_root,
                       args.cores_root]:
        try:
            cm.add_cores_root(cores_root)
        except (RuntimeError, IOError) as e:
            pr_warn("Failed to register cores root '{}'".format(str(e)))
    # Process global options
    if vars(args)['32']:
        config.archbits = 32
        logger.debug("Forcing 32-bit mode")
    elif vars(args)['64']:
        config.archbits = 64
        logger.debug("Forcing 64-bit mode")
    else:
        config.archbits = 64 if platform.architecture()[0] == '64bit' else 32
        logger.debug("Autodetected " + str(config.archbits) + "-bit mode")
    config.monochrome = vars(args)['monochrome']
    if config.monochrome:
        logger.debug("Monochrome output")
    else:
        logger.debug("Colorful output")
    config.verbose = vars(args)['verbose']
    if config.verbose:
        logger.debug("Verbose output")
    else:
        logger.debug("Concise output")
    # Run the function
    args.func(args)
예제 #6
0
파일: xsim.py 프로젝트: fjullien/fusesoc
    def _write_config_files(self):
        xsim_file = 'xsim.prj'
        f1 = open(os.path.join(self.sim_root,xsim_file),'w')
        self.incdirs = set()
        src_files = []

        (src_files, self.incdirs) = self._get_fileset_files(['sim', 'xsim'])
        for src_file in src_files:
            if src_file.file_type in ["verilogSource",
		                      "verilogSource-95",
		                      "verilogSource-2001"]:
                f1.write('verilog work ' + src_file.name + '\n')
            elif src_file.file_type in ["vhdlSource",
                                        "vhdlSource-87",
                                        "vhdlSource-93"]:
                f1.write('vhdl work ' + src_file.logical_name + " " + src_file.name + '\n')
            elif src_file.file_type in ['vhdlSource-2008']:
                f1.write('vhdl2008 ' + src_file.logical_name + " " + src_file.name + '\n')
            elif src_file.file_type in ["systemVerilogSource",
                                        "systemVerilogSource-3.0",
                                        "systemVerilogSource-3.1",
                                        "systemVerilogSource-3.1a",
                                        "verilogSource-2005"]:
                f1.write('sv work ' + src_file.name + '\n')
            else:
                _s = "{} has unknown file type '{}'"
                pr_warn(_s.format(src_file.name,
                                  src_file.file_type))
        f1.close()

        tcl_file = 'xsim.tcl'
        f2 = open(os.path.join(self.sim_root,tcl_file),'w')
        f2.write('add_wave -radix hex /\n')
        f2.write('run all\n')
        f2.close()
예제 #7
0
파일: core.py 프로젝트: Limb/fusesoc
    def export(self, dst_dir):
        logger.debug('export() *Entered*')
        logger.debug("  name="+self.name)
        if os.path.exists(dst_dir):
            shutil.rmtree(dst_dir)

        src_dir = self.files_root

        #FIXME: Separate tb_files to an own directory tree (src/tb/core_name ?)
        src_files = []
        if self.verilog:
            src_files += self.verilog.export()
        if self.vpi:
            src_files += self.vpi.export()
        if self.verilator:
            src_files += self.verilator.export()
        if self.vhdl:
            src_files += self.vhdl.export()

        dirs = list(set(map(os.path.dirname,src_files)))
        logger.debug("export src_files=" + str(src_files))
        logger.debug("export dirs=" + str(dirs))
        for d in dirs:
            if not os.path.exists(os.path.join(dst_dir, d)):
                os.makedirs(os.path.join(dst_dir, d))

        for f in src_files:
            if(os.path.exists(os.path.join(src_dir, f))):
                shutil.copyfile(os.path.join(src_dir, f), 
                                os.path.join(dst_dir, f))
            else:
                pr_warn("File " + os.path.join(src_dir, f) + " doesn't exist")
        logger.debug('export() -Done-')
예제 #8
0
파일: icarus.py 프로젝트: hoangt/fusesoc
    def _write_config_files(self):
        icarus_file = 'icarus.scr'

        f = open(os.path.join(self.sim_root,icarus_file),'w')

        incdirs = set()
        src_files = []

        (src_files, incdirs) = self._get_fileset_files(['sim', 'icarus'])
        for id in incdirs:
            f.write("+incdir+" + id+'\n')
        for src_file in src_files:
            if src_file.file_type in ["verilogSource",
		                      "verilogSource-95",
		                      "verilogSource-2001",
		                      "verilogSource-2005",
                                      "systemVerilogSource",
			              "systemVerilogSource-3.0",
			              "systemVerilogSource-3.1",
			              "systemVerilogSource-3.1a"]:
                f.write(src_file.name+'\n')
            else:
                _s = "{} has unknown file type '{}'"
                pr_warn(_s.format(src_file.name,
                                  src_file.file_type))

        f.close()
예제 #9
0
파일: core.py 프로젝트: horos/fusesoc
    def export(self, dst_dir):
        if os.path.exists(dst_dir):
            shutil.rmtree(dst_dir)

        src_dir = self.files_root

        #FIXME: Separate tb_files to an own directory tree (src/tb/core_name ?)
        src_files = []
        if self.verilog:
            src_files += self.verilog.export()
        if self.vpi:
            src_files += self.vpi.export()
        if self.verilator:
            src_files += self.verilator.export()
        if self.vhdl:
            src_files += self.vhdl.export()

        dirs = list(set(map(os.path.dirname,src_files)))
        for d in dirs:
            if not os.path.exists(os.path.join(dst_dir, d)):
                os.makedirs(os.path.join(dst_dir, d))

        for f in src_files:
            if(os.path.exists(os.path.join(src_dir, f))):
                shutil.copyfile(os.path.join(src_dir, f), 
                                os.path.join(dst_dir, f))
            else:
                utils.pr_warn('File %s does not exist' %
                        os.path.join(src_dir, f))
예제 #10
0
파일: url.py 프로젝트: horos/fusesoc
    def fetch(self, local_dir, core_name):
        status = self.status(local_dir)
        if '----' in self.version:
            self.corename = core_name
        else:
            self.corename = self.version

        if status == 'empty':
            try:
                self._checkout(local_dir, self.corename)
                return True
            except RuntimeError:
                raise
        elif status == 'modified':
            self.clean_cache()
            try:
                self._checkout(local_dir, self.corename)
                return True
            except RuntimeError:
                raise
        elif status == 'outofdate':
            self._update()
            return True
        elif status == 'downloaded':
            return False
        else:
            pr_warn("Provider status is: '" + status + "'. This shouldn't happen")
            return False
예제 #11
0
파일: __init__.py 프로젝트: Limb/fusesoc
 def load_dict(self, items):
     for item in items:
         if item in self.lists:
             setattr(self, item, items.get(item).split())
         elif item in self.strings:
             setattr(self, item, items.get(item))
         else:
             pr_warn("Warning: Unknown item '{item}' in section '{section}'".format(item=item, section=self.name))
예제 #12
0
파일: modelsim.py 프로젝트: hoangt/fusesoc
    def _write_build_rtl_tcl_file(self, tcl_main):
        tcl_build_rtl  = open(os.path.join(self.sim_root, "fusesoc_build_rtl.tcl"), 'w')

        (src_files, incdirs) = self._get_fileset_files(['sim', 'modelsim'])
        vlog_include_dirs = ['+incdir+'+d for d in incdirs]

        libs = []
        for f in src_files:
            if not f.logical_name:
                f.logical_name = 'work'
            if not f.logical_name in libs:
                tcl_build_rtl.write("vlib {}\n".format(f.logical_name))
                libs.append(f.logical_name)
            if f.file_type in ["verilogSource",
		               "verilogSource-95",
		               "verilogSource-2001",
		               "verilogSource-2005"]:
                cmd = 'vlog'
                args = self.vlog_options[:]
                args += vlog_include_dirs
            elif f.file_type in ["systemVerilogSource",
			         "systemVerilogSource-3.0",
			         "systemVerilogSource-3.1",
			         "systemVerilogSource-3.1a"]:
                cmd = 'vlog'
                args = self.vlog_options[:]
                args += ['-sv']
                args += vlog_include_dirs
            elif f.file_type == 'vhdlSource':
                cmd = 'vcom'
                args = []
            elif f.file_type == 'vhdlSource-87':
                cmd = 'vcom'
                args = ['-87']
            elif f.file_type == 'vhdlSource-93':
                cmd = 'vcom'
                args = ['-93']
            elif f.file_type == 'vhdlSource-2008':
                cmd = 'vcom'
                args = ['-2008']
            elif f.file_type == 'tclSource':
                cmd = None
                tcl_main.write("do {}\n".format(f.name))
            elif f.file_type == 'user':
                cmd = None
            else:
                _s = "{} has unknown file type '{}'"
                pr_warn(_s.format(f.name,
                                  f.file_type))
                cmd = None
            if cmd:
                if not Config().verbose:
                    args += ['-quiet']
                args += ['-work', f.logical_name]
                args += [f.name]
                tcl_build_rtl.write("{} {}\n".format(cmd, ' '.join(args)))
예제 #13
0
파일: section.py 프로젝트: ptracton/fusesoc
def load_section(config, section_name, name='<unknown>'):
    cls = SECTION_MAP.get(section_name)
    if cls is None:
        return None

    items = config.get_section(section_name)
    section = cls(items)
    if section.warnings:
        for warning in section.warnings:
            pr_warn('Warning: %s in %s' % (warning, name))
    return section
예제 #14
0
 def load_core(self, name, file):
     if os.path.exists(file):
         try:
             self._cores[name] = Core(file)
             logger.debug("Adding core " + file)
         except SyntaxError as e:
             w = "Warning: Failed to parse " + file + ": " + e.msg
             print(w)
             logger.warning(w)
         except ImportError as e:
             pr_warn('Failed to register core "{}"  due to unknown provider: {}'.format(name, str(e)))
예제 #15
0
 def load_core(self, file):
     if os.path.exists(file):
         try:
             core = Core(file)
             self.db.add(core)
         except SyntaxError as e:
             w = "Failed to parse " + file + ": " + e.msg
             pr_warn(w)
             logger.warning(w)
         except ImportError as e:
             pr_warn('Failed to register "{}" due to unknown provider: {}'.format(file, str(e)))
예제 #16
0
 def load_dict(self, items):
     for item in items:
         if item in self._members:
             _type = self._members.get(item)['type']
             try:
                 setattr(self, item, _type(items.get(item)))
             except ValueError as e:
                 _s = "Invalid value '{}'. Allowed values are '{}'"
                 pr_warn(_s.format(', '.join(e.args[1]),
                                   ', '.join(e.args[2])))
                 setattr(self, item, _type(e.args[0]))
         else:
             self.warnings.append(
                     'Unknown item "%(item)s" in section "%(section)s"' % {
                         'item': item, 'section': self.TAG})
예제 #17
0
 def fetch(self):
     status = self.status()
     if status == 'empty':
         self._checkout(self.files_root)
         return True
     elif status == 'modified':
         self.clean_cache()
         self._checkout(self.files_root)
         return True
     elif status == 'outofdate':
         self._update()
         return True
     elif status == 'downloaded':
         pass
     else:
         pr_warn("Provider status is: '" + status + "'. This shouldn't happen")
         return False
예제 #18
0
파일: backend.py 프로젝트: fjullien/fusesoc
    def _export_backend_files(self):
        src_dir = self.system.system_root
        dst_dir = os.path.join(self.src_root, self.system.name)

        export_files = self.system.backend.export()
        dirs = list(set(map(os.path.dirname, export_files)))

        for d in dirs:
            if not os.path.exists(os.path.join(dst_dir, d)):
                os.makedirs(os.path.join(dst_dir, d))

        for f in export_files:
            if(os.path.exists(os.path.join(src_dir, f))):
                shutil.copyfile(os.path.join(src_dir, f),
                                os.path.join(dst_dir, f))
            else:
                pr_warn("File " + os.path.join(src_dir, f) + " doesn't exist")
예제 #19
0
파일: github.py 프로젝트: Limb/fusesoc
 def fetch(self, local_dir, core_name):
     status = self.status(local_dir)
     if status == 'empty':
         self._checkout(local_dir)
         return True
     elif status == 'modified':
         self.clean_cache()
         self._checkout(local_dir)
         return True
     elif status == 'outofdate':
         self._update()
         return True
     elif status == 'downloaded':
         pass
     else:
         pr_warn("Provider status is: '" + status + "'. This shouldn't happen")
         return False
예제 #20
0
파일: main.py 프로젝트: hoangt/fusesoc
def init(args):
    # Fix Python 2.x.
    global input
    try:
        input = raw_input
    except NameError:
        pass

    xdg_data_home = os.environ.get('XDG_DATA_HOME') or \
                     os.path.join(os.path.expanduser('~'), '.local', 'share')
    default_dir = default_dir=os.path.join(xdg_data_home, REPO_NAME)
    prompt = 'Directory to use for {} [{}] : '
    if args.y:
        cores_root = None
    else:
        cores_root = input(prompt.format(REPO_NAME, default_dir))
    if not cores_root:
        cores_root = default_dir
    if os.path.exists(cores_root):
        pr_warn("'{}' already exists".format(cores_root))
        #TODO: Check if it's a valid orspoc-cores repo
    else:
        pr_info("Initializing orpsoc-cores")
        args = ['clone', REPO_URI, cores_root]
        Launcher('git', args).run()

    xdg_config_home = os.environ.get('XDG_CONFIG_HOME') or \
                      os.path.join(os.path.expanduser('~'), '.config')
    config_file = os.path.join(xdg_config_home, 'fusesoc', 'fusesoc.conf')


    if os.path.exists(config_file):
        pr_warn("'{}' already exists".format(config_file))
        #TODO. Prepend cores_root to file if it doesn't exist
    else:
        pr_info("Writing configuration file to '{}'".format(config_file))
        if not os.path.exists(os.path.dirname(config_file)):
            os.makedirs(os.path.dirname(config_file))
        f = open(config_file,'w')
        f.write("[main]\n")
        f.write("cores_root = {}\n".format(cores_root))
    pr_info("FuseSoC is ready to use!")
예제 #21
0
def load_section(config, section_name, file_name='<unknown>'):
    tmp = section_name.split(' ')
    _type = tmp[0]
    if len(tmp) == 2:
        _name = tmp[1]
    else:
        _name = None
    cls = SECTION_MAP.get(_type)
    if cls is None:
        #Note: The following sections are not in section.py yet
        if not section_name in ['plusargs', 'simulator', 'provider']:
            pr_warn("Unknown section '{}' in '{}'".format(section_name, file_name))
        return None

    items = config.get_section(section_name)
    section = cls(items)
    if section.warnings:
        for warning in section.warnings:
            pr_warn('Warning: %s in %s' % (warning, file_name))
    if _name:
        return (section, _name)
    else:
        return section
예제 #22
0
파일: url.py 프로젝트: beans365/fusesoc
 def fetch(self):
     status = self.status()
     if status == 'empty':
         try:
             self._checkout(self.files_root, self.version)
             return True
         except RuntimeError:
             raise
     elif status == 'modified':
         self.clean_cache()
         try:
             self._checkout(self.files_root, self.version)
             return True
         except RuntimeError:
             raise
     elif status == 'outofdate':
         self._update()
         return True
     elif status == 'downloaded':
         return False
     else:
         pr_warn("Provider status is: '" + status + "'. This shouldn't happen")
         return False
예제 #23
0
파일: icarus.py 프로젝트: mwelling/fusesoc
    def _write_config_files(self):
        icarus_file = 'icarus.scr'

        f = open(os.path.join(self.work_root, icarus_file), 'w')

        incdirs = set()
        src_files = []

        (src_files, incdirs) = self._get_fileset_files(['sim', 'icarus'])
        for id in incdirs:
            f.write("+incdir+" + id + '\n')
        for src_file in src_files:
            if src_file.file_type in [
                    "verilogSource", "verilogSource-95", "verilogSource-2001",
                    "verilogSource-2005", "systemVerilogSource",
                    "systemVerilogSource-3.0", "systemVerilogSource-3.1",
                    "systemVerilogSource-3.1a"
            ]:
                f.write(src_file.name + '\n')
            else:
                _s = "{} has unknown file type '{}'"
                pr_warn(_s.format(src_file.name, src_file.file_type))

        f.close()
예제 #24
0
def load_section(config, section_name, file_name='<unknown>'):
    tmp = section_name.split(' ')
    _type = tmp[0]
    if len(tmp) == 2:
        _name = tmp[1]
    else:
        _name = None
    cls = SECTION_MAP.get(_type)
    if cls is None:
        #Note: The following sections are not in section.py yet
        if not section_name in ['plusargs', 'simulator', 'provider']:
            pr_warn("Unknown section '{}' in '{}'".format(
                section_name, file_name))
        return None

    items = config.get_section(section_name)
    section = cls(items)
    if section.warnings:
        for warning in section.warnings:
            pr_warn('Warning: %s in %s' % (warning, file_name))
    if _name:
        return (section, _name)
    else:
        return section
예제 #25
0
    def build(self):
        super(Modelsim, self).build()

        (src_files, incdirs) = self._get_fileset_files(['sim', 'modelsim'])
        logfile = os.path.join(self.sim_root, 'vlog.log')
        vlog_include_dirs = ['+incdir+' + d for d in incdirs]
        for f in src_files:
            if not f.logical_name:
                f.logical_name = 'work'
            if not os.path.exists(os.path.join(self.sim_root, f.logical_name)):
                Launcher(self.model_tech + '/vlib', [f.logical_name],
                         cwd=self.sim_root,
                         errormsg="Failed to create library '{}'".format(
                             f.logical_name)).run()

            if f.file_type in [
                    "verilogSource", "verilogSource-95", "verilogSource-2001",
                    "verilogSource-2005"
            ]:
                cmd = 'vlog'
                args = self.vlog_options[:]
                args += vlog_include_dirs
            elif f.file_type in [
                    "systemVerilogSource", "systemVerilogSource-3.0",
                    "systemVerilogSource-3.1", "systemVerilogSource-3.1a"
            ]:
                cmd = 'vlog'
                args = self.vlog_options[:]
                args += ['-sv']
                args += vlog_include_dirs
            elif f.file_type == 'vhdlSource':
                cmd = 'vcom'
                args = []
            elif f.file_type == 'vhdlSource-87':
                cmd = 'vcom'
                args = ['-87']
            elif f.file_type == 'vhdlSource-93':
                cmd = 'vcom'
                args = ['-93']
            elif f.file_type == 'vhdlSource-2008':
                cmd = 'vcom'
                args = ['-2008']
            else:
                _s = "{} has unknown file type '{}'"
                pr_warn(_s.format(f.name, f.file_type))
            if not Config().verbose:
                args += ['-quiet']
            args += ['-work', f.logical_name]
            args += [f.name]
            Launcher(
                os.path.join(self.model_tech, cmd),
                args,
                cwd=self.sim_root,
                errormsg=
                "Failed to compile simulation model. Compile log is available in "
                + logfile).run()

        for vpi_module in self.vpi_modules:
            objs = []
            for src_file in vpi_module['src_files']:
                args = []
                args += ['-c']
                args += ['-std=c99']
                args += ['-fPIC']
                args += ['-fno-stack-protector']
                args += ['-g']
                args += ['-m32']
                args += ['-DMODELSIM_VPI']
                args += ['-I' + self.model_tech + '/../include']
                args += ['-I' + s for s in vpi_module['include_dirs']]
                args += [src_file]
                Launcher('gcc',
                         args,
                         cwd=self.sim_root,
                         errormsg="Compilation of " + src_file +
                         "failed").run()

            object_files = [
                os.path.splitext(os.path.basename(s))[0] + '.o'
                for s in vpi_module['src_files']
            ]

            args = []
            args += ['-shared']
            args += ['-E']
            args += ['-melf_i386']
            args += ['-o', vpi_module['name']]
            args += object_files
            args += [s for s in vpi_module['libs']]
            Launcher('ld',
                     args,
                     cwd=self.sim_root,
                     errormsg="Linking of " + vpi_module['name'] +
                     " failed").run()
예제 #26
0
    def configure(self, args):
        super(Quartus, self).configure(args)

        with open(
                os.path.join(self.work_root,
                             self.system.sanitized_name + '.tcl'),
                'w') as tcl_file:
            tcl_file.write("project_new " + self.system.sanitized_name +
                           " -overwrite\n")
            tcl_file.write("set_global_assignment -name FAMILY " +
                           self.backend.family + '\n')
            tcl_file.write("set_global_assignment -name DEVICE " +
                           self.backend.device + '\n')
            tcl_file.write("set_global_assignment -name TOP_LEVEL_ENTITY " +
                           self.backend.top_module + '\n')

            for key, value in self.vlogparam.items():
                tcl_file.write("set_parameter -name {} {}\n".format(
                    key, value))
            (src_files,
             incdirs) = self._get_fileset_files(['synth', 'quartus'])

            qsys_files = []
            for f in src_files:
                if f.file_type in [
                        "verilogSource", "verilogSource-95",
                        "verilogSource-2001", "verilogSource-2005"
                ]:
                    _type = 'VERILOG_FILE'
                elif f.file_type in [
                        "systemVerilogSource", "systemVerilogSource-3.0",
                        "systemVerilogSource-3.1", "systemVerilogSource-3.1a"
                ]:
                    _type = 'SYSTEMVERILOG_FILE'
                elif f.file_type in [
                        'vhdlSource', 'vhdlSource-87', 'vhdlSource-93',
                        'vhdlSource-2008'
                ]:
                    _type = 'VHDL_FILE'
                elif f.file_type in ['QIP']:
                    _type = 'QIP_FILE'
                elif f.file_type in ['QSYS']:
                    #Each qsys file will be run through ip-generate, which will
                    #generate a qip file with the same name as the qsys file
                    #The qip will will be stored in work_root/qsys/name/name.qip
                    #Therefore we replace the qsys_file with the qip file here
                    _src_dir = os.path.dirname(f.name)
                    _name = os.path.basename(f.name).split('.qsys')[0]
                    _dst_dir = os.path.join('qsys', _name)

                    qsys_files.append((_src_dir, _dst_dir, _name))

                    f.name = os.path.join(_dst_dir, _name + '.qip')
                    _type = 'QIP_FILE'
                elif f.file_type in ['SDC']:
                    _type = 'SDC_FILE'
                elif f.file_type in ['tclSource']:
                    tcl_file.write("source {}\n".format(
                        f.name.replace('\\', '/')))
                    _type = None
                elif f.file_type in ['user']:
                    _type = None
                else:
                    _type = None
                    _s = "{} has unknown file type '{}'"
                    utils.pr_warn(_s.format(f.name, f.file_type))
                if _type:
                    _s = "set_global_assignment -name {} {}\n"
                    tcl_file.write(_s.format(_type, f.name.replace('\\', '/')))

            for include_dir in incdirs:
                tcl_file.write("set_global_assignment -name SEARCH_PATH " +
                               include_dir.replace('\\', '/') + '\n')

        with open(os.path.join(self.work_root, 'Makefile'), 'w') as makefile:
            makefile.write(self.MAKEFILE_TEMPLATE)

        with open(os.path.join(self.work_root, 'config.mk'), 'w') as config_mk:
            config_mk.write(
                self.CONFIG_MK_TEMPLATE.format(
                    design_name=self.system.sanitized_name,
                    quartus_options=self.backend.quartus_options))
            for qsys_file in qsys_files:
                config_mk.write(
                    self.QSYS_TEMPLATE.format(src_dir=qsys_file[0],
                                              dst_dir=qsys_file[1],
                                              name=qsys_file[2],
                                              family=self.backend.family,
                                              device=self.backend.device))
예제 #27
0
    def __init__(self, core_file=None, name=None, core_root=None):
        if core_file:
            basename = os.path.basename(core_file)
        self.depend = []
        self.simulators = []

        self.plusargs = None
        self.provider = None
        self.system   = None

        for s in section.SECTION_MAP:
            assert(not hasattr(self, s))
            if(section.SECTION_MAP[s].named):
                setattr(self, s, OrderedDict())
            else:
                setattr(self, s, None)

        self.core_root = os.path.dirname(core_file)
        self.files_root = self.core_root

        self.export_files = []
        if core_file:

            config = FusesocConfigParser(core_file)

            #FIXME : Make simulators part of the core object
            self.simulator        = config.get_section('simulator')

            for s in section.load_all(config, core_file):
                if type(s) == tuple:
                    _l = getattr(self, s[0].TAG)
                    _l[s[1]] = s[0]
                    setattr(self, s[0].TAG, _l)
                else:
                    setattr(self, s.TAG, s)

            if self.main.name:
                self.name = self.main.name
            else:
                self.name = basename.split('.core')[0]

            self.sanitized_name = self.name

            self.depend     = self.main.depend
            self.simulators = self.main.simulators

            self._collect_filesets()

            cache_root = os.path.join(Config().cache_root, self.sanitized_name)
            if config.has_section('plusargs'):
                utils.pr_warn("plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters in " + str(self.name))
                self.plusargs = Plusargs(dict(config.items('plusargs')))
            if config.has_section('provider'):
                items    = dict(config.items('provider'))

                provider_name = items.get('name')
                if provider_name is None:
                    raise RuntimeError('Missing "name" in section [provider]')
                try:
                    provider_module = importlib.import_module(
                            'fusesoc.provider.%s' % provider_name)
                    self.provider = provider_module.PROVIDER_CLASS(self.name,
                        items, self.core_root, cache_root)
                except ImportError:
                    raise
            if self.provider:
                self.files_root = self.provider.files_root

            # We need the component file here, but it might not be
            # available until the core is fetched. Try to fetch first if any
            # of the component files are missing
            if False in [os.path.exists(f) for f in self.main.component]:
                self.setup()

            for f in self.main.component:
                self._parse_component(os.path.join(self.files_root, f))

            system_file = os.path.join(self.core_root, basename.split('.core')[0]+'.system')
            if os.path.exists(system_file):
                self.system = System(system_file)
        else:
            self.name = name
            self.provider = None
예제 #28
0
    def build(self):
        super(Modelsim, self).build()

        (src_files, incdirs) = self._get_fileset_files(['sim', 'modelsim'])
        logfile = os.path.join(self.sim_root, 'vlog.log')
        vlog_include_dirs = ['+incdir+'+d for d in incdirs]
        for f in src_files:
            if not f.logical_name:
                f.logical_name = 'work'
            if not os.path.exists(os.path.join(self.sim_root, f.logical_name)):
                Launcher(self.model_tech+'/vlib', [f.logical_name],
                         cwd      = self.sim_root,
                         errormsg = "Failed to create library '{}'".format(f.logical_name)).run()

            if f.file_type in ["verilogSource",
		               "verilogSource-95",
		               "verilogSource-2001",
		               "verilogSource-2005"]:
                cmd = 'vlog'
                args = self.vlog_options[:]
                args += vlog_include_dirs
            elif f.file_type in ["systemVerilogSource",
			         "systemVerilogSource-3.0",
			         "systemVerilogSource-3.1",
			         "systemVerilogSource-3.1a"]:
                cmd = 'vlog'
                args = self.vlog_options[:]
                args += ['-sv']
                args += vlog_include_dirs
            elif f.file_type == 'vhdlSource':
                cmd = 'vcom'
            elif f.file_type == 'vhdlSource-87':
                cmd = 'vcom'
                args = ['-87']
            elif f.file_type == 'vhdlSource-93':
                cmd = 'vcom'
                args = ['-93']
            elif f.file_type == 'vhdlSource-2008':
                cmd = 'vcom'
                args = ['-2008']
            else:
                _s = "{} has unknown file type '{}'"
                pr_warn(_s.format(f.name,
                                  f.file_type))
            if not Config().verbose:
                args += ['-quiet']
            args += ['-work', f.logical_name]
            args += [f.name]
            Launcher(os.path.join(self.model_tech, cmd), args,
                 cwd      = self.sim_root,
                 errormsg = "Failed to compile simulation model. Compile log is available in " + logfile).run()

        for vpi_module in self.vpi_modules:
            objs = []
            for src_file in vpi_module['src_files']:
                args = []
                args += ['-c']
                args += ['-std=c99']
                args += ['-fPIC']
                args += ['-fno-stack-protector']
                args += ['-g']
                args += ['-m32']
                args += ['-DMODELSIM_VPI']
                args += ['-I'+self.model_tech+'/../include']
                args += ['-I'+s for s in vpi_module['include_dirs']]
                args += [src_file]
                Launcher('gcc', args,
                         cwd      = self.sim_root,
                         errormsg = "Compilation of "+src_file + "failed").run()

            object_files = [os.path.splitext(os.path.basename(s))[0]+'.o' for s in vpi_module['src_files']]

            args = []
            args += ['-shared']
            args += ['-E']
            args += ['-melf_i386']
            args += ['-o', vpi_module['name']]
            args += object_files
            args += [s for s in vpi_module['libs']]
            Launcher('ld', args,
                     cwd      = self.sim_root,
                     errormsg = "Linking of "+vpi_module['name'] + " failed").run()
예제 #29
0
    def _write_build_rtl_tcl_file(self, tcl_main):
        tcl_build_rtl = open(
            os.path.join(self.work_root, "fusesoc_build_rtl.tcl"), 'w')

        (src_files, incdirs) = self._get_fileset_files(['sim', 'rivierapro'])
        vlog_include_dirs = [
            '+incdir+' + d.replace('\\', '/') for d in incdirs
        ]

        libs = []
        for f in src_files:
            if not f.logical_name:
                f.logical_name = 'work'
            if not f.logical_name in libs:
                tcl_build_rtl.write("vlib {}\n".format(f.logical_name))
                libs.append(f.logical_name)
            if f.file_type.startswith("verilogSource") or \
               f.file_type.startswith("systemVerilogSource"):

                cmd = 'vlog'
                args = []

                if self.system.rivierapro is not None:
                    args += self.system.rivierapro.vlog_options

                if f.file_type.startswith("verilogSource"):
                    if f.file_type.endswith("95"):
                        args.append('-v95')
                    elif f.file_type.endswith("2001"):
                        args.append('-v2k')
                    elif f.file_type.endswith("2005"):
                        args.append('-v2k5')
                else:
                    args += ['-sv']

                for k, v in self.vlogdefine.items():
                    args += ['+define+{}={}'.format(k, v)]

                args += vlog_include_dirs
            elif f.file_type.startswith("vhdlSource"):
                cmd = 'vcom'
                if f.file_type.endswith("-87"):
                    args = ['-87']
                if f.file_type.endswith("-93"):
                    args = ['-93']
                if f.file_type.endswith("-2008"):
                    args = ['-2008']
                else:
                    args = []
            elif f.file_type == 'tclSource':
                cmd = None
                tcl_main.write("do {}\n".format(f.name))
            elif f.file_type == 'user':
                cmd = None
            else:
                _s = "{} has unknown file type '{}'"
                pr_warn(_s.format(f.name, f.file_type))
                cmd = None
            if cmd:
                if not Config().verbose:
                    args += ['-quiet']
                args += ['-work', f.logical_name]
                args += [f.name.replace('\\', '/')]
                tcl_build_rtl.write("{} {}\n".format(cmd, ' '.join(args)))
예제 #30
0
    def _write_tcl_file(self):
        tcl_file = open(
            os.path.join(self.work_root, self.system.name + '.tcl'), 'w')
        tcl_file.write("project_new " + self.system.name + " -overwrite\n")
        tcl_file.write("set_global_assignment -name FAMILY " +
                       self.system.backend.family + '\n')
        tcl_file.write("set_global_assignment -name DEVICE " +
                       self.system.backend.device + '\n')
        # default to 'orpsoc_top' if top_module entry is missing
        top_module = 'orpsoc_top'
        if self.system.backend.top_module:
            top_module = self.system.backend.top_module
        tcl_file.write("set_global_assignment -name TOP_LEVEL_ENTITY " +
                       top_module + '\n')

        for key, value in self.vlogparam.items():
            tcl_file.write("set_parameter -name {} {}\n".format(key, value))
        (src_files, incdirs) = self._get_fileset_files(['synth', 'quartus'])

        for f in src_files:
            if f.file_type in [
                    "verilogSource", "verilogSource-95", "verilogSource-2001",
                    "verilogSource-2005"
            ]:
                _type = 'VERILOG_FILE'
            elif f.file_type in [
                    "systemVerilogSource", "systemVerilogSource-3.0",
                    "systemVerilogSource-3.1", "systemVerilogSource-3.1a"
            ]:
                _type = 'SYSTEMVERILOG_FILE'
            elif f.file_type in [
                    'vhdlSource', 'vhdlSource-87', 'vhdlSource-93',
                    'vhdlSource-2008'
            ]:
                _type = 'VHDL_FILE'
            else:
                _type = None
                _s = "{} has unknown file type '{}'"
                utils.pr_warn(_s.format(f.name, f.file_type))
            if _type:
                _s = "set_global_assignment -name {} {}\n"
                tcl_file.write(_s.format(_type, f.name))

        for include_dir in incdirs:
            tcl_file.write("set_global_assignment -name SEARCH_PATH " +
                           include_dir + '\n')

        for f in self.system.backend.sdc_files:
            dst_dir = os.path.join(self.src_root, self.system.name)
            sdc_file = os.path.relpath(os.path.join(dst_dir, f),
                                       self.work_root)
            tcl_file.write("set_global_assignment -name SDC_FILE " + sdc_file +
                           '\n')

        # NOTE: The relative path _have_ to be used here, if the absolute path
        # is used, quartus_asm will fail with an error message that
        # sdram_io.pre.h can't be read or written.
        for f in self.qip_files:
            tcl_file.write("set_global_assignment -name QIP_FILE " +
                           os.path.relpath(f, self.work_root) + '\n')

        tcl_files = self.system.backend.tcl_files
        for f in tcl_files:
            tcl_file.write(open(os.path.join(self.system_root, f)).read())
        tcl_file.close()