예제 #1
0
def cpu_core(clock, data_in, pc_in, write_pc, debug=False):
    """
    the core CPU state machine
    executes a 4 state loop continuously
    s0: fetch address from pc
    s1: fetch value from address and increment pc
    s2: fetch address from pc
    s3: store value to address and increment pc
    """

    network = clock.network
    word_size = len(data_in)

    # step through the 4 states in order
    state = PlaceholderWord(network, 2)
    incr, c = ripple_incr(state)
    state.replace(register(incr, clock))
    s0, s1, s2, s3 = address_decode(state)

    # pc increments in s1 and s3, incoming pc writes from the jump module are taken in s3
    pc = PlaceholderWord(network, word_size)
    incr, c = ripple_incr(pc)
    jumping = And(write_pc, s3)
    new_pc = word_mux([jumping], incr, pc_in)
    clock_pc = And(clock, Or(s1, s3))
    pc.replace(register(new_pc, clock_pc))

    # clock in address in s0 and s2
    addr = register(data_in, And(clock, Or(s0, s2)))

    # set address lines to pc in s0 and s2 and to the previously fetched address in s1 and s3
    addr_out = word_switch([Or(s0, s2), Or(s1, s3)], pc, addr)

    # read in data in s1
    data = register(data_in, And(clock, s1))

    # write out data in s3
    write_out = s3
    data_out = data

    if debug:
        clock.watch('clock')
        s0.watch('s0')
        s1.watch('s1')
        s2.watch('s2')
        s3.watch('s3')
        jumping.watch('jumping')
        clock_pc.watch('clock pc')
        write_out.watch('write out')

    return addr_out, data_out, write_out
예제 #2
0
def computer(clock, rom_content):
    network = clock.network

    # cpu
    data_in = PlaceholderWord(network, WORD_SIZE)
    pc_in = PlaceholderWord(network, WORD_SIZE)
    pc_write = Placeholder(network)
    address, data_out, write_out = cpu_core.cpu_core(clock, data_in, pc_in,
                                                     pc_write)

    # rom
    rom_write = Placeholder(network)
    rom_data = memory.rom(clock, rom_write, address, data_out, ROM_SIZE,
                          rom_content)
    rom_module = Module('rom', ROM_BASE, ROM_SIZE, rom_data, rom_write)

    # add
    add_write = Placeholder(network)
    add_data = math.add(clock, add_write, address, data_out)
    add_module = Module('add', ADD_BASE, 2, add_data, add_write)

    # sub
    sub_write = Placeholder(network)
    sub_data = math.sub(clock, sub_write, address, data_out)
    sub_module = Module('sub', SUB_BASE, 2, sub_data, sub_write)

    # mult
    mult_write = Placeholder(network)
    mult_data = math.mult(clock, mult_write, address, data_out)
    mult_module = Module('mult', MULT_BASE, 2, mult_data, mult_write)

    # shift right
    shr_write = Placeholder(network)
    shr_data = math.shift_right(clock, shr_write, address, data_out)
    shr_module = Module('shr', SHR_BASE, 2, shr_data, shr_write)

    # lit
    low_literal_write = Placeholder(network)
    low_literal_data = literals.low_literal(clock, low_literal_write, address,
                                            data_out, LIT_SIZE)
    low_literal_module = Module('lit', LIT_BASE, LIT_SIZE, low_literal_data,
                                low_literal_write)

    # print
    print_write = Placeholder(network)
    print_data = memory.memory(clock, print_write, address, data_out, 0)
    print_module = Module('print', PRINT_BASE, 0, print_data, print_write)

    # ram
    ram_write = Placeholder(network)
    ram_data = memory.memory(clock, ram_write, address, data_out, RAM_SIZE)
    ram_module = Module('ram', RAM_BASE, RAM_SIZE, ram_data, ram_write)

    # jump
    jump_write = Placeholder(network)
    jump_data, _pc_in, _pc_write = jump.jump(clock, jump_write, address,
                                             data_out)
    pc_in.replace(_pc_in)
    pc_write.replace(_pc_write)
    jump_module = Module('jump', JUMP_BASE, 2, jump_data, jump_write)

    modules = [
        rom_module,
        low_literal_module,
        ram_module,
        add_module,
        sub_module,
        mult_module,
        jump_module,
        print_module,
        shr_module,
    ]

    # bus ties it all together
    module_data_lines = [(m.base_address, m.address_size, m.data_lines)
                         for m in modules]
    data_from_bus, write_lines = bus.bus(address, write_out, module_data_lines)
    data_in.replace(data_from_bus)
    for write_line, module in zip(write_lines, modules):
        module.write_line.replace(write_line)

    # print out the module sizes
    print('cpu', data_out[0].block.size)
    for module in modules:
        print(module.name, module.data_lines[0].block.size)
    print('bus', data_from_bus[0].block.size)
    print('total', network.get_size())

    return print_write, print_data
예제 #3
0
def test_jmp2():
    """ same deal as above but with automatic signals so more realistic timing """
    network = Network()
    clock = Switch(network)
    data_in = BinaryIn(network, 8)
    pc_in = PlaceholderWord(network, 8)
    write_pc = Placeholder(network)

    def step():
        network.drain()
        clock.write(True)
        network.drain()
        clock.write(False)
        network.drain()

    addr, data_out, write = cpu_core(clock, data_in, pc_in, write_pc)
    write_pc = write_pc.replace(And(write, mux.equals(102, addr)))
    pc_in = pc_in.replace(data_out)

    addr = BinaryOut(addr)
    data_out = BinaryOut(data_out)

    # fetch addr1 from pc
    network.drain()
    assert not write.read()
    assert addr.read() == 0
    data_in.write(100)

    # fetch data from addr1
    step()
    assert not write.read()
    assert addr.read() == 100
    data_in.write(200)

    # fetch addr2 from pc
    step()
    assert not write.read()
    assert addr.read() == 1
    data_in.write(102)

    # write data to addr2 AND PC
    step()
    assert write.read()
    assert addr.read() == 102
    assert data_out.read() == 200

    # fetch addr1 from pc
    step()
    assert not write.read()
    assert addr.read() == 200
    data_in.write(99)

    # fetch data from addr1
    step()
    assert not write.read()
    assert addr.read() == 99
    data_in.write(98)

    # fetch addr2 from pc
    step()
    assert not write.read()
    assert addr.read() == 201
    data_in.write(97)

    # write data to addr2
    step()
    assert write.read()
    assert addr.read() == 97
    assert data_out.read() == 98
예제 #4
0
def test_jmp2():
    """ same deal as above but with automatic signals so more realistic timing """
    network = Network()
    clock = Switch(network)
    data_in = BinaryIn(network, 8)
    pc_in = PlaceholderWord(network, 8)
    write_pc = Placeholder(network)

    def step():
        network.drain()
        clock.write(True)
        network.drain()
        clock.write(False)
        network.drain()

    addr, data_out, write = cpu_core(clock, data_in, pc_in, write_pc)
    write_pc = write_pc.replace(
        And(write, mux.address_matches(102, addr, invert(addr))))
    pc_in = pc_in.replace(data_out)

    addr = BinaryOut(addr)
    data_out = BinaryOut(data_out)

    # fetch addr1 from pc
    network.drain()
    assert not write.read()
    assert addr.read() == 0
    data_in.write(100)

    # fetch data from addr1
    step()
    assert not write.read()
    assert addr.read() == 100
    data_in.write(200)

    # fetch addr2 from pc
    step()
    assert not write.read()
    assert addr.read() == 1
    data_in.write(102)

    # write data to addr2 AND PC
    step()
    assert write.read()
    assert addr.read() == 102
    assert data_out.read() == 200

    # fetch addr1 from pc
    step()
    assert not write.read()
    assert addr.read() == 200
    data_in.write(99)

    # fetch data from addr1
    step()
    assert not write.read()
    assert addr.read() == 99
    data_in.write(98)

    # fetch addr2 from pc
    step()
    assert not write.read()
    assert addr.read() == 201
    data_in.write(97)

    # write data to addr2
    step()
    assert write.read()
    assert addr.read() == 97
    assert data_out.read() == 98