def __init__(self, platform, **kwargs):
clk_freq = 50 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x4000,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
# front panel (ATX)
self.submodules.front_panel = FrontPanelGPIO(platform, clk_freq)
self.comb += self.crg.reset.eq(self.front_panel.reset)
# sdram
self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(
platform.request("ddram"),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
sdram_module = MT41J128M16(self.clk_freq, "1:4")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb),
self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb),
]
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
def __init__(self, platform, **kwargs):
clk_freq = 100 * 1000000
SoCSDRAM.__init__(self,
platform,
clk_freq,
cpu_type=None,
l2_size=32,
with_uart=False,
with_timer=False)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# uart
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
def __init__(self, platform,
firmware_ram_size=0xa000,
firmware_filename=None,
**kwargs):
clk_freq = 80*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(with_bandwidth=True),
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo("minispartan6"[:8], self.__class__.__name__[:8])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = gensdrphy.GENSDRPHY(platform.request("sdram"),
AS4C16M16(clk_freq))
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash2x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
def __init__(self,
platform,
firmware_ram_size=0x10000,
firmware_filename=None,
**kwargs):
clk_freq = 75 * 1000000
SDRAMSoC.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(
l2_size=32, with_bandwidth=True),
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo(
"atlys", self.__class__.__name__[:8])
self.submodules.firmware_ram = firmware.FirmwareROM(
firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"],
self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
P3R1GE4JGF(self.clk_freq),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash4x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.gateware_size)
self.specials += Keep(self.crg.cd_sys.clk)
platform.add_platform_command("""
NET "{sys_clk}" TNM_NET = "GRPsys_clk";
""",
sys_clk=self.crg.cd_sys.clk)
def __init__(self,
platform,
firmware_ram_size=0xa000,
firmware_filename=None,
**kwargs):
clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
SDRAMSoC.__init__(self,
platform,
clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(
l2_size=32, with_bandwidth=True),
**kwargs)
platform.add_extension(PipistrelloCustom)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo(
"pipistrello"[:8], self.__class__.__name__[:8])
self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset"))
self.submodules.fx2_hack = i2c_hack.I2CShiftReg(
platform.request("fx2_hack"))
self.submodules.firmware_ram = firmware.FirmwareROM(
firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"],
self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
MT46H32M16(self.clk_freq),
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash4x"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.gateware_size)
def __init__(self, platform, **kwargs):
clk_freq = 100*1000000
SoCSDRAM.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.submodules.oled = oled.OLED(platform.request("oled"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 8)
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
def __init__(self, platform,
with_sdram_bist=True, bist_async=True, bist_random=False):
clk_freq = 100*1000000
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_type=None,
l2_size=32,
csr_data_width=32,
with_uart=False,
with_timer=False)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random)
# uart
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# logic analyzer
analyzer_signals = [Signal(2)]
if False:
analyzer_signals = [
generator_user_port.cmd.valid,
generator_user_port.cmd.ready,
generator_user_port.cmd.we,
generator_user_port.cmd.adr,
generator_user_port.wdata.valid,
generator_user_port.wdata.ready,
generator_user_port.wdata.we,
self.generator.start.re,
self.checker.start.re
]
if False:
gen_data = Signal(32)
read_data = Signal(32)
self.comb += [
gen_data.eq(self.checker.core.gen.o),
read_data.eq(checker_user_port.rdata.data)
]
analyzer_signals = [
checker_user_port.cmd.valid,
checker_user_port.cmd.ready,
checker_user_port.cmd.we,
checker_user_port.cmd.adr,
checker_user_port.rdata.valid,
checker_user_port.rdata.ready,
self.generator.start.re,
self.checker.start.re,
gen_data,
read_data,
self.checker.core.errors
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self, platform,
firmware_ram_size=0x10000,
firmware_filename=None,
**kwargs):
clk_freq = 50*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
with_uart=False,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.submodules.dna = dna.DNA()
self.submodules.git_info = git_info.GitInfo()
self.submodules.platform_info = platform_info.PlatformInfo("opsis", self.__class__.__name__[:8])
fx2_uart_pads = platform.request("serial_fx2")
sd_card_uart_pads = platform.request("serial_sd_card")
uart_pads = UARTSharedPads()
self.comb += [
# TX
fx2_uart_pads.tx.eq(uart_pads.tx),
sd_card_uart_pads.tx.eq(uart_pads.tx),
# RX
uart_pads.rx.eq(fx2_uart_pads.rx & sd_card_uart_pads.rx)
]
self.submodules.uart_phy = UARTPHY(uart_pads, self.clk_freq, 115200)
self.submodules.uart = uart.UART(self.uart_phy)
# self.submodules.opsis_eeprom_i2c = i2c.I2C(platform.request("opsis_eeprom"))
self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset"))
self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("opsis_eeprom"))
self.submodules.tofe_eeprom_i2c = i2c.I2C(platform.request("tofe_eeprom"))
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(platform.request("ddram"),
MT41J128M16(self.clk_freq),
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
self.comb += [
self.ddrphy.clk8x_wr_strb.eq(self.crg.clk8x_wr_strb),
self.ddrphy.clk8x_rd_strb.eq(self.crg.clk8x_rd_strb),
]
self.register_sdram_phy(self.ddrphy)
self.submodules.spiflash = spiflash.SpiFlash(
platform.request("spiflash4x"), dummy=platform.spiflash_read_dummy_bits, div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=platform.gateware_size)
self.specials += Keep(self.crg.cd_sys.clk)
platform.add_platform_command("""
NET "{sys_clk}" TNM_NET = "GRPsys_clk";
""", sys_clk=self.crg.cd_sys.clk)
def __init__(self,
platform,
with_sdram_bist=True, bist_async=True, bist_random=True,
spiflash="spiflash_1x",
**kwargs):
clk_freq = 100*1000000
SoCSDRAM.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
with_uart=False,
**kwargs)
self.submodules.crg = _CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.submodules.leds = led.ClassicLed(Cat(platform.request("user_led", i) for i in range(4)))
self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds"))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("A7DDRPHY_BITSLIP", 2)
self.add_constant("A7DDRPHY_DELAY", 6)
sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(cmd_buffer_depth=8))
# sdram bist
if with_sdram_bist:
generator_user_port = self.sdram.crossbar.get_port(mode="write", cd="clk50" if bist_async else "sys")
self.submodules.generator = LiteDRAMBISTGenerator(generator_user_port, random=bist_random)
checker_user_port = self.sdram.crossbar.get_port(mode="read", cd="clk50" if bist_async else "sys")
self.submodules.checker = LiteDRAMBISTChecker(checker_user_port, random=bist_random)
# spi flash
spiflash_pads = platform.request(spiflash)
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
spiflash_dummy = {
"spiflash_1x": 9,
"spiflash_4x": 11,
}
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=spiflash_dummy[spiflash], div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus)
self.add_memory_region("spiflash",
self.mem_map["spiflash"] | self.shadow_base, 16*1024*1024)
# uart mux
uart_sel = platform.request("user_sw", 0)
self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200)
uart_phys = {
"cpu": UARTVirtualPhy(),
"bridge": UARTVirtualPhy()
}
self.comb += [
If(uart_sel,
self.uart_phy.source.connect(uart_phys["bridge"].source),
uart_phys["bridge"].sink.connect(self.uart_phy.sink),
uart_phys["cpu"].source.ready.eq(1) # avoid stalling cpu
).Else(
self.uart_phy.source.connect(uart_phys["cpu"].source),
uart_phys["cpu"].sink.connect(self.uart_phy.sink),
uart_phys["bridge"].source.ready.eq(1) # avoid stalling bridge
)
]
# uart cpu
self.submodules.uart = UART(uart_phys["cpu"])
# uart bridge
self.submodules.bridge = WishboneStreamingBridge(uart_phys["bridge"], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)
