def __init__(self, platform, spiboot=False, **kwargs):
if ICE40:
SoCCore.mem_map = {
} # clear the default map provided by the simulation
SoCCore.mem_map["rom"] = 0x0
SoCCore.mem_map["sram"] = 0x01000000
SoCCore.mem_map["com"] = 0xd0000000 # when simulating ICE40
SoCCore.mem_map["csr"] = 0xe0000000
else:
SoCCore.mem_map["wifi"] = 0xe0010000 # when simulating 7-series
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
vex_verilog_path=VEX_CPU_PATH,
**kwargs) # SoC magic is in here
# FIXME: the SpiFifoPeripheral core inside spi_ice40 is *not* the code used in the EC
# FIXME: the EC currently keeps it in an "rtl" directory. This should be fixed to point to "gateware"
# SPI interface
self.submodules.spicontroller = ClockDomainsRenamer({"sys": "spi"})(
spi_7series.SPIController(platform.request("com")))
self.add_csr("spicontroller")
self.submodules.com = ClockDomainsRenamer({"spi_peripheral": "spi"})(
spi_ice40.SpiFifoPeripheral(platform.request("peripheral")))
self.add_wb_slave(self.mem_map["com"], self.com.bus, 4)
self.add_memory_region("com", self.mem_map["com"], 4, type='io')
self.add_csr("com")
self.add_interrupt("com")
def __init__(self, platform, spiboot=False, **kwargs):
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
**kwargs) # SoC magic is in here
# SPI interface
self.submodules.spicontroller = spi_7series.SPIController(
platform.request("com")
) # replace with spi_ice40 to simulate the ice40 controller
self.add_csr("spicontroller")
self.submodules.spiperipheral = spi_7series.SPIPeripheral(
platform.request("peripheral"))
self.add_csr("spiperipheral")
def __init__(self, platform, spiboot=False, **kwargs):
if ICE40:
SoCCore.mem_map = {
} # clear the default map provided by the simulation
SoCCore.mem_map["rom"] = 0x0
SoCCore.mem_map["sram"] = 0x01000000
SoCCore.mem_map["com"] = 0xd0000000 # when simulating ICE40
SoCCore.mem_map["csr"] = 0xe0000000
else:
SoCCore.mem_map["wifi"] = 0xe0010000 # when simulating 7-series
Sim.__init__(self,
platform,
custom_clocks=local_clocks,
spiboot=spiboot,
vex_verilog_path=VEX_CPU_PATH,
**kwargs) # SoC magic is in here
# SPI interface
self.submodules.spicontroller = ClockDomainsRenamer({"sys": "spi"})(
spi_7series.SPIController(platform.request("com"),
pipeline_cipo=True))
self.add_csr("spicontroller")
self.clock_domains.cd_sclk = ClockDomain()
self.comb += self.cd_sclk.clk.eq(self.spicontroller.sclk)
self.submodules.com = spi_ice40.SpiFifoPeripheral(
platform.request("peripheral"), pipeline_cipo=True)
self.comb += self.com.oe.eq(1),
self.bus.add_slave(
"com", self.com.bus,
SoCRegion(origin=self.mem_map["com"],
size=4,
mode="rw",
cached=False))
#self.add_wb_slave(self.mem_map["com"], self.com.bus, 4)
#self.add_memory_region("com", self.mem_map["com"], 4, type='io')
self.add_csr("com")