def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x2800
# FIXME: Force either lite or minimal variants of CPUs; full is too big.
clk_freq = int(12e6)
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
# Control and Status
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# SPI flash peripheral
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom",
kwargs['cpu_reset_address'],
bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region(
"user_flash",
self.flash_boot_address,
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
platform.spiflash_total_size -
(self.flash_boot_address - self.mem_map["spiflash"]) - 0x100,
type="cached+linker")
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[
3] = "icepack -s {build_name}.txt {build_name}.bin"
platform.toolchain.nextpnr_build_template[
2] = "icepack -s {build_name}.txt {build_name}.bin"
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
# disable ROM, it'll be added later
kwargs['integrated_rom_size'] = 0x0
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size
if os.environ.get('JIMMO', '0') == '0':
kwargs['uart_baudrate'] = 19200
else:
kwargs['uart_baudrate'] = 115200
sys_clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / sys_clk_freq)
# Basic peripherals ------------------------------------------------------------------------
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Add debug interface if the CPU has one ---------------------------------------------------
if hasattr(self.cpu, "debug_bus"):
self.register_mem(name="vexriscv_debug",
address=0xf00f0000,
interface=self.cpu.debug_bus,
size=0x100)
# Memory mapped SPI Flash ------------------------------------------------------------------
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size)
self.add_wb_slave(self.mem_map["spiflash"], self.spiflash.bus,
platform.spiflash_total_size)
self.add_memory_region("spiflash", self.mem_map["spiflash"],
platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom",
kwargs['cpu_reset_address'],
bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
define_flash_constants(self)
def __init__(self, platform, **kwargs):
cpu_reset_address = self.mem_map["spiflash"] + platform.gateware_size
clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
SoCSDRAM.__init__(
self,
platform,
clk_freq,
#integrated_rom_size=0x8000,
integrated_rom_size=None,
integrated_sram_size=0x4000,
uart_baudrate=(19200, 115200)[int(os.environ.get('JIMMO', '0'))],
cpu_reset_address=cpu_reset_address,
**kwargs)
self.submodules.crg = _CRG(platform, clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
# Basic peripherals
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# spi flash
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom", cpu_reset_address, bios_size)
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
# sdram
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_rom_size', 0x8000)
dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
kwargs['uart_baudrate'] = 230400
sys_clk_freq = int(75 * 1000 * 1000)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / sys_clk_freq)
# Basic peripherals ------------------------------------------------------------------------
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Memory mapped SPI Flash ------------------------------------------------------------------
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
# SDRAM ------------------------------------------------------------------------------------
sdram_module = MT47H32M16(self.sys_clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=0,
wr_bitslip=4,
dqs_ddr_alignment="C0")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size']=0
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size']=0x2800
# FIXME: Force either lite or minimal variants of CPUs; full is too big.
platform.add_extension(serial)
clk_freq = int(16e6)
# Extra 0x28000 is due to bootloader bitstream.
kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size+platform.bootloader_size
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
# Control and Status
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# SPI flash peripheral
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.register_mem("spiflash", self.mem_map["spiflash"],
self.spiflash.bus, size=platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region(
"rom", kwargs['cpu_reset_address'], bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size+platform.bootloader_size
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region("user_flash",
self.flash_boot_address,
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
platform.spiflash_total_size - (self.flash_boot_address - self.mem_map["spiflash"]) - 0x100,
type="cached+linker")
# Disable USB activity until we switch to a USB UART.
self.comb += [platform.request("usb").pullup.eq(0)]
# Arachne-pnr is unsupported- it has trouble routing this design
# on this particular board reliably. That said, annotate the build
# template anyway just in case.
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[3] = "icepack -s {build_name}.txt {build_name}.bin"
platform.toolchain.nextpnr_build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size']=0
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size']=0
# FIXME: Force either lite or minimal variants of CPUs; full is too big.
# Assume user still has LEDs/Buttons still attached to the PCB or as
# a PMOD; pinout is identical either way.
platform.add_extension(icebreaker.break_off_pmod)
clk_freq = int(12e6)
kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
# Control and Status
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# SPI flash peripheral
# TODO: Inferred tristate not currently supported by nextpnr; upgrade
# to spiflash4x when possible.
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.register_mem("spiflash", self.mem_map["spiflash"],
self.spiflash.bus, size=platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
# free up scarce block RAM.
self.submodules.spram = up5kspram.Up5kSPRAM(size=128*1024)
self.register_mem("sram", 0x10000000, self.spram.bus, 0x20000)
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region("user_flash",
self.flash_boot_address,
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
platform.spiflash_total_size - (self.flash_boot_address - self.mem_map["spiflash"]) - 0x100)
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[3] = "icepack -s {build_name}.txt {build_name}.bin"
platform.toolchain.nextpnr_build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_sram_size', 0x2800)
# disable ROM, it'll be added later
kwargs['integrated_rom_size'] = 0x0
# FIXME: Force either lite or minimal variants of CPUs; full is too big.
clk_freq = int(12e6)
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
# Control and Status
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
self.add_csr("cas")
# SPI flash peripheral
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom",
kwargs['cpu_reset_address'],
bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
define_flash_constants(self)
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region(
"user_flash",
self.flash_boot_address,
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
platform.spiflash_total_size -
(self.flash_boot_address - self.mem_map["spiflash"]) - 0x100,
type="cached+linker")
def __init__(self, platform, **kwargs):
# The TinyFPGA BX has 128kbit of blockram == 16kbytes
# Each BRAM is 512bytes == 32 BRAM blocks
# Need 4 BRAM blocks for USB, leaving 28.
# - 8kbytes ROM - 16 x BRAMs
# - 4kbytes RAM - 8 x BRAMs
kwargs['integrated_rom_size']=0
kwargs['integrated_sram_size']=16*1024
# Disable BIOS
#kwargs['integrated_rom_init'] = [0]
# FIXME: Force either lite or minimal variants of CPUs; full is too big.
if 'cpu_variant' not in kwargs:
kwargs['cpu_variant']='lite'
platform.add_extension(serial)
platform.add_extension(reset_button)
clk_freq = int(16e6)
# Extra 0x28000 is due to bootloader bitstream.
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
# Control and Status
# self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# self.add_csr("cas")
# SPI flash peripheral
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.register_mem("spiflash", self.mem_map["spiflash"],
self.spiflash.bus, size=platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size+platform.bootloader_size
def __init__(self, platform, **kwargs):
bios_size = 0x8000
spiflash_base = self.mem_map['spiflash']
spiflash_bios_base = spiflash_base + platform.gateware_size
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
spiflash_user_base = spiflash_base + platform.gateware_size + bios_size
spiflash_user_size = platform.spiflash_total_size - round_up_to_4(platform.gateware_size + bios_size)
print("""
Flash start: {:08x}
Gateware size: {:08x}
BIOS start: {:08x}
BIOS size: {:08x}
BIOS end: {:08x}
User start: {:08x}
User size: {:08x}
User end: {:08x}
Flash end: {:08x}
""".format(
spiflash_base,
platform.gateware_size,
spiflash_bios_base,
bios_size,
spiflash_bios_base+bios_size,
spiflash_user_base,
spiflash_user_size,
spiflash_user_base+spiflash_user_size,
spiflash_base + platform.spiflash_total_size,
))
kwargs['cpu_reset_address'] = spiflash_bios_base
dict_set_max(kwargs, 'integrated_sram_size', 0x2800)
# disable ROM, it'll be added later
kwargs['integrated_rom_size'] = 0x0
kwargs['uart_name'] = 'crossover'
sys_clk_freq = int(12e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
#if isinstance(self.cpu, VexRiscv):
# self.cpu.use_external_variant("gateware/cpu/VexRiscv_Fomu_Debug.v")
self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
if isinstance(self.cpu, VexRiscv) and "debug" in self.cpu.variant:
self.register_mem(
name="vexriscv_debug",
address=0xf00f0000,
interface=self.cpu.debug_bus,
size=0x100)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
# Basic peripherals ------------------------------------------------------------------------
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
#self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
#self.add_csr("cas")
# Memory mapped SPI Flash ------------------------------------------------------------------
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div,
endianness='little') #self.cpu.endianness)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size)
self.register_mem(
name="spiflash",
address=spiflash_base,
interface=self.spiflash.bus,
size=platform.spiflash_total_size)
# BIOS is running from flash
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region(
name="rom",
origin=spiflash_bios_base,
length=bios_size,
type="cached+linker")
self.flash_boot_address = spiflash_user_base
define_flash_constants(self)
# Make the LEDs flash ----------------------------------------------------------------------
cnt = Signal(32)
self.sync += [
cnt.eq(cnt + 1),
]
self.comb += [
self.platform.request("user_led").eq(cnt[31]),
self.platform.request("user_led").eq(cnt[30]),
self.platform.request("user_led").eq(cnt[29]),
self.platform.request("user_led").eq(cnt[28]),
self.platform.request("user_led").eq(cnt[27]),
self.platform.request("user_led").eq(cnt[26]),
self.platform.request("user_led").eq(cnt[25]),
]
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region(
name="user_flash",
origin=spiflash_user_base,
length=spiflash_user_size,
type="cached+linker")
platform_toolchain_extend(platform, "nextpnr-ice40", "--placer heap")
def __init__(self, platform, debug=False, **kwargs):
clk_freq = int(12e6)
if "cpu_type" not in kwargs:
kwargs["cpu_type"] = None
kwargs["cpu_variant"] = None
if "with_uart" not in kwargs:
kwargs["with_uart"] = False
if "with_ctrl" not in kwargs:
kwargs["with_ctrl"] = False
kwargs["integrated_sram_size"] = 0
bios_size = kwargs["integrated_rom_size"]
kwargs["integrated_rom_size"] = 0
kwargs["cpu_reset_address"] = self.mem_map["spiflash"]+platform.bootloader_size+platform.gateware_size
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
# free up scarce block RAM.
spram_size = 128*1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
# Control and Status
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# SPI flash peripheral
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.register_mem("spiflash", self.mem_map["spiflash"],
self.spiflash.bus, size=platform.spiflash_total_size)
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region(
"rom", kwargs["cpu_reset_address"], bios_size,
type="cached+linker")
self.flash_boot_address = kwargs["cpu_reset_address"]+bios_size
define_flash_constants(self)
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region("user_flash",
self.flash_boot_address,
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
platform.spiflash_total_size - (self.flash_boot_address - self.mem_map["spiflash"]) - 0x100,
type="cached+linker")
# Add USB pads
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=debug)
if debug:
self.add_wb_master(self.usb.debug_bridge.wishbone)
# For the EVT board, ensure the pulldown pin is tristated as an input
if hasattr(usb_pads, "pulldown"):
pulldown = TSTriple()
self.specials += pulldown.get_tristate(usb_pads.pulldown)
self.comb += pulldown.oe.eq(0)
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_sram_size', 0x4000)
# disable ROM, it'll be added later
kwargs['integrated_rom_size'] = 0x0
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size
if os.environ.get('JIMMO', '0') == '0':
kwargs['uart_baudrate'] = 19200
else:
kwargs['uart_baudrate'] = 115200
sys_clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / sys_clk_freq)
# DDR2 SDRAM -------------------------------------------------------------------------------
if True:
sdram_module = MT46H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
memtype=sdram_module.memtype,
rd_bitslip=1,
wr_bitslip=3,
dqs_ddr_alignment="C1")
self.add_csr("ddrphy")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
# Basic peripherals ------------------------------------------------------------------------
self.submodules.info = info.Info(platform, self.__class__.__name__)
self.add_csr("info")
self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
self.add_csr("cas")
# Add debug interface if the CPU has one ---------------------------------------------------
if hasattr(self.cpu, "debug_bus"):
self.register_mem(name="vexriscv_debug",
address=0xf00f0000,
interface=self.cpu.debug_bus,
size=0x100)
# Memory mapped SPI Flash ------------------------------------------------------------------
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size)
self.add_wb_slave(self.mem_map["spiflash"], self.spiflash.bus,
platform.spiflash_total_size)
self.add_memory_region("spiflash", self.mem_map["spiflash"],
platform.spiflash_total_size)
if kwargs.get('cpu_type', None) == "mor1kx":
bios_size = 0x10000
else:
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom",
kwargs['cpu_reset_address'],
bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
define_flash_constants(self)
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = 0
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0
print(kwargs)
clk_freq = int(12e6)
kwargs['uart_stub'] = True
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
# Control and Status
# self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
# SPI flash peripheral
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
# SDRAM
sdram_module = AS4C16M16(clk_freq, "1:1")
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom",
kwargs['cpu_reset_address'],
bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
#self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region(
"user_flash",
self.flash_boot_address,
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
platform.spiflash_total_size -
(self.flash_boot_address - self.mem_map["spiflash"]) - 0x100,
type="cached+linker")
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_sram_size', 0x2800)
# We save the ROM size passed in as the BIOS size, and then force the
# integrated ROM size to 0 to avoid integrated ROM.
bios_size = kwargs['integrated_rom_size']
kwargs['integrated_rom_size'] = 0x0
# FIXME: Force either lite or minimal variants of CPUs; full is too big.
platform.add_extension(serial)
clk_freq = int(16e6)
# Extra 0x28000 is due to bootloader bitstream.
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size + platform.bootloader_size
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / clk_freq)
# Control and Status
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
self.add_csr("cas")
# SPI flash peripheral
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom",
kwargs['cpu_reset_address'],
bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size + platform.bootloader_size
define_flash_constants(self)
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region(
"user_flash",
self.flash_boot_address,
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
platform.spiflash_total_size -
(self.flash_boot_address - self.mem_map["spiflash"]) - 0x100,
type="cached+linker")
# Disable USB activity until we switch to a USB UART.
self.comb += [platform.request("usb").pullup.eq(0)]
def __init__(self, platform, **kwargs):
if 'integrated_rom_size' not in kwargs:
kwargs['integrated_rom_size'] = None
if 'integrated_sram_size' not in kwargs:
kwargs['integrated_sram_size'] = 0x4000
kwargs['cpu_reset_address'] = self.mem_map[
"spiflash"] + platform.gateware_size
#kwargs['uart_baudrate']=115200
clk_freq = (15 + Fraction(5, 8)) * 1000 * 1000 #15625000
SoCSDRAM.__init__(self, platform, clk_freq,
**kwargs) #with_uart=False,
self.submodules.crg = _CRG(platform, clk_freq)
# spi flash
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE",
platform.spiflash_sector_size)
#self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=platform.spiflash_total_size)
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
self.flash_boot_address = self.mem_map[
"spiflash"] + platform.gateware_size + bios_size
# self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
# self.submodules.uart = uart.UART(self.uart_phy)
# self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), self.clk_freq, baudrate=115200)
# self.add_wb_master(self.bridge.wishbone)
# # Litescope for analyzing the BIST output
# # --------------------
# self.submodules.io = LiteScopeIO(8)
# for i in range(8):
# try:
# self.comb += platform.request("user_led", i).eq(self.io.output[i])
# except:
# pass
# analyzer_signals = [
# self.spiflash.bus,
# # self.spiflash.cs_n,
# # self.spiflash.clk,
# # self.spiflash.dq_oe,
# # self.spiflash.dqi,
# # self.spiflash.sr,
# ]
# self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 1024)
# def do_exit(self, vns, filename="test/analyzer.csv"):
# self.analyzer.export_csv(vns, filename)
# sdram
sdram_module = MT47H32M16(self.clk_freq, "1:2")
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
platform.request("ddram"),
sdram_module.memtype,
rd_bitslip=2,
wr_bitslip=3,
dqs_ddr_alignment="C1")
controller_settings = ControllerSettings(with_bandwidth=True)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
def __init__(self, platform, **kwargs):
# disable SRAM, it'll be added later
kwargs['integrated_sram_size'] = 0x0
# disable ROM, it'll be added later
kwargs['integrated_rom_size'] = 0x0
# FIXME: Force either lite or minimal variants of CPUs; full is too big.
# Assume user still has LEDs/Buttons still attached to the PCB or as
# a PMOD; pinout is identical either way.
platform.add_extension(icebreaker.break_off_pmod)
clk_freq = int(12e6)
kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
# Control and Status
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
self.add_csr("cas")
# SPI flash peripheral
# TODO: Inferred tristate not currently supported by nextpnr; upgrade
# to spiflash4x when possible.
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.register_mem("spiflash", self.mem_map["spiflash"],
self.spiflash.bus, size=platform.spiflash_total_size)
# rgb led connector
platform.add_extension(icebreaker.rgb_led)
self.submodules.rgbled = ice40.LED(platform.request("rgbled", 0))
self.add_csr("rgbled")
bios_size = 0x8000
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region(
"rom", kwargs['cpu_reset_address'], bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size
define_flash_constants(self)
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
# free up scarce block RAM.
self.submodules.spram = ice40.SPRAM(size=128*1024)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, 0x20000)
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region("user_flash",
self.flash_boot_address,
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
platform.spiflash_total_size - (self.flash_boot_address - self.mem_map["spiflash"]) - 0x100,
type="cached+linker")
