예제 #1
0
def createILA():
    gb = GBArch()
    U1(gb)
    U2(gb)
    U3(gb)
    U4(gb)
    WRI(gb)

    gb.setNext()
    verilogFile = 'gb_verilog_wri.v'
    gb.exportVerilog(verilogFile)
예제 #2
0
파일: export_rdi.py 프로젝트: yuex1994/ILA
def createILA():
    gb = GBArch()
    U1(gb)
    U1b(gb)
    U2(gb)
    U3(gb)
    U3b(gb)
    U4(gb)
    RDI(gb)
    U1c(gb)

    gb.setNext()
    verilogFile = 'gb_verilog_rdi.v'
    gb.exportVerilog(verilogFile)
예제 #3
0
    arg_0_TDATA_nxt = gb.arg_0_TDATA
    gb.arg_0_TDATA_nxt = ila.ite(decode, arg_0_TDATA_nxt, gb.arg_0_TDATA_nxt)

    gbit_nxt = ila.ite((gb.RAM_x == gb.RAM_x_M) & (gb.RAM_y == gb.RAM_y_M),
                       gb.gbit + 1, gb.gbit)
    gb.gbit_nxt = ila.ite(decode, gbit_nxt, gb.gbit_nxt)

    # other states are not affected
    gb.cur_pix_nxt = ila.ite(decode, gb.cur_pix, gb.cur_pix_nxt)
    gb.RAM_x_nxt = ila.ite(decode, gb.RAM_x, gb.RAM_x_nxt)
    gb.RAM_y_nxt = ila.ite(decode, gb.RAM_y, gb.RAM_y_nxt)
    gb.RAM_w_nxt = ila.ite(decode, gb.RAM_w, gb.RAM_w_nxt)
    for i in xrange(0, gb.RAM_size):
        gb.RAM_nxt[i] = ila.ite(decode, gb.RAM[i], gb.RAM_nxt[i])
    for i in xrange(0, gb.stencil_size):
        gb.stencil_nxt[i] = ila.ite(decode, gb.stencil[i], gb.stencil_nxt[i])


def setNext(gb):
    gb.setNext()


if __name__ == '__main__':
    gb = GBArch()

    defNext(gb)
    setNext(gb)

    verilogFile = 'gb_verilog_rdi.v'
    gb.exportVerilog(verilogFile)