def run(module,
submodules=[],
K=4,
virtexFamily=None,
performCheck=True,
generateImplementationFilesFlag=False,
resynthesizeFlag=False,
qsfFileName=None,
parameterFileName=None,
synthesizedFileName=None,
verboseFlag=False):
baseName, ext = getBasenameAndExtension(os.path.basename(module))
if virtexFamily in ("virtex2pro", ):
K = 4
elif virtexFamily in ("virtex5", "zynq", "kintex7"):
K = 6
elif virtexFamily != None:
raise Exception("Unknown virtex family: %s" % virtexFamily)
# Setup working directory
workDir = "work/" + baseName
print "Stage: Creating %s directory and copying design" % workDir
workFiles = [module] + submodules
if qsfFileName: workFiles.append(qsfFileName)
if parameterFileName: workFiles.append(parameterFileName)
if synthesizedFileName: workFiles.append(synthesizedFileName)
createWorkDirAndCopyFiles(workDir, workFiles)
ret_pwd = os.getcwd()
os.chdir(workDir)
# Synthesis
if synthesizedFileName == None:
print "Stage: Synthesizing"
if qsfFileName == None:
qsfFileName = generateQSF(module, submodules)
synthesizedFileName = synthesize(module, qsfFileName, verboseFlag)
# Automatically extract parameters from VHDL
print "Stage: Generating parameters"
if parameterFileName == None:
parameterFileName = baseName + '.par'
with open(parameterFileName, "w") as parameterFile:
parameter_names = extract_parameter_names(module)
parameter_signals = extract_parameter_signals(
parameter_names, synthesizedFileName)
print >> parameterFile, '\n'.join(parameter_signals)
print "Attention: Verify the detected parameters by inspecting %s/%s" % (
workDir, parameterFileName)
if verboseFlag:
print "Parameters:"
os.system('cat %s' % parameterFileName)
# Resynthesize
if resynthesizeFlag:
synthesizedFileName = resynthesize(baseName, synthesizedFileName)
# Unleash TLUT mapper
print "Stage: TLUT mapper"
numLuts, numTLUTs, depth, avDup, origAnds, paramAnds, check = \
simpleTMapper(baseName, synthesizedFileName, parameterFileName, K, performCheck, generateImplementationFilesFlag, module, verboseFlag)
print collumnize(['Luts (TLUTS)', 'depth', 'check'], colwidth)
print collumnize([str(numLuts) + ' (' + str(numTLUTs) + ')', depth, check],
colwidth)
# Print C-files
if generateImplementationFilesFlag:
tlutconfFile = baseName + "-parconfig_resyn.aig"
CFileName = baseName + '.c'
headerFileName = baseName + '.h'
printCFunction(tlutconfFile, CFileName, headerFileName, virtexFamily,
verboseFlag)
# Run regular MAP
print "Stage: SimpleMAP"
numLuts, depth, check = simpleMapper(baseName, synthesizedFileName, K,
performCheck, verboseFlag)
print collumnize(['Luts', 'depth', 'check'], colwidth)
print collumnize([numLuts, depth, check], colwidth)
# Run regular abc fpga
print "Stage: ABC fpga"
numLuts, depth, check = fpgaMapper(baseName, synthesizedFileName, K,
performCheck, verboseFlag)
print collumnize(['Luts', 'depth', 'check'], colwidth)
print collumnize([numLuts, depth, check], colwidth)
os.chdir(ret_pwd)
def run(module, submodules=[], K=4, virtexFamily=None, performCheck=True, generateImplementationFilesFlag=False, resynthesizeFlag=False, qsfFileName=None, parameterFileName=None, synthesizedFileName=None, verboseFlag=False):
baseName, ext = getBasenameAndExtension(os.path.basename(module))
if virtexFamily in ("virtex2pro",):
K = 4
elif virtexFamily in ("virtex5", "zynq", "kintex7"):
K = 6
elif virtexFamily != None:
raise Exception("Unknown virtex family: %s"%virtexFamily)
# Setup working directory
workDir = "work/"+baseName
print "Stage: Creating %s directory and copying design"%workDir
workFiles = [module] + submodules
if qsfFileName: workFiles.append(qsfFileName)
if parameterFileName: workFiles.append(parameterFileName)
if synthesizedFileName: workFiles.append(synthesizedFileName)
createWorkDirAndCopyFiles(workDir, workFiles)
ret_pwd = os.getcwd()
os.chdir(workDir)
# Synthesis
if synthesizedFileName == None:
print "Stage: Synthesizing"
if qsfFileName == None:
qsfFileName = generateQSF(module, submodules)
synthesizedFileName = synthesize(module, qsfFileName, verboseFlag)
# Automatically extract parameters from VHDL
print "Stage: Generating parameters"
if parameterFileName == None:
parameterFileName = baseName+'.par'
with open(parameterFileName, "w") as parameterFile:
parameter_names = extract_parameter_names(module)
parameter_signals = extract_parameter_signals(parameter_names, synthesizedFileName)
print >>parameterFile, '\n'.join(parameter_signals)
print "Attention: Verify the detected parameters by inspecting %s/%s"%(workDir, parameterFileName)
if verboseFlag:
print "Parameters:"
os.system('cat %s'%parameterFileName)
# Resynthesize
if resynthesizeFlag:
synthesizedFileName = resynthesize(baseName, synthesizedFileName)
# Unleash TLUT mapper
print "Stage: TLUT mapper"
numLuts, numTLUTs, depth, avDup, origAnds, paramAnds, check = \
simpleTMapper(baseName, synthesizedFileName, parameterFileName, K, performCheck, generateImplementationFilesFlag, module, verboseFlag)
print collumnize(['Luts (TLUTS)','depth','check'],colwidth)
print collumnize([str(numLuts)+' ('+str(numTLUTs)+')',depth,check],colwidth)
# Print C-files
if generateImplementationFilesFlag:
tlutconfFile = baseName + "-parconfig_resyn.aig"
CFileName = baseName + '.c'
headerFileName = baseName + '.h'
printCFunction(tlutconfFile, CFileName, headerFileName, virtexFamily, verboseFlag)
# Run regular MAP
print "Stage: SimpleMAP"
numLuts, depth, check = simpleMapper(baseName, synthesizedFileName, K, performCheck, verboseFlag)
print collumnize(['Luts','depth','check'],colwidth)
print collumnize([numLuts,depth,check],colwidth)
# Run regular abc fpga
print "Stage: ABC fpga"
numLuts, depth, check = fpgaMapper(baseName, synthesizedFileName, K, performCheck, verboseFlag)
print collumnize(['Luts','depth','check'],colwidth)
print collumnize([numLuts,depth,check],colwidth)
os.chdir(ret_pwd)