def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) import sram from characterizer import trim_spice debug.info(1, "SRAM Test") a = sram.sram(word_size=16, words_per_row=2, num_rows=64, num_subanks=4, branch_factors=(4,4), bank_orientations=("H", "H"), name="sram") tempspice = OPTS.AMC_temp + "sram.sp" a.sp_write(tempspice) filename="{0}{1}".format(OPTS.AMC_temp, "sram.sp") while not path.exists(filename): time.sleep(1) else: os.chmod(filename, 0o777) address1="1"*a.addr_size address2="0"*a.addr_size reduced_file="{0}{1}".format(OPTS.AMC_temp, "reduced.sp") trim_spice.trim_spice(filename, reduced_file, a.word_size, a.w_per_row, a.num_rows, address1, address2) globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import column_mux_array debug.info(1, "Testing sample for 1-way column_mux_array") a = column_mux_array.column_mux_array(columns=8, word_size=1, name="columnmux_array_1") self.local_check(a) debug.info(1, "Testing sample for 2-way column_mux_array") a = column_mux_array.column_mux_array(columns=8, word_size=4, name="columnmux_array_2") self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array") a = column_mux_array.column_mux_array(columns=16, word_size=4, name="columnmux_array_4") self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import sense_amp_array debug.info( 2, "Testing sense_amp_array for word_size=16, words_per_row=1") a = sense_amp_array.sense_amp_array(word_size=16, words_per_row=1, name="sa_array1") self.local_check(a) debug.info( 2, "Testing sense_amp_array for word_size=16, words_per_row=2") a = sense_amp_array.sense_amp_array(word_size=16, words_per_row=2, name="sa_array2") self.local_check(a) debug.info( 2, "Testing sense_amp_array for word_size=16, words_per_row=4") a = sense_amp_array.sense_amp_array(word_size=16, words_per_row=4, name="sa_array4") self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import contact for layer_stack in [("poly", "contact", "metal1"), ("metal1", "via1", "metal2")]: # Check single 1 x 1 contact" debug.info(2, "1 x 1 {} test".format(layer_stack)) c1 = contact.contact(layer_stack, (1, 1)) self.local_drc_check(c1) # check vertical array with one in the middle and two ends debug.info(2, "1 x 3 {} test".format(layer_stack)) c2 = contact.contact(layer_stack, (1, 3)) self.local_drc_check(c2) # check horizontal array with one in the middle and two ends debug.info(2, "3 x 1 {} test".format(layer_stack)) c3 = contact.contact(layer_stack, (3, 1)) self.local_drc_check(c3) # check 3x3 array for all possible neighbors debug.info(2, "3 x 3 {} test".format(layer_stack)) c4 = contact.contact(layer_stack, (3, 3)) self.local_drc_check(c4) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import hierarchical_decoder # rows=4 and rows=8 Doesn't require hierarchical decoder, # they should be made with only predecoders debug.info(1, "Testing 16 row sample for hierarchical_decoder") a = hierarchical_decoder.hierarchical_decoder( rows=16, name="hierarchical_decoder_16") self.local_check(a) debug.info(1, "Testing 32 row sample for hierarchical_decoder") a = hierarchical_decoder.hierarchical_decoder( rows=32, name="hierarchical_decoder_32") self.local_check(a) debug.info(1, "Testing 128 row sample for hierarchical_decoder") a = hierarchical_decoder.hierarchical_decoder( rows=128, name="hierarchical_decoder_128") self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import multi_bank debug.info(1, "Multi Bank SRAM Test") """ range of acceptable value: word_size in any number greater than 1 word_per_row in [1, 2, 4] num_rows in [32, 64, 128, 256, 512] num_subanks in [1, 2, 4, 8] num_banks in [1, 2, 4] orientation in ["H","V"]: Horizontal or Verical two_level_bank in [False, True]: if true split and merge cell will be added """ a = multi_bank.multi_bank(word_size=8, words_per_row=2, num_rows=32, num_subanks=2, num_banks=4, orientation="H", two_level_bank=True, name="multi_bank") self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) # This is a hack to reload the characterizer __init__ with the spice version import characterizer reload(characterizer) from characterizer import lib import sram import tech #**** Setup synopsys' HSIM and VCS ***# debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") s = sram.sram(word_size=4, words_per_row=1, num_rows=32, num_subanks=1, branch_factors=(1, 1), bank_orientations=("H", "H"), name="sram") tempspice = OPTS.AMC_temp + "sram.sp" s.sp_write(tempspice) lib.lib(OPTS.AMC_temp, s) globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name), is_unit_test=False) global calibre import calibre OPTS.check_lvsdrc = False import bank debug.info(1, "Single Bank Test") """ range of acceptable value: word_size is any number greater than 1 word_per_row in [1, 2, 4] num_rows in [32, 64, 128, 256, 512] num_subanks in [1, 2, 4, 8] two_level_bank [False, True] : if True split and merge cells will be added """ a = bank.bank(word_size=32, words_per_row=1, num_rows=64, num_subanks=2, two_level_bank=True, name="bank") self.local_check(a) OPTS.check_lvsdrc = True # return it back to it's normal state globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import precharge_array debug.info(2, "Checking 4 column precharge") pc = precharge_array.precharge_array(columns=4) self.local_check(pc) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import precharge debug.info(2, "Checking precharge") tx = precharge.precharge() self.local_check(tx) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import bitcell_array debug.info(2, "Testing 64x4 array for 6t_cell") a = bitcell_array.bitcell_array(name="bitcell_array", cols=4, rows=8) self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import single_driver_array debug.info(2, "Checking driver") a = single_driver_array.single_driver_array(rows=64) self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import column_mux debug.info(1, "Testing sample of asingle column_mux cell") a = column_mux.column_mux() self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import driver debug.info(2, "Checking driver") tx = driver.driver(rows=8, inv_size =5) self.local_check(tx) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import hierarchical_predecode2x4 as pre debug.info(1, "Testing sample for hierarchy_predecode2x4") a = pre.hierarchical_predecode2x4() self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import pull_up_pull_down debug.info(2, "Checking pull_up_pull_down gate") tx = pull_up_pull_down.pull_up_pull_down(num_nmos=4, num_pmos=3, nmos_size=1, pmos_size=1, vdd_pins=[], gnd_pins=[]) self.local_check(tx) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import replica_bitline stages=2 fanout=3 rows=7 debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) a = replica_bitline.replica_bitline(stages,fanout,rows) self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import delay_chain debug.info(2, "Testing delay_chain, 2 stages with fanout 3") a = delay_chain.delay_chain(fanout_list=[2,3], name="delay_chain1") self.local_check(a) debug.info(2, "Testing delay_chain, 3 stage with fanout 4") a = delay_chain.delay_chain(fanout_list=[4,4,4], name="delay_chain2") self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) OPTS.check_lvsdrc = False import sram debug.info(1, "Testing Verilog for a sample sram") s = sram.sram(word_size=2, words_per_row=1, num_rows=64, num_subanks=4, branch_factors=(1, 4), bank_orientations=("H", "H"), name="sram") OPTS.check_lvsdrc = True vfile = s.name + ".v" vname = OPTS.AMC_temp + vfile s.verilog_write(vname) globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) import sram debug.info(1, "Testing LEF for a sample sram") s = sram.sram(word_size=4, words_per_row=1, num_rows=64, num_subanks=4, branch_factors=(1, 4), bank_orientations=("H", "H"), name="sram3") gdsfile = s.name + ".gds" leffile = s.name + ".lef" gdsname = OPTS.AMC_temp + gdsfile lefname = OPTS.AMC_temp + leffile s.gds_write(gdsname) s.lef_write(lefname) globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import split_merge_control debug.info(1, "Testing sample for split_merge_control for 2 banks") a = split_merge_control.split_merge_control(num_banks=2, name="split_merge_ctrl2") self.local_check(a) debug.info(1, "Testing sample for split_merge_control for 4 banks") a = split_merge_control.split_merge_control(num_banks=4, name="split_merge_ctrl4") self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import sram debug.info(1, "SRAM Test") """ range of acceptable value: word_size in any number greater than 1 word_per_row in [1, 2, 4] num_rows in [32, 64, 128, 256, 512] num_subanks in [1, 2, 4, 8] # In banch_factor, first num is no. of outter_banks and second num is no. of inner_banks, e.g (2, 4) means each one of two outter_bank has 4 inner_banks branch_factors in [(1,1), (1,2), (1,4), (2,4), (4,4)] # In bank_orientations, first value is orientaion of outter_banks and second value is orientaion of inner_banks, e.g ("V", "H") means outter_banks are placed vertically and inner_banks are place horizontally bank_orientations in [("H", "H"), ("V", "H"), ("H", "V"), ("V", "V")] """ a = sram.sram(word_size=16, words_per_row=2, num_rows=64, num_subanks=4, branch_factors=(4, 4), bank_orientations=("H", "H"), name="sram") self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) OPTS.check_lvsdrc = False # This is a hack to reload the characterizer __init__ with the spice version import characterizer reload(characterizer) from characterizer import functional_test import sram import tech debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") s = sram.sram(word_size=2, words_per_row=1, num_rows=32, num_subanks=2, branch_factors=(1, 2), bank_orientations=("H", "H"), name="sram") tempspice = OPTS.AMC_temp + "sram.sp" s.sp_write(tempspice) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) size = (s.addr_size, s.word_size) #at least 4 simulation is needed to calculate delays for each operation T = functional_test.functional_test(size, corner, name=s.name, w_per_row=s.w_per_row, num_rows=s.num_rows, load=tech.spice["input_cap"], slew=tech.spice["rise_time"]) globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import pinv debug.info(2, "Checking 1x size inverter") tx = pinv.pinv(size=1) self.local_check(tx) debug.info(2, "Checking 2x size inverter") tx = pinv.pinv(size=2) self.local_check(tx) debug.info(2, "Checking 7x size inverter") tx = pinv.pinv(size=7) self.local_check(tx) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False # Only print banner here so it's not in unit tests print_banner() # Output info about this run report_status() # Start importing design modules after we have the config file import tech import sram # Keep track of running stats start_time = datetime.datetime.now() print_time("Start",start_time) # import SRAM test generation s = sram.sram(word_size=OPTS.word_size, words_per_row=OPTS.words_per_row, num_rows=OPTS.num_rows, num_subanks=OPTS.num_subanks, branch_factors=OPTS.branch_factors, bank_orientations=OPTS.bank_orientations, name="sram2") # return it back to it's normal state self.local_check(s) OPTS.check_lvsdrc = True print_time("End",datetime.datetime.now(), start_time) globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import write_complete_array debug.info(2, "Testing write_complete for columns=4, word_size=1") a = write_complete_array.write_complete_array(columns=4, word_size=1, name="write_complete1") self.local_check(a) debug.info(2, "Testing write_complete for columns=4, word_size=2") a = write_complete_array.write_complete_array(columns=4, word_size=2, name="write_complete2") self.local_check(a) debug.info(2, "Testing write_complete for columns=4, word_size=4") a = write_complete_array.write_complete_array(columns=4, word_size=4, name="write_complete4") self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import wire import tech import design min_space = 2 * (tech.drc["minwidth_poly"] + tech.drc["minwidth_metal1"]) layer_stack = ("poly", "contact", "metal1") old_position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], [4 * min_space, 3 * min_space], [4 * min_space, 0], [7 * min_space, 0], [7 * min_space, 4 * min_space], [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] position_list = [[x - min_space, y - min_space] for x, y in old_position_list] w = design.design("wire_test1") wire.wire(w, layer_stack, position_list) self.local_drc_check(w) min_space = 2 * (tech.drc["minwidth_poly"] + tech.drc["minwidth_metal1"]) layer_stack = ("metal1", "contact", "poly") old_position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], [4 * min_space, 3 * min_space], [4 * min_space, 0], [7 * min_space, 0], [7 * min_space, 4 * min_space], [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] position_list = [[x + min_space, y + min_space] for x, y in old_position_list] w = design.design("wire_test2") wire.wire(w, layer_stack, position_list) self.local_drc_check(w) min_space = 2 * (tech.drc["minwidth_metal2"] + tech.drc["minwidth_metal1"]) layer_stack = ("metal1", "via1", "metal2") position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], [4 * min_space, 3 * min_space], [4 * min_space, 0], [7 * min_space, 0], [7 * min_space, 4 * min_space], [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] w = design.design("wire_test3") wire.wire(w, layer_stack, position_list) self.local_drc_check(w) min_space = 2 * (tech.drc["minwidth_metal2"] + tech.drc["minwidth_metal1"]) layer_stack = ("metal2", "via1", "metal1") position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], [4 * min_space, 3 * min_space], [4 * min_space, 0], [7 * min_space, 0], [7 * min_space, 4 * min_space], [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] w = design.design("wire_test4") wire.wire(w, layer_stack, position_list) self.local_drc_check(w) min_space = 2 * (tech.drc["minwidth_metal2"] + tech.drc["minwidth_metal3"]) layer_stack = ("metal2", "via2", "metal3") position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], [4 * min_space, 3 * min_space], [4 * min_space, 0], [7 * min_space, 0], [7 * min_space, 4 * min_space], [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] position_list.reverse() w = design.design("wire_test5") wire.wire(w, layer_stack, position_list) self.local_drc_check(w) min_space = 2 * (tech.drc["minwidth_metal2"] + tech.drc["minwidth_metal3"]) layer_stack = ("metal3", "via2", "metal2") position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], [4 * min_space, 3 * min_space], [4 * min_space, 0], [7 * min_space, 0], [7 * min_space, 4 * min_space], [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] position_list.reverse() w = design.design("wire_test6") wire.wire(w, layer_stack, position_list) self.local_drc_check(w) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import path import tech import design min_space = 2 * tech.drc["minwidth_metal1"] layer = ("metal1") # checks if we can retrace a path position_list = [[0, 0], [0, 3 * min_space], [4 * min_space, 3 * min_space], [4 * min_space, 3 * min_space], [0, 3 * min_space], [0, 6 * min_space]] w = design.design("path_test0") path.path(w, layer, position_list) self.local_drc_check(w) min_space = 2 * tech.drc["minwidth_metal1"] layer = ("metal1") old_position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], [4 * min_space, 3 * min_space], [4 * min_space, 0], [7 * min_space, 0], [7 * min_space, 4 * min_space], [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] position_list = [[x + min_space, y + min_space] for x, y in old_position_list] w = design.design("path_test1") path.path(w, layer, position_list) self.local_drc_check(w) min_space = 2 * tech.drc["minwidth_metal2"] layer = ("metal2") old_position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], [4 * min_space, 3 * min_space], [4 * min_space, 0], [7 * min_space, 0], [7 * min_space, 4 * min_space], [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] position_list = [[x - min_space, y - min_space] for x, y in old_position_list] w = design.design("path_test2") path.path(w, layer, position_list) self.local_drc_check(w) min_space = 2 * tech.drc["minwidth_metal3"] layer = ("metal3") position_list = [[0, 0], [0, 3 * min_space], [1 * min_space, 3 * min_space], [4 * min_space, 3 * min_space], [4 * min_space, 0], [7 * min_space, 0], [7 * min_space, 4 * min_space], [-1 * min_space, 4 * min_space], [-1 * min_space, 0]] # run on the reverse list position_list.reverse() w = design.design("path_test3") path.path(w, layer, position_list) self.local_drc_check(w) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import ptx import tech debug.info(2, "Checking single finger NMOS") fet1 = ptx.ptx(width=tech.drc["minwidth_tx"], mults=1, tx_type="nmos", connect_active=False, connect_poly=False) #self.local_drc_check(fet1) debug.info(2, "Checking single finger PMOS") fet2 = ptx.ptx(width=2 * tech.drc["minwidth_tx"], mults=1, tx_type="pmos", connect_active=False, connect_poly=False) #self.local_drc_check(fet2) debug.info(2, "Checking three fingers NMOS") fet3 = ptx.ptx(width=3 * tech.drc["minwidth_tx"], mults=3, tx_type="nmos", connect_active=False, connect_poly=False) #self.local_drc_check(fet3) debug.info(2, "Checking foure fingers PMOS") fet4 = ptx.ptx(width=2 * tech.drc["minwidth_tx"], mults=4, tx_type="pmos", connect_active=True, connect_poly=True) #self.local_drc_check(fet4) debug.info(2, "Checking three fingers NMOS") fet5 = ptx.ptx(width=3 * tech.drc["minwidth_tx"], mults=4, tx_type="nmos", connect_active=True, connect_poly=False) #self.local_drc_check(fet5) debug.info(2, "Checking foure fingers PMOS") fet6 = ptx.ptx(width=2 * tech.drc["minwidth_tx"], mults=3, tx_type="pmos", connect_active=False, connect_poly=True) #self.local_drc_check(fet6) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()
def runTest(self): globals.init_AMC("config_20_{0}".format(OPTS.tech_name)) global calibre import calibre OPTS.check_lvsdrc = False import bank_control_logic import tech debug.info(1, "Testing sample for bank_control_logic") a = bank_control_logic.bank_control_logic(num_rows=32, num_subanks=1, two_level_bank=False, name="bank_ctrl1") self.local_check(a) debug.info(1, "Testing sample for bank_control_logic") a = bank_control_logic.bank_control_logic(num_rows=64, num_subanks=1, two_level_bank=False, name="bank_ctrl2") self.local_check(a) debug.info(1, "Testing sample for bank_control_logic") a = bank_control_logic.bank_control_logic(num_rows=64, num_subanks=2, two_level_bank=True, name="bank_ctrl3") self.local_check(a) debug.info(1, "Testing sample for bank_control_logic") a = bank_control_logic.bank_control_logic(num_rows=32, num_subanks=2, two_level_bank=False, name="bank_ctrl4") self.local_check(a) debug.info(1, "Testing sample for bank_control_logic") a = bank_control_logic.bank_control_logic(num_rows=32, num_subanks=4, two_level_bank=True, name="bank_ctrl5") self.local_check(a) debug.info(1, "Testing sample for bank_control_logic") a = bank_control_logic.bank_control_logic(num_rows=32, num_subanks=4, two_level_bank=False, name="bank_ctrl6") self.local_check(a) debug.info(1, "Testing sample for bank_control_logic") a = bank_control_logic.bank_control_logic(num_rows=64, num_subanks=8, two_level_bank=True, name="bank_ctrl7") self.local_check(a) debug.info(1, "Testing sample for bank_control_logic") a = bank_control_logic.bank_control_logic(num_rows=32, num_subanks=8, two_level_bank=False, name="bank_ctrl8") self.local_check(a) # return it back to it's normal state OPTS.check_lvsdrc = True globals.end_AMC()