def fifoBench(SYNCWRITE=False, SYNCREAD=False):
fifoBus = fifo.bus(DATA=DATA,
ADDR=ADDR,
UPPER=UPPER,
LOWER=LOWER,
OFFSET=OFFSET)
inclk = Signal(bool(0))
outclk = Signal(bool(0))
rst = ResetSignal(0, active=1, isasync=False)
inclkInst = clockDriver(inclk, DELAY=5)
outclkInst = clockDriver(outclk, DELAY=8)
fifoInst = fifoBus.fifo(inclk, outclk, rst)
fifoTesterInst = fifoBus.tester(inclk,
outclk,
rst,
PRINTLOG=False,
SYNCWRITE=SYNCWRITE,
SYNCREAD=SYNCREAD,
inbuff=[],
outbuff=[],
SLOWFACTOR=2)
@instance
def stimulus():
yield delay(10)
yield outclk.posedge
rst.next = rst.active
yield outclk.posedge
rst.next = not rst.active
return instances()
def signalSyncBench(DATA=DATA, indata=tuple([i for i in range(2**DATA)])):
#n = 2**DATA
dIn, dOut = [Signal(intbv(0)[DATA:]) for i in range(2)]
clkIn, clkOut = [Signal(bool(0)) for i in range(2)]
rst = ResetSignal(0, active=1, isasync=False)
clockDriver0_inst = clockDriver(clkIn, DELAY=5)
clockDriver1_inst = clockDriver(clkOut, DELAY=7)
signalSync_inst = signalSync(clkOut, rst, dIn, dOut, DATA=DATA)
@instance
def ResetStimulus():
yield delay(15)
rst.next = rst.active
yield delay(10)
rst.next = not rst.active
for i in indata:
dIn.next = i
yield clkIn.posedge
print("%d" % dIn, "%d" % dOut)
#assert B == B2, "Error occured !!"
#assert False, "Error occured !!"
raise StopSimulation()
return instances()
def laneBench(SYNCWRITE=False, SYNCREAD=False):
laneBus = lane.bus(DATA=DATA, ADDR=ADDR, UPPER=UPPER, LOWER=LOWER, OFFSET=OFFSET)
clkA = Signal(bool(0))
clkB = Signal(bool(0))
rst = ResetSignal(0, active=1, isasync=False)
clkAInst = clockDriver(clkA, DELAY = 5)
clkBInst = clockDriver(clkB, DELAY = 8)
laneInst = lane.lane(clkA, clkB, rst, laneBus)
laneInst.convert(hdl='Verilog', header=hdlcfg.header, directory=hdlcfg.hdl_path, name='lane')
fifoTesterInst = laneBus.busA.tester(clkA, clkA, rst,
PRINTLOG=False, SYNCWRITE=SYNCWRITE,
SYNCREAD=SYNCREAD, inbuff =[], outbuff=[],
SLOWFACTOR=2)
LanePlugInst = laneBus.busB.connector(clkB, rst)
@instance
def stimulus():
yield delay(10)
yield clkB.posedge
rst.next = rst.active
yield clkB.posedge
rst.next = not rst.active
return instances()
def varfifoBench(SYNCWRITE=False, SYNCREAD=False):
varfifoBus = varfifo.bus(DATA=DATA,
WORDS=WORDS,
ADDR=ADDR,
UPPER=UPPER,
LOWER=LOWER,
OFFSET=OFFSET)
clkS = Signal(bool(0))
clkL = Signal(bool(0))
rst = ResetSignal(0, active=1, isasync=False)
clkSInst = clockDriver(clkS, DELAY=5)
clkLInst = clockDriver(clkL, DELAY=8)
varfifo0Inst = varfifoBus.one2many(clkS, clkL, rst)
varfifo1Inst = varfifoBus.many2one(clkS, clkL, rst)
#varfifo0Inst.convert(hdl='Verilog', header=hdlcfg.header, directory=hdlcfg.hdl_path)
#varfifo1Inst.convert(hdl='Verilog', header=hdlcfg.header, directory=hdlcfg.hdl_path)
fifoTesterInst = varfifoBus.busS.tester(
clkS,
clkS,
rst,
PRINTLOG=False,
SYNCWRITE=SYNCWRITE,
SYNCREAD=SYNCREAD,
inbuff=[Signal(modbv(randrange(2**DATA))) for i in range(1024)],
outbuff=[],
SLOWFACTOR=2)
LanePlugInst = varfifoBus.busL.connector(clkL, rst)
@instance
def stimulus():
yield delay(10)
yield clkL.posedge
rst.next = rst.active
yield clkL.posedge
rst.next = not rst.active
return instances()
def axi4StreamBench(packet, SYNCWRITE=False, SYNCREAD=False):
clk = Signal(bool(0))
rst = ResetSignal(0, active=1, isasync=False)
clkInst = clockDriver(clk, DELAY=5)
axi4StreamBus0 = axi4Stream.axi4Stream(DATA=DATA,
WORDS=WORDS,
ADDR=ADDR,
UPPER=UPPER,
LOWER=LOWER,
OFFSET=OFFSET,
U_SIZE=U_SIZE)
axi4StreamBus1 = axi4Stream.axi4Stream(DATA=DATA,
WORDS=WORDS,
ADDR=ADDR,
UPPER=UPPER,
LOWER=LOWER,
OFFSET=OFFSET,
U_SIZE=U_SIZE)
axi2lane0 = axi4Stream.axi2lane(clk, rst, axi4StreamBus0)
axi2lane1 = axi4Stream.axi2lane(clk, rst, axi4StreamBus1)
fifoTesterInst = axi4StreamBus0.laneBus.busB.tester(clk,
clk,
rst,
PRINTLOG=False,
SYNCWRITE=SYNCWRITE,
SYNCREAD=SYNCREAD,
inbuff=packet,
outbuff=[],
SLOWFACTOR=2)
axiConnectorInst = axi4StreamBus0.connector(axi4StreamBus1)
LanePlugInst = axi4StreamBus1.laneBus.busB.connector(clk, rst)
@instance
def stimulus():
yield delay(10)
yield clk.posedge
rst.next = rst.active
yield clk.posedge
rst.next = not rst.active
return instances()
def LFSRBench(LFSR=LFSR):
dout = Signal(bool(0))
din = Signal(bool(0))
run = Signal(bool(0))
ready = Signal(bool(0))
clk = Signal(bool(0))
rst = ResetSignal(0, active=1, isasync=False)
SIZE = 65
TRINOMIAL = 18
IV = 0x00000000000001111
clkInst = clockDriver(clk, DELAY=5)
lfsrInst = LFSR(dout, din, run, ready, clk, rst, SIZE, TRINOMIAL, IV)
@instance
def stimulus():
yield delay(10)
yield clk.posedge
rst.next = rst.active
yield clk.posedge
rst.next = not rst.active
din.next = 0
for i in range(10):
yield clk.posedge
print("%d" % now()) #, "%d" % dout) #, "%d" % ready)
pass
raise StopSimulation()
# run.next = 1
# #print "B: " + bin(B, width) + "| G_v: " + bin(G_v, width)
# #print bin(G, width)
# #print bin(G_v, width)
# #print("%d" % G)
# print("%d" % dout, "%d" % ready)
# #assert B == B2, "Error occured !!"
return instances()
def axi4NodeBench(packet, SYNCWRITE=False, SYNCREAD=False):
clk = Signal(bool(0))
rst = ResetSignal(0, active=1, isasync=False)
clkInst = clockDriver(clk, DELAY=5)
axi4StreamBus0 = axi4Stream.axi4Stream(DATA=DATA,
WORDS=WORDS,
ADDR=ADDR,
UPPER=UPPER,
LOWER=LOWER,
OFFSET=OFFSET,
U_SIZE=U_SIZE)
axi4StreamBus1 = axi4StreamBus0.clone()
axi4StreamBus2 = axi4StreamBus0.clone()
fifoBus0 = fifo.bus(DATA=DATA * WORDS,
ADDR=ADDR,
UPPER=UPPER,
LOWER=LOWER,
OFFSET=OFFSET)
fifoBus1 = fifo.bus(DATA=DATA * WORDS,
ADDR=ADDR,
UPPER=UPPER,
LOWER=LOWER,
OFFSET=OFFSET)
fifoBus2 = fifo.bus(DATA=DATA * WORDS,
ADDR=ADDR,
UPPER=UPPER,
LOWER=LOWER,
OFFSET=OFFSET)
axi4Node0 = axi4Node.node(clk, rst, axi4StreamBus0, fifoBus0)
axi4Node1 = axi4Node.tNode(clk,
rst,
axi4StreamBus1,
axi4StreamBus2,
fifoBus1,
ADDRESS=0xFF,
PRIORITY=1)
axi4Node2 = axi4Node.node(clk, rst, axi4StreamBus2, fifoBus2)
fifoTesterInst = fifoBus0.tester(clk,
clk,
rst,
PRINTLOG=False,
SYNCWRITE=SYNCWRITE,
SYNCREAD=SYNCREAD,
inbuff=packet,
outbuff=[],
SLOWFACTOR=2)
axiConnectorInst = axi4StreamBus0.connector(axi4StreamBus1)
fifoPlugInst0 = fifoBus1.connector(clk, rst)
fifoPlugInst1 = fifoBus2.connector(clk, rst)
@instance
def stimulus():
yield delay(10)
yield clk.posedge
rst.next = rst.active
yield clk.posedge
rst.next = not rst.active
return instances()