#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('fifo.test_fifo') from myhdl import (Signal, ResetSignal, intbv, always_seq, always_comb, instances) from simple.reg import Reg, RoField from ._mem import FifoMem class SyncFifo(object): """FIFO""" def __init__(self, rst, clk, factory, depth): # Depth must be a power of two assert depth == depth & ~(depth - 1) self.depth = depth self.factory = factory self.WR_CLK = clk self.WR_RST = rst self.WR = Signal(False) self.WR_DATA = Signal(factory) self.WR_FULL = Signal(False) self.RD_CLK = clk
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('simple.test_fifo_ram') import sys from myhdl import toVerilog, Simulation, traceSignals, intbv, instance, delay, instances from common.timebase import nsec from common.util import rename_interface from common.test_system import create_system from fifo.sync import SyncFifo from fifo. async import AsyncFifo from .fifo_ram import FifoRam from .test_bus import sb_write, sb_read class Harness(object): def __init__(self, addr_depth, data_width): self.duration = 1000 * nsec self.stimuli = [] self.system, system_inst = create_system(reset_duration=10) self.stimuli.append(system_inst)
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('scope.test_renderer') from myhdl import (Signal, intbv, always_comb, always_seq, instances) from simple.bus import Bus class Renderer(object): def __init__(self, system, sample_width, accumulator_width): self.system = system self.sample_width = sample_width self.accumulator_width = accumulator_width self.STROBE = Signal(False) self.SAMPLE = Signal(intbv(0)[sample_width:]) self._bus = Bus(addr_depth = 1 << sample_width, data_width = self.accumulator_width) def bus(self): return self._bus def gen(self): system = self.system
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('simple.test_reg') from myhdl import Signal, ConcatSignal, SignalType, always_comb, always_seq, intbv from .bus import Bus class Port(object): def __init__(self, width): self.width = width self.WR = Signal(False) self.WR_DATA = Signal(intbv(0)[width:]) self.RD = Signal(False) self.RD_DATA = Signal(intbv(0)[width:]) if 0: self.WR.read = True self.WR_DATA.read = True self.RD.read = True self.RD_DATA.driven = True class Field(object): def __init__(self, name, description, port): self.name = name self.description = description
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('simple.test_algo') import sys from myhdl import toVerilog, Simulation, traceSignals, instance, delay from common.timebase import nsec from common.util import rename_interface from common.test_system import create_system from .algo import Algo from .test_bus import sb_write, sb_read class Harness(object): def __init__(self, addr_depth, data_width): self.duration = 1000 * nsec self.stimuli = [] self.system, system_inst = create_system() self.stimuli.append(system_inst) self.dut = Algo(self.system, addr_depth, data_width) self.bus = self.dut.bus()
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('simple.test_bus') from myhdl import Signal, intbv, always_comb class Bus(object): """ bus. A simple bus port. A master presents the ADDR and WR, WR_DATA and RD on the first positive edge of the clock. On a read the slave must output RD_DATA with enough setup time to be sampled on the second edge. Since there can be no wait states, there is no ACK nor WAIT signal. The clock and reset is provided separately from the rest of the bus since a device, such as a dual port RAM, can have multiple port. Use the system.System class for providing clock and reset. A slave must drive zeroes on RD_DATA when it is not selected. This simplifies the address decoder/mux since it can just use an OR of all the slave RD_DATAs to combine all the buses. A write cycle: 1 2 _ _ |_ |_ _ CLK / \_/ \_/ \_/ \_/ \_
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('simple.test_dpram') from myhdl import Signal, intbv, always_seq, instances from common.system import System from .bus import Bus class DpRam(object): """Dual port DRAM""" def __init__(self, system0, system1, addr_depth, data_width): self.addr_depth = addr_depth self.data_width = data_width self.system0 = system0 self.system1 = system1 self._bus0 = Bus(addr_depth, data_width) self._bus1 = Bus(addr_depth, data_width) def bus0(self): return self._bus0 def bus1(self): return self._bus1
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('common.test_system') from myhdl import ResetSignal from .timebase import nsec from .clk import Clk from .rst import rstgen from .system import System def create_system(clk_freq = 100E6, reset_duration = 99 * nsec): insts = [] clk = Clk(clk_freq) insts.append(clk.gen()) if reset_duration is None: rst = None else: rst = ResetSignal(0, active = 1, async = 0) insts.append(rstgen(rst, reset_duration, clk)) system = System(clk, rst) return system, insts
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('common.clk') from myhdl import Signal, SignalType, instance, delay from .timebase import sec def clkgen(clk, freq): halfperiod = sec / float(freq) / 2 # print "clk", freq, halfperiod @instance def inst(): acc = 0 while 1: acc += halfperiod d = int(acc) acc -= d yield delay(d) clk.next = not clk return inst class Clk(SignalType): def __init__(self, freq, value = False):
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('scope.test_renderer') import sys from myhdl import (ResetSignal, toVerilog, Simulation, traceSignals, instance, delay, instances) from common.timebase import nsec from common.clk import Clk from common.rst import rstgen from .renderer import Renderer duration = 1000 * nsec rst = ResetSignal(True, True, False) clk = Clk(100E6) args = [rst, clk] def gen(rst, clk): global renderer renderer = Renderer(rst, clk,
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('simple.test_mux') import sys from myhdl import (ResetSignal, toVerilog, Simulation, traceSignals, instance, delay) from common.timebase import nsec from common.clk import Clk from common.rst import rstgen from common.system import System from common.util import rename_interface from common.test_system import create_system from .ram import Ram from .mux import Mux from .test_bus import sb_write, sb_read class Harness(object): def __init__(self): self.duration = 1200 * nsec self.stimuli = [] self.system, system_inst = create_system() self.stimuli.append(system_inst)
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('simple.test_bus') from myhdl import Signal, intbv, always_comb class Bus(object): """ bus. A simple bus port. A master presents the ADDR and WR, WR_DATA and RD on the first positive edge of the clock. On a read the slave must output RD_DATA with enough setup time to be sampled on the second edge. Since there can be no wait states, there is no ACK nor WAIT signal. The clock and reset is provided separately from the rest of the bus since a device, such as a dual port RAM, can have multiple port. Use the system.System class for providing clock and reset. A slave must drive zeroes on RD_DATA when it is not selected. This simplifies the address decoder/mux since it can just use an OR of all the slave RD_DATAs to combine all the buses. A write cycle: 1 2 _ _ |_ |_ _ CLK / \_/ \_/ \_/ \_/ \_ ___| |
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('common.test_system') from myhdl import ResetSignal from .timebase import nsec from .clk import Clk from .rst import rstgen from .system import System def create_system(clk_freq=100E6, reset_duration=99 * nsec): insts = [] clk = Clk(clk_freq) insts.append(clk.gen()) if reset_duration is None: rst = None else: rst = ResetSignal(0, active=1, async=0) insts.append(rstgen(rst, reset_duration, clk)) system = System(clk, rst) return system, insts
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('fifo.test_fifo') from myhdl import (Signal, intbv, always_seq, always_comb, instances) from simple.reg import Reg, RoField from ._mem import FifoMem class FifoInterleaver(object): """Interleave data from a wide fifo into a narrower fifo""" def __init__(self, fifo, parts = 2): self.parent = fifo self.parts = parts assert len(self.parent.RD_DATA) % parts == 0 self.data_width = len(self.parent.RD_DATA) / parts self.RD_CLK = self.parent.RD_CLK self.RD_RST = self.parent.RD_RST self.RD = Signal(False) self.RD_DATA = Signal(intbv(0)[self.data_width:]) self.RD_EMPTY = Signal(False)
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('simple.test_algo') from myhdl import Signal, intbv, always_seq, always_comb from common.system import System from common.gray import gray_encoder from .bus import Bus class Algo(object): """ bus slave which returns some data based on the address. This slave is used to test reading over the SoC bus.""" def __init__(self, system, addr_depth, data_width): self.system = system self._bus = Bus(addr_depth, data_width) def bus(self): return self._bus def gen(self): system = self.system bus = self.bus()
#! /usr/bin/python from __future__ import absolute_import if __name__ == '__main__': import hacking hacking.run_as_module('simple.test_fifo_ram') from myhdl import Signal, intbv, always_seq, always_comb, instances from common.system import System from .bus import Bus from .reg import Reg, Port, Field def flatten(x): result = [] for el in x: if not el: pass elif isinstance(el, list) or isinstance(el, tuple): result.extend(flatten(el)) else: result.append(el) return result class FifoRam(object): """RAM a bit of RAM""" def __init__(self, name, system, out_fifo, in_fifo, addr_depth, data_width): self.system = system