def as_hdl_HdlPortItem(self, o: HdlPortItem):
i = o.getInternSig()._interface
d = o.direction
if isinstance(i, Clk):
assert i._dtype.bit_length() == 1, i
if d == DIRECTION.IN:
t = self.sc_in_clk
elif d == DIRECTION.OUT:
t = self.sc_out_clk
elif d == DIRECTION.INOUT:
t = self.sc_inout_clk
else:
raise ValueError(d)
else:
if d == DIRECTION.IN:
pt = self.sc_in
elif d == DIRECTION.OUT:
pt = self.sc_out
elif d == DIRECTION.INOUT:
pt = self.sc_inout
else:
raise ValueError(d)
t = self.as_hdl_HdlType(o._dtype)
t = HdlOp(HdlOpType.PARAMETRIZATION, [pt, t])
var = HdlIdDef()
var.direction = HWT_TO_HDLCONVEROTR_DIRECTION[o.direction]
s = o.getInternSig()
var.name = s.name
var.origin = o
var.type = t
return var
def create_HdlModuleDef(self, target_platform: DummyPlatform,
store_manager: "StoreManager"):
"""
Generate a module body (architecture) for this module
* Resolve name collisions
* Convert netlist representation to HdlProcesses
* Remove unconnected
* Mark visibility of signals
"""
removeUnconnectedSignals(self)
markVisibilityOfSignalsAndCheckDrivers(self.signals, self.interfaces)
for proc in target_platform.beforeHdlArchGeneration:
proc(self)
ns = store_manager.name_scope
mdef = HdlModuleDef()
mdef.dec = self.ent
mdef.module_name = HdlValueId(self.ent.name, obj=self.ent)
mdef.name = "rtl"
processes = sorted(self.statements, key=HdlStatement_sort_key)
processes = sorted(statements_to_HdlStatementBlocks(processes),
key=HdlStatement_sort_key)
# add signals, variables etc. in architecture
for s in sorted((s for s in self.signals
if not s.hidden and s not in self.interfaces.keys()),
key=RtlSignal_sort_key):
v = HdlIdDef()
v.origin = s
s.name = v.name = ns.checked_name(s.name, s)
v.type = s._dtype
v.value = s.def_val
v.is_const = s._const
mdef.objs.append(v)
for p in processes:
p.name = ns.checked_name(p.name, p)
mdef.objs.extend(processes)
# instantiate subUnits in architecture
for u in self.subUnits:
ci = HdlCompInst()
ci.origin = u
ci.module_name = HdlValueId(u._ctx.ent.name, obj=u._ctx.ent)
ci.name = HdlValueId(ns.checked_name(u._name + "_inst", ci), obj=u)
e = u._ctx.ent
ci.param_map.extend(e.params)
ci.port_map.extend(e.ports)
mdef.objs.append(ci)
self.arch = mdef
return mdef
def create_HdlModuleDec(self, name: str, store_manager: "StoreManager",
params: List[Param]):
"""
Generate a module header (entity) for this module
"""
self.ent = ent = HdlModuleDec()
ent.name = store_manager.name_scope.checked_name(name, ent)
ns = store_manager.hierarchy_push(ent)
# create generics
for p in sorted(params, key=lambda x: x._name):
hdl_val = p.get_hdl_value()
v = HdlIdDef()
v.origin = p
v.name = p.hdl_name = ns.checked_name(p._name, p)
v.type = hdl_val._dtype
v.value = hdl_val
ent.params.append(v)
return ent
def as_hdl_HdlType_array(self, typ: HArray, declaration=False):
if declaration:
v = HdlIdDef()
name = getattr(typ, "name", None)
if name is None:
name = "arr_t_"
v.name = self.name_scope.checked_name(name, typ)
v.type = HdlTypeType
v.origin = typ
size = hdl_downto(self.as_hdl_int(int(typ.size) - 1),
self.as_hdl_int(0))
if self.does_type_requires_extra_def(typ.element_t, ()):
raise NotImplementedError(typ.element_t)
e_t = self.as_hdl_HdlType(typ.element_t, declaration=False)
v.value = hdl_index(e_t, size)
return v
else:
return super(ToHdlAstVhdl2008_types,
self).as_hdl_HdlType_array(typ, declaration)
def as_hdl_SignalItem(self,
si: Union[SignalItem, HdlIdDef],
declaration=False):
if declaration:
if isinstance(si, HdlIdDef):
var = copy(si)
si = si.origin
else:
var = HdlIdDef()
var.name = si.name
var.origin = si
var.value = si._val
var.type = si._dtype
var.is_const = si._const
v = var.value
if isinstance(si, RtlSignalBase):
if si.virtual_only:
var.is_latched = True
elif si.drivers or var.direction != HdlDirection.UNKNOWN:
# has drivers or is port/param
pass
elif si.endpoints:
if not v.vld_mask:
raise SerializerException(
"Signal %s is constant and has undefined value" %
si.name)
var.is_const = True
else:
raise SerializerException(
"Signal %s should be declared but it is not used" %
si.name)
if v is None:
pass
elif isinstance(v, RtlSignalBase):
if v._const:
var.value = self.as_hdl(v)
else:
# default value has to be set by reset,
# because it is not resolvable in compile time
var.value = None
pass
elif isinstance(v, Value):
if v.vld_mask or var.is_const:
orig_const_cache = self.constCache
try:
self.constCache = None
var.value = self.as_hdl_Value(v)
finally:
self.constCache = orig_const_cache
else:
# remove value if it is entirely undefined
var.value = None
else:
raise NotImplementedError(v)
var.type = self.as_hdl_HdlType(var.type)
return var
else:
if si.hidden and hasattr(si, "origin"):
# hidden signal, render it's driver instead
return self.as_hdl(si.origin)
return HdlValueId(si.name, obj=si)