def _registerClearConnection(self):
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "--External Clear Connection")
for register_num, register_word in self.reg.items():
for index, register in register_word.items():
if (isinstance(register,RegisterBit) or isinstance(register,RegisterSlice)):
if self.useRecords:
clearname = register.clearName
else:
clearname = register.clearName + "_i"
if register.size == 1:
defaultvalue = "'1'"
elsevalue = "'0'"
vectorRange = str(index)
else:
vectorRange = "%d downto %d" % (index+register.size-1, index)
tmp = register.vhdlRange.replace("(","")
tmp = tmp.replace(")","")
defaultvalue = "(%s => '1')" % tmp
elsevalue = "(%s => '0')" % tmp
if ( register.regType == "Write2Clear" or register.regType == "Write2Pulse"):
elsevalue = "regwrite_s(%d)(%s)" % (register_num, vectorRange)
if register.externalClear:
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "regclear_s(%d)(%s) <= %s when %s = '1' else %s;" %
(register_num, vectorRange, defaultvalue, clearname, elsevalue))
elif ( register.regType == "Write2Clear" or register.regType == "Write2Pulse"):
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "regclear_s(%d)(%s) <= %s;" % (register_num, vectorRange, elsevalue) )
def code(self, indent_level=0):
hdl_code = ""
hdl_code = vhdl.indent(indent_level) + ("package body %s is\r\n" %
self.name)
hdl_code = hdl_code + "\r\n"
# Header
if (self.bodyCodeHeader):
hdl_code = hdl_code + self.bodyCodeHeader.code()
hdl_code = hdl_code + "\r\n"
# Functions
hdl_code = hdl_code + vhdl.indent(indent_level + 1) + (
"-- Functions & Procedures\r\n")
if (self.subPrograms):
hdl_code = hdl_code + self.subPrograms.code()
hdl_code = hdl_code + "\r\n"
else:
hdl_code = hdl_code + vhdl.indent(indent_level + 2) + (
"-- subprograms_declaration_tag\r\n")
# Footer
if (self.bodyCodeHeader):
hdl_code = hdl_code + self.bodyCodeFooter.code()
hdl_code = hdl_code + "\r\n"
hdl_code = hdl_code + vhdl.indent(indent_level) + (
"end package body;\r\n")
hdl_code = hdl_code + "\r\n"
return hdl_code
def _registerSetConnection(self):
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "--Set Connection for Write to Clear")
for reg_num, register_word in self.reg.items():
for index, register in register_word.items():
if isinstance(register, RegisterBit) or isinstance(register, RegisterSlice):
if register.size == 1:
vectorRange = str(index)
else:
vectorRange = "%d downto %d" % (index+register.size-1, index)
if register.regType == "Write2Clear":
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "regset_s(%d)(%s) <= %s;" % (reg_num, vectorRange, register.vhdlName))
self.architecture.bodyCodeFooter.add("")
def _registerConnection(self):
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "--Register Connection")
for register_num, register_word in self.reg.items():
for index, register in register_word.items():
if isinstance(register, RegisterBit) or isinstance(register, RegisterSlice):
if register.size == 1:
vectorRange = str(index)
else:
vectorRange = "%d downto %d" % (index+register.size-1, index)
register.name = register.name+"(%d downto 0)" % (register.size-1)
if "ReadOnly" in register.regType:
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "regread_s(%d)(%s) <= %s;" % (register_num, vectorRange, register.vhdlName))
elif "SplitReadWrite" in register.regType:
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "%s <= regwrite_s(%d)(%s);" %
(register.inv_vhdlName, register_num, vectorRange))
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "regread_s(%d)(%s) <= %s;" %
(register_num, vectorRange, register.vhdlName))
elif "ReadWrite" in register.regType:
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "%s <= regwrite_s(%d)(%s);" % (register.vhdlName, register_num, vectorRange))
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "regread_s(%d)(%s) <= regwrite_s(%d)(%s);" %
(register_num, vectorRange, register_num, vectorRange))
elif "Write2Clear" in register.regType:
# self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "regread_s(%d)(%s) <= %s;" % (register_num,vectorRange,register.name))
pass
elif "Write2Pulse" in register.regType:
self.architecture.bodyCodeFooter.add(vhdl.indent(1) + "%s <= regwrite_s(%d)(%s);" % (register.vhdlName, register_num, vectorRange))
self.architecture.bodyCodeFooter.add("\r\n")
def code(self, indent_level=0):
hdl_code = ""
hdl_code = vhdl.indent(indent_level) + ("package %s is\r\n" %
self.name)
hdl_code = hdl_code + "\r\n"
# Pkg Generics
if (self.generic or self.genericTypes):
hdl_code = hdl_code + vhdl.indent(indent_level +
1) + ("generic (\r\n")
hdl_code = hdl_code + self.generic.code(indent_level + 1)
hdl_code = hdl_code + self.genericTypes.code(indent_level + 1)
hdl_code = hdl_code + vhdl.indent(indent_level + 1) + ("--);\r\n")
hdl_code = hdl_code + "\r\n"
else:
hdl_code = hdl_code + vhdl.indent(indent_level +
1) + ("--generic (\r\n")
hdl_code = hdl_code + vhdl.indent(indent_level + 2) + (
"--Package Generics go here.\r\n")
hdl_code = hdl_code + vhdl.indent(indent_level + 1) + ("--);\r\n")
hdl_code = hdl_code + "\r\n"
hdl_code = hdl_code + self.declarationHeader.code()
hdl_code = hdl_code + self.constant.code()
hdl_code = hdl_code + self.customTypes.code()
hdl_code = hdl_code + self.customTypesConstants.code()
hdl_code = hdl_code + self.signal.code()
hdl_code = hdl_code + self.subPrograms.declaration()
hdl_code = hdl_code + self.component.code()
hdl_code = hdl_code + self.declarationFooter.code()
hdl_code = hdl_code + vhdl.indent(0) + ("end %s;\r\n" % self.name)
hdl_code = hdl_code + "\r\n"
return hdl_code
def write_testbench(self):
self._generate()
testbench = vhdl.BasicVHDL(self.entity.name+"_tb","simulation")
testbench.entity.generic.add("runner_cfg", "string", "")
testbench.entity.generic.add("run_time", "integer", "100")
testbench.library = self.library
testbench.library.add("std")
testbench.library["std"].package.add("textio")
testbench.library.add("vunit_lib")
testbench.library["vunit_lib"].context.add("vunit_context")
testbench.library["vunit_lib"].context.add("vc_context")
testbench.work.add(self.pkg.name)
for index, generic in self.entity.generic.items():
testbench.architecture.constant.add(index,generic.type,generic.value)
testbench.architecture.constant.add("axi_handle","bus_master_t","new_bus(data_length => C_S_AXI_DATA_WIDTH, address_length => C_S_AXI_ADDR_WIDTH)")
testbench.architecture.constant.add("addr_increment_c","integer",str(self.addr_increment))
for port in self.entity.port:
testbench.architecture.signal.add(port,self.entity.port[port].type)
# set starting value to clock. All other signals should be handled by reset.
testbench.architecture.signal["S_AXI_ACLK"].value = "'0'"
testbench.architecture.instances.add("axi_master_u","entity vunit_lib.axi_lite_master")
testbench.architecture.instances["axi_master_u"].generic.add("bus_handle","","axi_handle")
for local_port in list(vunitPort.keys()):
testbench.architecture.instances["axi_master_u"].port.add(local_port,"","")
testbench.architecture.instances["axi_master_u"].port[local_port].assign(vunitPort[local_port])
testbench.architecture.instances.append(self.instanciation("dut_u"))
read_only = vhdl.GenericCodeBlock()
read_write = vhdl.GenericCodeBlock()
split_read_write = vhdl.GenericCodeBlock()
write_to_clear = vhdl.GenericCodeBlock()
write_to_pulse = vhdl.GenericCodeBlock()
external_clear = vhdl.GenericCodeBlock()
for reg_number, register_word in self.reg.items():
reg_address = reg_number * self.addr_increment
for index, register in register_word.items():
if not (isinstance(register,RegisterBit) or isinstance(register,RegisterSlice)):
continue
if register.size == 1:
tb_value = random_bit()
vector_location = "(%s)" % index
all_one = "'1'"
all_zero = "'0'"
else:
tb_value = random_vector(register.size)
vector_location = "(%s downto %s)" % (register.size + index - 1, index)
all_one = "(others=>'1')"
all_zero = "(others=>'0')"
if register.regType == "ReadOnly":
testbench.architecture.bodyCodeFooter.add(vhdl.indent(1) + "--Read Only: %s;" % register.vhdlName)
testbench.architecture.bodyCodeFooter.add(vhdl.indent(1) + "%s <= %s;" % (register.vhdlName, tb_value))
read_only.add(vhdl.indent(1) + "--Testing %s" % register.vhdlName)
read_only.add(vhdl.indent(1) + "read_bus(net,axi_handle,%d,rdata_v);" % reg_address )
read_only.add(vhdl.indent(1) + "check_equal(rdata_v%s,%s,result(\"Test Read: %s.\"));" % ( vector_location, register.vhdlName, register.vhdlName ))
if register.regType == "ReadWrite":
tb_value = random_vector(self.datasize)
read_write.add(vhdl.indent(1) + "--Testing %s" % register.vhdlName)
read_write.add(vhdl.indent(1) + "rdata_v := %s;" % tb_value)
read_write.add(vhdl.indent(1) + "write_bus(net,axi_handle,%d,rdata_v,%s);" % (reg_address, register.byte_enable) )
read_write.add(vhdl.indent(1) + "read_bus(net,axi_handle,%d,rdata_v);" % reg_address )
read_write.add(vhdl.indent(1) + "check_equal(%s,rdata_v%s,result(\"Test Readback and Port value: %s.\"));" % ( register.vhdlName, vector_location, register.vhdlName ))
if register.regType == "SplitReadWrite":
testbench.architecture.bodyCodeFooter.add(vhdl.indent(1) + "--Split Read and Write: %s;" % register.vhdlName)
testbench.architecture.bodyCodeFooter.add(vhdl.indent(1) + "%s <= %s;" % (register.vhdlName, tb_value))
split_read_write.add(vhdl.indent(1) + "--Testing %s" % register.vhdlName)
split_read_write.add(vhdl.indent(1) + "read_bus(net,axi_handle,%d,rdata_v);" % reg_address )
split_read_write.add(vhdl.indent(1) + "check_equal(rdata_v%s,%s,result(\"Test Read: %s.\"));" % ( vector_location, register.vhdlName, register.vhdlName ))
tb_value = random_vector(self.datasize)
split_read_write.add(vhdl.indent(1) + "--Testing %s" % register.inv_vhdlName)
split_read_write.add(vhdl.indent(1) + "rdata_v := %s;" % tb_value )
split_read_write.add(vhdl.indent(1) + "write_bus(net,axi_handle,%d,rdata_v,%s);" % (reg_address, register.byte_enable) )
split_read_write.add(vhdl.indent(1) + "wait for 1 us;")
split_read_write.add(vhdl.indent(1) + "check_equal(%s,rdata_v%s,result(\"Test Read: %s.\"));" % ( register.inv_vhdlName, vector_location, register.inv_vhdlName ))
if register.regType == "Write2Clear":
write_to_clear.add(vhdl.indent(1) + "--Testing %s: Set to %s" % (register.vhdlName, all_one) )
write_to_clear.add(vhdl.indent(1) + "%s <= %s;" % (register.vhdlName, all_one))
write_to_clear.add(vhdl.indent(1) + "wait until rising_edge(S_AXI_ACLK);")
write_to_clear.add(vhdl.indent(1) + "%s <= %s;" % (register.vhdlName, all_zero))
write_to_clear.add(vhdl.indent(1) + "wait until rising_edge(S_AXI_ACLK);")
write_to_clear.add(vhdl.indent(1) + "read_bus(net,axi_handle,%d,rdata_v);" % reg_address )
write_to_clear.add(vhdl.indent(1) + "check(rdata_v%s = %s,result(\"Test Read Ones: %s.\"));" % ( vector_location, tb_value.replace('0','1'), register.vhdlName ))
write_to_clear.add(vhdl.indent(1) + "rdata_v := (others=>'0');" )
write_to_clear.add(vhdl.indent(1) + "rdata_v%s := %s;" % (vector_location, all_one) )
write_to_clear.add(vhdl.indent(1) + "write_bus(net,axi_handle,%d,rdata_v,%s);" % (reg_address, register.byte_enable) )
write_to_clear.add(vhdl.indent(1) + "read_bus(net,axi_handle,%d,rdata_v);" % reg_address )
write_to_clear.add(vhdl.indent(1) + "check(rdata_v%s = %s,result(\"Test Read Zeroes: %s.\"));" % ( vector_location, tb_value.replace('1','0'), register.vhdlName ))
if register.regType == "Write2Pulse":
write_to_pulse.add(vhdl.indent(1) + "--Testing %s" % register.vhdlName)
write_to_pulse.add(vhdl.indent(1) + "rdata_v%s := %s;" % (vector_location, all_one) )
write_to_pulse.add(vhdl.indent(1) + "write_bus(net,axi_handle,%d,rdata_v,%s);" % (reg_address, register.byte_enable) )
write_to_pulse.add(vhdl.indent(1) + "wait until %s = %s;" % (register.vhdlName, tb_value.replace("0","1")) )
read_only.add(vhdl.indent(1) + "check_passed(result(\"Read Out Test Pass.\"));")
read_write.add(vhdl.indent(1) + "check_passed(result(\"Read and Write Test Pass.\"));")
split_read_write.add(vhdl.indent(1) + "check_passed(result(\"Split Read Write Test Pass.\"));")
write_to_clear.add(vhdl.indent(1) + "check_passed(result(\"Write to Clear Test Pass.\"));")
write_to_pulse.add(vhdl.indent(1) + "check_passed(result(\"Write to Pulse Test Pass.\"));")
external_clear.add(vhdl.indent(1) + "check_passed(result(\"External Clear Test Pass.\"));")
new_tb_code = testBenchCode.replace("--read_only_tag",read_only.code(4))
new_tb_code = new_tb_code.replace("--read_write_tag",read_write.code(4))
new_tb_code = new_tb_code.replace("--split_read_write_tag",split_read_write.code(4))
new_tb_code = new_tb_code.replace("--write_to_clear_tag",write_to_clear.code(4))
new_tb_code = new_tb_code.replace("--write_to_pulse_tag",write_to_pulse.code(4))
new_tb_code = new_tb_code.replace("--external_clear_tag",external_clear.code(4))
testbench.architecture.bodyCodeHeader.add(new_tb_code)
testbench.write_file()