class StaticForLoopCntrl(Unit):
"""
.. hwt-schematic::
"""
def _config(self):
self.ITERATIONS = Param(15)
def _declr(self):
addClkRstn(self)
self.cntrl = HandshakeSync()
self.COUNTER_WIDTH = log2ceil(self.ITERATIONS)
self.index = VectSignal(self.COUNTER_WIDTH)._m()
self.body = HandshakeSync()._m()
self.bodyBreak = Signal()
def _impl(self):
ITERATIONS = int(self.ITERATIONS)
"""
Iterates from ITERATIONS -1 to 0 body is enabled by bodyVld and if bodyRd
then counter is decremented for next iteration
break causes reset of counter
"""
counter = self._reg("counter", Bits(self.COUNTER_WIDTH),
ITERATIONS - 1)
If(counter._eq(0), If(self.cntrl.vld, counter(ITERATIONS - 1))).Else(
If(self.body.rd,
If(self.bodyBreak, counter(0)).Else(counter(counter - 1))))
self.cntrl.rd(counter._eq(0))
self.body.vld(counter != 0)
self.index(counter[self.COUNTER_WIDTH:0])
class StaticForLoopCntrl(Unit):
"""
.. hwt-schematic::
"""
def _config(self):
self.ITERATIONS = Param(15)
def _declr(self):
addClkRstn(self)
self.cntrl = HandshakeSync()
self.COUNTER_WIDTH = log2ceil(self.ITERATIONS)
self.index = VectSignal(self.COUNTER_WIDTH)._m()
self.body = HandshakeSync()._m()
self.bodyBreak = Signal()
def _impl(self):
ITERATIONS = int(self.ITERATIONS)
"""
Iterates from ITERATIONS -1 to 0 body is enabled by bodyVld and if bodyRd
then counter is decremented for next iteration
break causes reset of counter
"""
counter = self._reg("counter", Bits(self.COUNTER_WIDTH), ITERATIONS - 1)
If(counter._eq(0),
If(self.cntrl.vld,
counter(ITERATIONS - 1)
)
).Else(
If(self.body.rd,
If(self.bodyBreak,
counter(0)
).Else(
counter(counter - 1)
)
)
)
self.cntrl.rd(counter._eq(0))
self.body.vld(counter != 0)
self.index(counter[self.COUNTER_WIDTH:0])
class FlipCntr(Unit):
"""
Counter with FlipRegister which is form memory with atomic access
interface doFilip drives switching of memories in flip register
dataIn has higher priority than doIncr
.. hwt-autodoc::
"""
def _config(self):
self.DATA_WIDTH = Param(18)
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.doIncr = Signal()
self.doFlip = HandshakeSync()
self.data = RegCntrl()
self.cntr = FlipRegister()
def flipHandler(self):
self.doFlip.rd(1)
flipSt = self._reg("flipState", def_val=0)
If(self.doFlip.vld,
flipSt(~flipSt)
)
self.cntr.select_sig(flipSt)
def dataHanldler(self):
cntr = self.cntr
cntr.first.dout.data(cntr.first.din + 1)
cntr.first.dout.vld(self.doIncr)
cntr.second(self.data)
def _impl(self):
propagateClkRstn(self)
self.flipHandler()
self.dataHanldler()
class FlipCntr(Unit):
"""
Counter with FlipRegister which is form memory with atomic access
interface doFilip drives switching of memories in flip register
dataIn has higher priority than doIncr
.. hwt-schematic::
"""
def _config(self):
self.DATA_WIDTH = Param(18)
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.doIncr = Signal()
self.doFlip = HandshakeSync()
self.data = RegCntrl()
self.cntr = FlipRegister()
def flipHandler(self):
self.doFlip.rd(1)
flipSt = self._reg("flipState", defVal=0)
If(self.doFlip.vld,
flipSt(~flipSt)
)
self.cntr.select_sig(flipSt)
def dataHanldler(self):
cntr = self.cntr
cntr.first.dout.data(cntr.first.din + 1)
cntr.first.dout.vld(self.doIncr)
cntr.second(self.data)
def _impl(self):
propagateClkRstn(self)
self.flipHandler()
self.dataHanldler()