def run(self):
try:
u = get_instance_from_directive_node(self, Unit)
synthesised(u, DEFAULT_PLATFORM)
except Exception as e:
absolute_name = get_absolute_name_of_class_of_node(self.state)
logging.error(e, exc_info=True)
raise Exception(
f"Error occured while processing of {absolute_name:s}")
if not u._units:
return []
description_group_list, obj_list = construct_property_description_list(
'HDL components')
name_to_descr_paragraph = {}
of_type = _('of type')
for p in u._units:
name = p._name
p_p = nodes.paragraph()
p_p += nodes.strong(name, name)
p_p += nodes.Text(f" - {of_type} ")
p_p += ref_to_class(p.__class__)
obj_list += nodes.list_item('', p_p)
name_to_descr_paragraph[name] = p_p
components = hwt_components(name_to_descr_paragraph)
components += description_group_list
self.state.nested_parse(self.content, self.content_offset, components)
return [
components,
]
def get_comb_loops(self, u: Unit):
s = CombLoopAnalyzer()
synthesised(u)
s.visit_Unit(u)
return freeze_set_of_sets(
set(str(member.resolve()[1:]) for member in loop)
for loop in s.report())
def visit_html(self, node):
"""
Generate html elements and schematic json
"""
absolute_name = get_absolute_name_of_class_of_node(node)
constructor_fn_name = node["constructor_fn_name"]
serialno = node["serialno"]
try:
schem_file = SchematicPaths.get_sch_file_name_absolute(
self.document, absolute_name, serialno)
makedirs(path.dirname(schem_file), exist_ok=True)
u = construct_hwt_obj(absolute_name, constructor_fn_name, Unit, "hwt-schematic")
with open(schem_file, "w") as f:
synthesised(u, DEFAULT_PLATFORM)
g = UnitToLNode(u, optimizations=DEFAULT_LAYOUT_OPTIMIZATIONS)
idStore = ElkIdStore()
data = g.toElkJson(idStore)
json.dump(data, f)
viewer = SchematicPaths.get_sch_viewer_link(self.document)
sch_name = SchematicPaths.get_sch_file_name(
self.document, absolute_name, serialno)
ref = nodes.reference(text=_("schematic"), # internal=False,
refuri="%s?schematic=%s" % (
viewer,
path.join(SchematicPaths.SCHEMATIC_DIR_PREFIX,
sch_name)))
node += ref
except Exception as e:
logging.error(e, exc_info=True)
raise Exception(
f"Error occured while processing of {absolute_name:s}")
def test_latch_in_switch(self):
u = LatchInSwitchTest()
ra = ResourceAnalyzer()
synthesised(u)
ra.visit_Unit(u)
res = ra.report()
expected = {(ResourceMUX, 4, 6): 1, ResourceLatch: 4}
self.assertDictEqual(res, expected)
def test_resources_b(self):
u = ListOfInterfacesSample3b()
expected = {}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
self.assertDictEqual(s.report(), expected)
def test_resources(self):
u = SwitchStmUnit()
expected = {(ResourceMUX, 1, 4): 1}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources_SimpleIfStatement3(self):
u = SimpleIfStatement3()
expected = {}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
r = s.report()
self.assertDictEqual(r, expected)
def test_BoolToBits(self):
u = BoolToBitTest()
ra = ResourceAnalyzer()
synthesised(u)
ra.visit_Unit(u)
res = ra.report()
expected = {
(AllOps.EQ, 4): 1,
}
self.assertDictEqual(res, expected)
def test_sync_resources(self):
u = SimpleSyncRam()
expected = {
ResourceRAM(8, 4, 0, 1, 1, 0, 0, 0, 0, 0): 1,
}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
self.assertDictEqual(s.report(), expected)
def test_latch_resources(self):
u = Latch()
expected = {
ResourceLatch: 1,
}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
self.assertDictEqual(s.report(), expected)
def convert(u):
synthesised(u, DEFAULT_PLATFORM)
g = UnitToLNode(u, optimizations=DEFAULT_LAYOUT_OPTIMIZATIONS)
idStore = ElkIdStore()
data = g.toElkJson(idStore)
# import json
# import os
# with open(os.path.join(os.path.dirname(__file__), "..", "..", "d3-hwschematic/examples/schemes/" + u._name + ".json"), "w") as fp:
# json.dump(data, fp, indent=2, sort_keys=True)
# from pprint import pprint
# pprint(data)
return g, data
def test_threeLvlSubUnitsArrIntf(self):
class ThreeSubunits(Unit):
"""a -> u0 -> u1 -> u2 -> b"""
def _config(self):
self.DATA_WIDTH = Param(64)
self.USE_STRB = Param(True)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.a = AxiStream()
self.b0 = AxiStream()._m()
self.b1 = AxiStream()._m()
self.u0 = Simple2withNonDirectIntConnection()
self.u1 = UnitWithArrIntf()
self.u2_0 = Simple2withNonDirectIntConnection()
self.u2_1 = Simple2withNonDirectIntConnection()
def _impl(self):
propagateClkRstn(self)
self.u0.a(self.a)
self.u1.a(self.u0.c)
self.u2_0.a(self.u1.b[0])
self.u2_1.a(self.u1.b[1])
self.b0(self.u2_0.c)
self.b1(self.u2_1.c)
u = ThreeSubunits()
u._loadDeclarations()
u = synthesised(u)
self.assertEqual(count_components(u), 4)
def test_resources_SimpleIfStatement2c(self):
u = SimpleIfStatement2c()
expected = {
(AllOps.AND, 1): 1,
(AllOps.EQ, 1): 1,
(ResourceMUX, 2, 2): 1,
(ResourceMUX, 2, 4): 1,
ResourceFF: 2,
}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
r = s.report()
self.assertDictEqual(r, expected)
def test_GroupOfBlockrams(self):
"""
Check interface directions pre and after synthesis
"""
u = GroupOfBlockrams()
u._loadDeclarations()
u = synthesised(u)
self.assertEqual(count_components(u), 2)
def test_If_solvable_comb_loop(self):
u = If_solvable_comb_loop()
synthesised(u)
b_d = u.b.drivers
c_d = u.c._sigInside.drivers
self.assertEqual(len(b_d), 1)
self.assertEqual(len(c_d), 1)
self.assertIsNot(b_d[0], c_d[0])
self.assertIsNone(b_d[0].parentStm)
self.assertSequenceEqual(b_d[0]._inputs, [u.a._sigInside])
self.assertSequenceEqual(b_d[0]._outputs, [u.b])
self.assertSequenceEqual(b_d[0]._sensitivity, [u.a._sigInside])
self.assertIsNone(c_d[0].parentStm)
self.assertSequenceEqual(c_d[0]._inputs, [u.a._sigInside, u.b])
self.assertSequenceEqual(c_d[0]._outputs, [u.c._sigInside])
self.assertSequenceEqual(c_d[0]._sensitivity, [u.a._sigInside, u.b])
def test_unitWithIntfPartsConnectedSeparately(self):
class FDStreamConnection(Unit):
def _declr(self):
self.dataIn = AxiStreamFullDuplex()
self.dataOut = AxiStreamFullDuplex()._m()
def _impl(self):
self.dataOut.tx(self.dataIn.tx)
self.dataIn.rx(self.dataOut.rx)
u = FDStreamConnection()
u._loadDeclarations()
u = synthesised(u)
fRam[r1](a, fit=True),
self.k(fRam[r1]._unsigned(), fit=True)
)
if __name__ == "__main__": # alias python main function
from pprint import pprint
from hwt.synthesizer.utils import to_rtl_str
from hwt.serializer.hwt import HwtSerializer
from hwt.serializer.vhdl import Vhdl2008Serializer
from hwt.serializer.verilog import VerilogSerializer
from hwt.serializer.systemC import SystemCSerializer
from hwt.serializer.resourceAnalyzer.analyzer import ResourceAnalyzer
from hwt.synthesizer.utils import synthesised
# * new instance has to be created every time because to_rtl_str modifies the unit
# * serializers are using templates which can be customized
# serialized code is trying to be human and git friendly
print(to_rtl_str(Showcase0(), serializer_cls=HwtSerializer))
print(to_rtl_str(Showcase0(), serializer_cls=Vhdl2008Serializer))
print(to_rtl_str(Showcase0(), serializer_cls=VerilogSerializer))
print(to_rtl_str(Showcase0(), serializer_cls=SystemCSerializer))
u = Showcase0()
ra = ResourceAnalyzer()
synthesised(u)
ra.visit_Unit(u)
pprint(ra.report())
def test_subUnitWithArrIntf(self):
u = UnitWithArrIntfParent()
u._loadDeclarations()
u = synthesised(u)
self.assertEqual(count_components(u), 1)
def test_twoSubUnits(self):
u = UnitToUnitConnection()
u._loadDeclarations()
u = synthesised(u)
self.assertEqual(count_components(u), 2)
def _bind_unit(self, u: Unit):
synthesised(u, DEFAULT_PLATFORM)
self.graph = UnitToLNode(u, optimizations=DEFAULT_LAYOUT_OPTIMIZATIONS)
self.json_idStore = ElkIdStore()
self.value = self.graph.toElkJson(self.json_idStore)
