def test_singleGet(self):
u = self.u
t = 5
BASE = 8 * (u.DATA_WIDTH // 8)
MAGIC = 99
INDEX = u.ITEMS - 1
u.base._ag.data.append(BASE)
u.index._ag.data.append(INDEX)
m = AxiDpSimRam(u.DATA_WIDTH, u.clk, rDatapumpIntf=u.rDatapump)
m.data[BASE // 8 + INDEX] = MAGIC
self.runSim(t * CLK_PERIOD)
self.assertValSequenceEqual(u.item._ag.data, [MAGIC, ])
def test_regularUpload2(self):
u = self.u
t = 200
BASE = 0x1020
BASE2 = 0x2020
ITEMS = self.ITEMS_IN_BLOCK * 2
MAGIC = 50
u.baseAddr._ag.dout.append(BASE)
u.rdPtr._ag.dout.append(ITEMS)
m = AxiDpSimRam(self.DATA_WIDTH, u.clk, u.rDatapump, u.wDatapump)
self.spotNextBaseAddr(m, BASE, BASE2)
self.spotNextBaseAddr(m, BASE2, BASE + BASE2)
self.spotNextBaseAddr(m, BASE + BASE2, BASE + BASE2 + BASE)
for i in range(ITEMS):
self.u.dataIn._ag.data.append(i + MAGIC)
self.runSim(t * CLK_PERIOD)
baseIndex = BASE // (self.DATA_WIDTH // 8)
for i in range(ITEMS):
try:
d = m.data[baseIndex + i]
except KeyError: # pragma: no cover
raise AssertionError(f"Invalid data on index {i:d}")
self.assertValEqual(d, i + MAGIC, f"Invalid data on index {i:d}")
def test_randomized2(self):
u = self.u
m = AxiDpSimRam(u.DATA_WIDTH, u.clk, wDatapumpIntf=u.wDatapump)
N = 25
_mask = mask(u.DATA_WIDTH // 8)
for d in u.drivers:
self.randomize(d.req)
self.randomize(d.w)
self.randomize(d.ack)
self.randomize(u.wDatapump.req)
self.randomize(u.wDatapump.w)
self.randomize(u.wDatapump.ack)
sectors = []
framesCnt = [0 for _ in range(self.DRIVER_CNT)]
for i in range(N):
for _id, d in enumerate(u.drivers):
size = self._rand.getrandbits(3) + 1
magic = self._rand.getrandbits(16)
addr = m.calloc(size,
u.DATA_WIDTH // 8,
initValues=[None for _ in range(size)])
d.req._ag.data.append((_id, addr, size - 1, 0))
for i in range(size):
data = (magic + i, _mask, int(i == size - 1))
d.w._ag.data.append(data)
values = [i + magic for i in range(size)]
sectors.append((_id, addr, values))
framesCnt[_id] += 1
self.runSim(self.DRIVER_CNT * N * 250 * Time.ns)
for _id, d in enumerate(u.drivers):
self.assertEmpty(d.req._ag.data)
self.assertEmpty(d.w._ag.data)
self.assertEqual(len(u.drivers[_id].ack._ag.data), framesCnt[_id])
for _id, addr, expected in sectors:
v = m.getArray(addr, u.DATA_WIDTH // 8, len(expected))
self.assertSequenceEqual(v, expected)
def test_randomized(self):
u = self.u
m = AxiDpSimRam(u.DATA_WIDTH, u.clk, wDatapumpIntf=u.wDatapump)
for d in u.drivers:
self.randomize(d.req)
self.randomize(d.w)
self.randomize(d.ack)
self.randomize(u.wDatapump.req)
self.randomize(u.wDatapump.w)
self.randomize(u.wDatapump.ack)
sectors = []
def prepare(driverIndex, addr, size, valBase=1, _id=1):
driver = u.drivers[driverIndex]
driver.req._ag.data.append((_id, addr, size - 1, 0))
_mask = mask(u.DATA_WIDTH // 8)
for i in range(size):
d = (valBase + i, _mask, int(i == size - 1))
driver.w._ag.data.append(d)
u.wDatapump.ack._ag.data.append(driverIndex)
sectors.append((addr, valBase, size))
prepare(0, 0x1000, 3, 99, _id=0)
prepare(0, 0x2000, 1, 100, _id=0)
prepare(0, 0x3000, 16, 101)
prepare(1, 0x4000, 3, 200, _id=1)
prepare(1, 0x5000, 1, 201, _id=1)
# + prepare(1, 0x6000, 16, 202) #+ prepare(1, 0x7000, 16, 203)
self.runSim(2000 * Time.ns)
for addr, seed, size in sectors:
expected = [seed + i for i in range(size)]
self.assertValSequenceEqual(
m.getArray(addr, u.DATA_WIDTH // 8, size), expected)
def test_get(self):
u = self.u
MAGIC = 99
N = u.ITEMS
t = 10 + N
m = AxiDpSimRam(u.DATA_WIDTH, u.clk, rDatapumpIntf=u.rDatapump)
base = m.calloc(u.ITEMS,
u.ITEM_WIDTH // 8,
initValues=[
MAGIC + i
for i in range(N)
])
u.base._ag.data.append(base)
u.index._ag.data.extend([i for i in range(N)])
self.runSim(t * CLK_PERIOD)
self.assertValSequenceEqual(u.item._ag.data,
[
MAGIC + i
for i in range(N)
])
def test_lvl2_fault(self):
u = self.u
MAGIC = 45
m = AxiDpSimRam(u.DATA_WIDTH, u.clk, rDatapumpIntf=u.rDatapump)
addr_bytes = u.ADDR_WIDTH // 8
ADDR_INVALID = mask(u.ADDR_WIDTH)
lvl2pgt = m.calloc(
u.LVL2_PAGE_TABLE_ITEMS,
addr_bytes,
initValues=[ADDR_INVALID for _ in range(u.LVL2_PAGE_TABLE_ITEMS)])
u.lvl1Table._ag.requests.append((WRITE, MAGIC, lvl2pgt))
va = self.buildVirtAddr(MAGIC, 0, 0)
# wait for lvl1Table storage init
u.virtIn._ag.data.extend([NOP, NOP, va])
self.runSim(10 * CLK_PERIOD)
self.assertEmpty(u.physOut._ag.data)
self.assertValEqual(u.segfault._ag.data[-1], 1)
def test_fullFill_randomized3(self, N=None):
u = self.u
BASE = 0x1230
MAGIC = 1
if N is None:
N = self.ITEMS + 10
m = AxiDpSimRam(self.DATA_WIDTH, u.clk, wDatapumpIntf=u.wDatapump)
u.baseAddr._ag.dout.append(BASE)
for i in range(N):
u.items._ag.data.append(MAGIC + i)
def enReq():
u.wDatapump.req._ag.enable = False
yield Timer(32 * CLK_PERIOD)
yield from simpleRandomizationProcess(self, u.wDatapump.req._ag)()
self.procs.append(enReq())
self.randomize(u.wDatapump.w)
self.randomize(u.items)
# self.randomize(u.req)
self.randomize(u.wDatapump.ack)
self.runSim(N * 40 * Time.ns)
self.assertEmpty(u.items._ag.data)
d = m.getArray(BASE, self.DATA_WIDTH // 8, self.ITEMS)
expected = [
i + MAGIC if i >= 10 else i + self.ITEMS + MAGIC
for i in range(self.ITEMS)
]
self.assertValSequenceEqual(d, expected)
self.assertValEqual(u.uploaded._ag.data[-1], N)
def test_downloadFullBlockNextAddrInSeparateReq(self):
u = self.u
N = self.ITEMS_IN_BLOCK + 1
MAGIC = 5896
m = AxiDpSimRam(self.DATA_WIDTH, u.clk, u.rDatapump)
ADDR_BASE, data = self.createBlock(m, MAGIC)
NEXT_BASE, data2 = self.createBlock(m, MAGIC*2)
self.updateNextAddr(m, ADDR_BASE, NEXT_BASE)
u.baseAddr._ag.dout.append(ADDR_BASE)
u.wrPtr._ag.dout.extend([NOP, self.MAX_LEN]
+ [NOP for _ in range(self.MAX_LEN + 4)] + [N])
self.runSim(N * 5 * CLK_PERIOD)
self.assertValSequenceEqual(u.dataOut._ag.data, data + [data2[0]])
def test_downloadFullBlockRandomized(self):
u = self.u
N = self.ITEMS_IN_BLOCK
MAGIC = 6413
m = AxiDpSimRam(self.DATA_WIDTH, u.clk, u.rDatapump)
ADDR_BASE, data = self.createBlock(m, MAGIC)
self.updateNextAddr(m, ADDR_BASE, ADDR_BASE)
self.randomize(u.rDatapump.r)
self.randomize(u.rDatapump.req)
self.randomize(u.dataOut)
u.baseAddr._ag.dout.append(ADDR_BASE)
u.wrPtr._ag.dout.extend([NOP, N])
self.runSim(N * 6 * CLK_PERIOD)
self.assertValSequenceEqual(u.dataOut._ag.data, data)
def test_randomized(self):
u = self.u
m = AxiDpSimRam(u.DATA_WIDTH, u.clk, u.rDatapump)
for d in u.drivers:
self.randomize(d.req)
self.randomize(d.r)
self.randomize(u.rDatapump.req)
self.randomize(u.rDatapump.r)
def prepare(driverIndex, addr, size, valBase=1, _id=1):
driver = u.drivers[driverIndex]
driver.req._ag.data.append((_id, addr, size - 1, 0))
expected = []
_mask = mask(u.DATA_WIDTH // 8)
index = addr // (u.DATA_WIDTH // 8)
for i in range(size):
v = valBase + i
m.data[index + i] = v
d = (_id, v, _mask, int(i == size - 1))
expected.append(d)
return expected
def check(driverIndex, expected):
driverData = u.drivers[driverIndex].r._ag.data
self.assertEqual(len(driverData), len(expected))
for d, e in zip(driverData, expected):
self.assertValSequenceEqual(d, e)
d0 = prepare(0, 0x1000, 3, 99, _id=0)
# + prepare(0, 0x2000, 1, 100, _id=0) + prepare(0, 0x3000, 16, 101)
d1 = prepare(1, 0x4000, 3, 200, _id=1) + prepare(
1, 0x5000, 1, 201, _id=1)
# + prepare(1, 0x6000, 16, 202) #+ prepare(1, 0x7000, 16, 203)
self.runSim(100 * CLK_PERIOD)
check(0, d0)
check(1, d1)
def buildEnv(self, structT):
u = self.u = StructWriter(structT)
u.DATA_WIDTH = 64
self.compileSimAndStart(u)
m = AxiDpSimRam(int(u.DATA_WIDTH), u.clk, wDatapumpIntf=u.wDatapump)
return m