def dataReader(self): yield Timer(1) if self.readPending: yield WaitCombRead() d = self.get_data() self.data.append(d) if self.readPending_invalidate: self.readPending = False if not self.readPending and not self._enabled: self.dataWriter.setEnable(False)
def monitor(self): """ Handle read/write request on this interfaces This method is executed on clock edge. This means that the read data should be put on dout after clock edge. """ intf = self.intf yield WaitCombStable() if self.notReset(): en = intf.en.read() en = int(en) if en: we = intf.we.read() we = int(we) addr = intf.addr.read() if we: data = intf.din.read() self.onWriteReq(addr, data) else: self.onReadReq(addr) if self.requests: req = self.requests.popleft() t = req[0] addr = req[1] if t == READ: v = self.mem.get(addr.val, None) yield Timer(1) yield WaitWriteOnly() intf.dout.write(v) else: assert t == WRITE # yield WaitWriteOnly() # intf.dout.write(None) yield Timer(1) # after clock edge yield WaitWriteOnly() self.mem[addr.val] = req[2]
def dataWriter(self): # delay data litle bit to have nicer wave # otherwise wirte happens before next clk period # and it means in 0 time and we will not be able to see it in wave yield Timer(1) yield WaitWriteOnly() self.set_data(self.lastData) if self.lastData_invalidate: self.lastData = None if not self._enabled: self.dataWriter.setEnable(False)
def tryInsertNotFoundAndLookupIt(): for i in range(N): yield from insertAndCheck(i) expected = [] for h, (k, v) in expected_content.items(): lookup.append(k) expected.append((h, k, v)) yield Timer(len(expected_content) * 3 * t_factor) for (h, k, v) in expected: _hash, key, _, found, occupied = lookupRes.popleft() self.assertValEqual(key, k) self.assertValEqual(_hash, h) self.assertValEqual(found, True) self.assertValEqual(occupied, True)
def get_pull_up_driver_with_reset(sim: HdlSimulator, sig, reset, clk_period): exp_t = 0 yield WaitWriteOnly() sig.write(0) assert sim.now == exp_t while True: yield WaitCombRead() if not reset.read(): assert sim.now == exp_t yield WaitWriteOnly() sig.write(1) return else: yield Timer(clk_period) exp_t += clk_period
def driver(self): """ Drive 'o' and 't' from data buffer. One step if not selfSynchronization else infinite loop. """ while True: yield WaitWriteOnly() if self.data: o = self.data.popleft() if o == NOP: t = 0 o = 0 else: t = 1 self.o.write(o) self.t.write(t) if self.selfSynchronization: yield Timer(CLK_PERIOD) else: break
def monitor(self): # set wait signal # if en == 1 take data intf = self.intf yield WaitWriteOnly() intf.wait.write(0) yield WaitCombStable() # wait for potential update of en en = intf.en.read() try: en = int(en) except ValueError: raise AssertionError(self.sim.now, intf, "en signal in invalid state") if en: yield Timer(CLK_PERIOD // 10) yield WaitCombRead() self.data.append(self.get_data())
def closeOutput(): yield Timer(self.OUT_CLK * 4) u.dataOut._ag.setEnable(False)
def openOutputAfterWile(): u.dataOut._ag.setEnable(False) yield Timer(self.CLK * 9) u.dataOut._ag.setEnable(True)
def pause(): yield Timer(3 * CLK_PERIOD) u.dataOut._ag.setEnable_asMonitor(False) yield Timer(3 * CLK_PERIOD) u.dataOut._ag.setEnable_asMonitor(True)
def planInsert(): # wait because we want to execute clean first yield Timer(3 * CLK_PERIOD) for k, v in sorted(reference.items(), key=lambda x: x[0]): u.insert._ag.data.append((k, v))
def late_add_data(): yield Timer(data_delay) axi.w._ag.data.extend([(MAGIC + i, self.m) for i in range(N)])
def dataInStimul(): yield Timer(3 * CLK_PERIOD) for _ in range(127): yield Timer(CLK_PERIOD) yield WaitWriteOnly() u.dataIn.write(None)
def enReq(): u.wDatapump.req._ag.enable = False yield Timer(32 * CLK_PERIOD) yield from simpleRandomizationProcess(self, u.wDatapump.req._ag)()
def doDelete(): yield Timer(35 * CLK_PERIOD) u.delete._ag.data.extend(toDelete)
def read(): while u.w._ag.data: yield Timer(3 * CLK_PERIOD) yield Timer(5 * CLK_PERIOD) u.r.addr._ag.data.extend([25 + i for i in range(N)])
def sizesEn(): yield Timer((SIZE_BUFF_SIZE + 5) * CLK_PERIOD) yield from simpleRandomizationProcess(self, u.sizes._ag)()
def enDataOut(): u.dataOut._ag.enable = False yield Timer(50 * Time.ns) u.dataOut._ag.enable = True
def data_feed(): for d in test_data: yield WaitWriteOnly() io.inp.write(d) yield Timer(CLK_PERIOD)