def main(): sys = ila.Abstraction("test") r0 = sys.reg('r0', 8) r1 = sys.reg('r1', 8) a = sys.bit('a') b = sys.bit('b') ex = ila.choice("function", r0 + r1, r0 - r1, r0 + r1 + 1) resfoo = sys.syn_elem("sum", ex, foo) assert sys.areEqual(resfoo, r0 + r1) resbar = sys.syn_elem("diff", ex, bar) assert sys.areEqual(resbar, r0 - r1) a1 = ila.choice("a1", a, ~a, a & b, a | b) b1 = ila.choice("b1", [b, ~b, a & b, a | b, a ^ b]) a2 = ila.choice("a2", a, ~a) b2 = ila.choice("b2", b, ~b) t1 = a1 & b1 t2 = a2 & b2 y = t1 | t2 resbaz = sys.syn_elem("baz", y, baz) assert sys.areEqual(resbaz, a ^ b) resshaz = sys.syn_elem("shaz", y, shaz) assert sys.areEqual(resshaz, ~(a ^ b)) c = ila.inrange("cnst", sys.const(0x00, 8), sys.const(0xff, 8)) z = ila.choice("func_z", r0 + r1 + c, r0 + r1 - c) resdaz = sys.syn_elem("daz", z, daz) assert sys.areEqual(resdaz, r0 + r1 + 0x44) slc0 = ila.readslice("r0slice", r0, 4) slc1 = ila.readchunk("r1chunk", r1, 4) res = ila.choice('slice', slc0 + slc1, slc0 - slc1) resrmz = sys.syn_elem("razmatazz", res, razmatazz) assert sys.areEqual(resrmz, r0[3:0] + r1[7:4]) nr0 = ila.writeslice("wr0slice", r0, slc0) resjazz = sys.syn_elem("jazz", nr0, jazz) assert sys.areEqual(resjazz, ila.concat(r0[3:0], r0[3:0])) nr1 = ila.writechunk("wr0chunk", r0, slc0) resjazy = sys.syn_elem("jazz", nr1, jazz) assert sys.areEqual(resjazy, ila.concat(r0[3:0], r0[3:0]))
def createAESILA(enable_ps): m = ila.Abstraction("aes") m.enable_parameterized_synthesis = enable_ps # I/O interface: this is where the commands come from. cmd = m.inp('cmd', 2) cmdaddr = m.inp('cmdaddr', 16) cmddata = m.inp('cmddata', 8) # response. dataout = m.reg('dataout', 8) # internal arch state. state = m.reg('aes_state', 2) opaddr = m.reg('aes_addr', 16) oplen = m.reg('aes_len', 16) keysel = m.reg('aes_keysel', 1) ctr = m.reg('aes_ctr', 128) key0 = m.reg('aes_key0', 128) key1 = m.reg('aes_key1', 128) # for the uinst. xram = m.mem('XRAM', 16, 8) aes = m.fun('aes', 128, [128, 128, 128]) # fetch is just looking at the input command. m.fetch_expr = ila.concat([state, cmd, cmdaddr, cmddata]) m.fetch_valid = (cmd == 1) | (cmd == 2) # decode rdcmds = [(state == i) & (cmd == 1) & (cmdaddr == addr) for addr in xrange(0xff00, 0xff40) for i in [0, 1, 2, 3]] wrcmds = [(state == 0) & (cmd == 2) & (cmdaddr == addr) for addr in xrange(0xff00, 0xff40)] nopcmds = [ ((state != 0) & (cmd != 1)) | ((state == 0) & (cmd != 1) & (cmd != 2)) ] m.decode_exprs = rdcmds + wrcmds + nopcmds # read commands statebyte = ila.zero_extend(state, 8) opaddrbyte = ila.readchunk('rd_addr', opaddr, 8) oplenbyte = ila.readchunk('rd_len', oplen, 8) keyselbyte = ila.zero_extend(keysel, 8) ctrbyte = ila.readchunk('rd_ctr', ctr, 8) key0byte = ila.readchunk('rd_key0', key0, 8) key1byte = ila.readchunk('rd_key1', key1, 8) dataoutnext = ila.choice('dataout', [ statebyte, opaddrbyte, oplenbyte, keyselbyte, ctrbyte, key0byte, key1byte, m.const(0, 8) ]) m.set_next('dataout', dataoutnext) # write commands. def mb_reg_wr(name, reg): # multibyte register write. reg_wr = ila.writechunk('wr_' + name, reg, cmddata) reg_nxt = ila.choice('nxt_' + name, [reg_wr, reg]) m.set_next(name, reg_nxt) mb_reg_wr('aes_addr', opaddr) mb_reg_wr('aes_len', oplen) mb_reg_wr('aes_ctr', ctr) mb_reg_wr('aes_key0', key0) mb_reg_wr('aes_key1', key1) # bit-level registers def bit_reg_wr(name, reg, sz): # bitwise register write assert reg.type.bitwidth == sz reg_wr = cmddata[sz - 1:0] reg_nxt = ila.choice('nxt_' + name, [reg_wr, reg]) m.set_next(name, reg_nxt) bit_reg_wr('aes_keysel', keysel, 1) # these are for the uinst um = m.add_microabstraction('aes_compute', state != 0) # read data rd_data = um.reg('rd_data', 128) enc_data = um.reg('enc_data', 128) byte_cnt = um.reg('byte_cnt', 4) oped_byte_cnt = um.reg('oped_byte_cnt', 16) blk_cnt = um.reg('blk_cnt', 16) um.set_init('byte_cnt', um.const(0, 4)) um.set_init('blk_cnt', um.const(0, 16)) um.set_init('oped_byte_cnt', um.const(0, 16)) uxram = m.getmem('XRAM') byte_cnt_16b = ila.zero_extend(byte_cnt, 16) um.fetch_expr = state um.decode_exprs = [(state == i) & (byte_cnt == j) for j in xrange(16) for i in [1, 2, 3]] usim = lambda s: AESmicro().simMicro(s) # byte_cnt byte_cnt_inc = byte_cnt + 1 byte_cnt_buf = ila.choice('byte_cnt_buf', [byte_cnt_inc, byte_cnt]) byte_cnt_nxt = ila.choice( 'byte_cnt_nxt', [byte_cnt_inc, m.const(0, 4), byte_cnt]) um.set_next('byte_cnt', byte_cnt_nxt) # oped_byte_cnt oped_byte_cnt_inc = oped_byte_cnt + 16 oped_byte_cnt_nxt = ila.choice( 'oped_byte_cnt_nxt', [m.const(0, 16), oped_byte_cnt, oped_byte_cnt_inc]) um.set_next('oped_byte_cnt', oped_byte_cnt_nxt) # blk_cnt blk_cnt_inc = blk_cnt + 16 more_blocks = (oped_byte_cnt_inc < oplen) blk_cnt_nxt = ila.choice('blk_cnt_nxt', [ m.const(0, 16), blk_cnt, blk_cnt_inc, ila.ite(more_blocks, blk_cnt_inc, blk_cnt) ]) um.set_next('blk_cnt', blk_cnt_nxt) # ustate ustate = um.getreg('aes_state') ustate_nxt = ila.choice('ustate_next', [ m.const(0, 2), m.const(1, 2), m.const(2, 2), m.const(3, 2), ustate, ila.ite(more_blocks, m.const(1, 2), m.const(0, 2)) ]) um.set_next('aes_state', ustate_nxt) # rd_data rdblock = ila.writechunk("rd_data_chunk", rd_data, ila.load(uxram, opaddr + blk_cnt + byte_cnt_16b)) rd_data_nxt = ila.choice('rd_data_nxt', rdblock, rd_data) um.set_next('rd_data', rd_data_nxt) # enc_data aes_key = ila.ite(keysel == 0, key0, key1) aes_enc_data = ila.appfun(aes, [ctr, aes_key, rd_data]) enc_data_nxt = ila.ite(state == 2, aes_enc_data, enc_data) um.set_next('enc_data', enc_data_nxt) #print um.get_next('enc_data') # xram write xram_w_data = ila.readchunk('enc_data_chunk', enc_data, 8) xram_w_addr = opaddr + blk_cnt + byte_cnt_16b xram_w_aes = ila.store(uxram, xram_w_addr, xram_w_data) xram_nxt = ila.choice('xram_nxt', uxram, xram_w_aes) um.set_next('XRAM', xram_nxt) suffix = 'en' if enable_ps else 'dis' timefile = open('aes-times-%s.txt' % suffix, 'wt') t_elapsed = 0 # micro-synthesis for s in [ 'XRAM', 'aes_state', 'byte_cnt', 'blk_cnt', 'oped_byte_cnt', 'rd_data' ]: t_elapsed = 0 st = time.clock() um.synthesize(s, usim) dt = time.clock() - st t_elapsed += dt print >> timefile, '%s %.2f' % ('u_' + s, dt) print '%s: %s' % (s, str(um.get_next(s))) ast = um.get_next(s) m.exportOne(ast, 'asts/u_%s_%s' % (s, suffix)) sim = lambda s: AESmacro().simMacro(s) # state state_next = ila.choice( 'state_next', [state, ila.ite(cmddata == 1, m.const(1, 2), state)]) m.set_next('aes_state', state_next) # xram m.set_next('XRAM', xram) # synthesize. for s in [ 'aes_state', 'aes_addr', 'aes_len', 'aes_keysel', 'aes_ctr', 'aes_key0', 'aes_key1', 'dataout' ]: st = time.clock() m.synthesize(s, sim) dt = time.clock() - st t_elapsed += dt print >> timefile, '%s %.2f' % (s, dt) ast = m.get_next(s) print '%s: %s' % (s, str(ast)) m.exportOne(ast, 'asts/%s_%s' % (s, suffix)) # connect to the uinst m.connect_microabstraction('aes_state', um) m.connect_microabstraction('XRAM', um) print 'total time: %.2f' % t_elapsed #print 'aes_state: %s' % str(m.get_next('aes_state')) #print 'XRAM: %s' % str(m.get_next('XRAM')) #m.generateSim('gen/aes_sim.hpp') m.generateSimToDir('sim')
def createRsaIla(): m = ila.Abstraction('rsa') m.enable_parameterized_synthesis = 0 # I/O interface cmd = m.inp('cmd', 2) cmdaddr = m.inp('cmdaddr', 16) cmddata = m.inp('cmddata', 8) # response dataout = m.reg('dataout', 8) # states state = m.reg('rsa_state', 2) addr = m.reg('rsa_addr', 16) rsa_M = m.reg('rsa_M', 2048) rsa_N = m.reg('rsa_N', 2048) rsa_E = m.reg('rsa_E', 2048) rsa_buff = m.reg('rsa_buff', 2048) byte_counter = m.reg('rsa_byte_counter', 8) xram = m.mem('XRAM', 16, 8) rsa = m.fun('rsa', 2048, [2048]) # fetch m.fetch_expr = ila.concat([state, cmd, cmdaddr, cmddata]) m.fetch_valid = (cmd == 1) | (cmd == 2) statebyte = ila.zero_extend(state, 8) wraddrbyte = ila.readchunk('rsa_addr', addr, 8) dataout_nxt = ila.choice('dataout', [statebyte, wraddrbyte, m.const(0, 8)]) m.set_next('dataout', dataout_nxt) # rsa_addr addr_wr = ila.writechunk('wr_addr', addr, cmddata) addr_nxt = ila.choice('nxt_addr', [addr_wr, addr]) m.set_next('rsa_addr', addr_nxt) # rsa_state state_choice = ila.choice( 'state_choice', [m.const(0, 2), m.const(1, 2), m.const(2, 2), m.const(3, 2)]) wr_nxt = ila.ite(byte_counter == 255, m.const(0, 2), m.const(3, 2)) state_nxt = ila.choice('rsa_state_nxt', [ wr_nxt, state_choice, ila.ite(cmddata == 1, m.const(1, 2), state), state ]) m.set_next('rsa_state', state_nxt) # byte_counter byte_counter_inc = byte_counter + 1 byte_counter_rst = ila.ite(cmddata == 1, m.const(0, 8), byte_counter) byte_counter_nxt = ila.choice( 'byte_counter_nxt', [byte_counter_inc, byte_counter_rst, byte_counter]) m.set_next('rsa_byte_counter', byte_counter_nxt) # buff rsa_buff_op = ila.appfun(rsa, [rsa_M]) rsa_buff_nxt = ila.choice('rsa_buff_nxt', rsa_buff_op, rsa_buff) m.set_next('rsa_buff', rsa_buff_nxt) # rsa_M m.set_next('rsa_M', rsa_M) # xram #xram_w_rsa_lit = ila.storeblk (xram, addr, rsa_buff) #xram_w_rsa_big = ila.storeblk_big (xram, addr, rsa_buff) byte_cnt_16 = ila.zero_extend(byte_counter, 16) sh = ila.zero_extend((255 - byte_counter) * 8, 2048) xram_w_rsa_data_1 = (rsa_buff >> sh)[7:0] #xram_w_rsa_data_2 = rsa_buff [255 - byte_cnt_16] xram_w_rsa_lit = ila.store(xram, addr + byte_cnt_16, xram_w_rsa_data_1) xram_nxt = ila.choice('xram_nxt', [xram_w_rsa_lit, xram]) m.set_next('XRAM', xram_nxt) return m
def createSHAILA(synstates, enable_ps): m = ila.Abstraction("sha") m.enable_parameterized_synthesis = enable_ps # I/O interface: this is where commands come from. cmd = m.inp('cmd', 2) cmdaddr = m.inp('cmdaddr', 16) cmddata = m.inp('cmddata', 8) # response. dataout = m.reg('dataout', 8) # internal arch state. state = m.reg('sha_state', 3) rdaddr = m.reg('sha_rdaddr', 16) wraddr = m.reg('sha_wraddr', 16) oplen = m.reg('sha_len', 16) # for the uinst. bytes_read = m.reg('sha_bytes_read', 16) rd_data = m.reg('sha_rd_data', 512) hs_data = m.reg('sha_hs_data', 160) xram = m.mem('XRAM', 16, 8) sha = m.fun('sha', 160, [512]) # fetch is just looking at the input command. m.fetch_expr = ila.concat([state, cmd, cmdaddr, cmddata]) m.fetch_valid = (cmd == 1) | (cmd == 2) # decode rdcmds = [(state == i) & (cmd == 1) & (cmdaddr == addr) for addr in xrange(0xfe00, 0xfe10) for i in [0, 1, 2, 3, 4]] wrcmds = [(state == 0) & (cmd == 2) & (cmdaddr == addr) for addr in xrange(0xfe00, 0xfe10)] nopcmds = [(state == i) & (cmd != 1) & (cmdaddr == addr) for addr in xrange(0xfe00, 0xfe10) for i in [1, 2, 3, 4]] m.decode_exprs = rdcmds + wrcmds + nopcmds # read commands. statebyte = ila.zero_extend(state, 8) rdaddrbyte = ila.readchunk('rd_addr', rdaddr, 8) wraddrbyte = ila.readchunk('wr_addr', wraddr, 8) oplenbyte = ila.readchunk('op_len', oplen, 8) dataoutnext = ila.choice( 'dataout', [statebyte, rdaddrbyte, wraddrbyte, oplenbyte, m.const(0, 8)]) m.set_next('dataout', dataoutnext) # write commands. def mb_reg_wr(name, reg): # multibyte register write. reg_wr = ila.writechunk('wr_' + name, reg, cmddata) reg_nxt = ila.choice('nxt_' + name, [reg_wr, reg]) m.set_next(name, reg_nxt) mb_reg_wr('sha_rdaddr', rdaddr) mb_reg_wr('sha_wraddr', wraddr) mb_reg_wr('sha_len', oplen) # state state_next = ila.choice('state_next', [ m.const(0, 3), m.const(1, 3), m.const(2, 3), m.const(3, 3), m.const(4, 3), ila.ite(cmddata == 1, m.const(1, 3), state), ila.ite(bytes_read < oplen, m.const(1, 3), m.const(4, 3)) ]) m.set_next('sha_state', state_next) # these are for the uinst # bytes_read #bytes_read_inc = ila.ite(bytes_read+64 <= oplen, bytes_read+64, oplen) bytes_read_inc = bytes_read + 64 bytes_read_rst = ila.ite(cmddata == 1, m.const(0, 16), bytes_read) bytes_read_nxt = ila.choice( 'bytes_read_nxt', [m.const(0, 16), bytes_read_inc, bytes_read_rst, bytes_read]) m.set_next('sha_bytes_read', bytes_read_nxt) # rd_data rdblock_little = ila.loadblk(xram, rdaddr + bytes_read, 64) rdblock_big = ila.loadblk_big(xram, rdaddr + bytes_read, 64) rd_data_nxt = ila.choice('rd_data_nxt', rdblock_big, rdblock_little, rd_data) m.set_next('sha_rd_data', rd_data_nxt) # hs_data sha_hs_data = ila.appfun(sha, [rd_data]) hs_data_nxt = ila.choice('hs_data_nxt', sha_hs_data, hs_data) m.set_next('sha_hs_data', hs_data_nxt) # xram write xram_w_sha_little = ila.storeblk(xram, wraddr, hs_data) xram_w_sha_big = ila.storeblk_big(xram, wraddr, hs_data) xram_nxt = ila.choice('xram_nxt', xram, xram_w_sha_little, xram_w_sha_big) m.set_next('XRAM', xram_nxt) suffix = 'en' if enable_ps else 'dis' timefile = open('sha-times-%s.txt' % suffix, 'wt') t_elapsed = 0 # synthesis. sim = lambda s: SHA().simulate(s) for s in synstates: st = time.clock() m.synthesize(s, sim) dt = time.clock() - st print >> timefile, '%s %.2f' % (s, dt) t_elapsed += dt ast = m.get_next(s) m.exportOne(ast, 'asts/%s_%s' % (s, suffix)) print 'time: %.2f' % t_elapsed #m.generateSim('tmp/shasim.hpp') m.generateSimToDir('sim')
def main(): # ila.enablelog("Synthesizer") ila.enablelog("VerilogExport") ila.setloglevel(3,"") sys = ila.Abstraction("test") r0 = sys.reg('r0', 8) r1 = sys.reg('r1', 8) a = sys.bit('a') b = sys.bit('b') out1 = sys.reg('Rsum',8) out2 = sys.reg('Rdiff',8) out3 = sys.bit('Rbaz') out4 = sys.bit('Rshaz') out5 = sys.reg('Rdaz',8) out6 = sys.reg('Rrazmatazz',4) out7 = sys.reg('Rjazz',8) mem = sys.mem('mem1',2,4) action1 = ila.store(mem,r0[1:0],r1[3:0]) action2 = ila.store(mem,r1[1:0],r0[3:0]) action3 = ila.store( ila.store(mem,r0[7:6],r1[7:4]) ,r1[7:6],r0[7:4] ) final_action = ila.ite(a,action1, ila.ite(b,action2,action3)) sys.set_next('mem1',final_action) ex = ila.choice("function", r0+r1, r0-r1, r0+r1+1) resfoo = sys.syn_elem("sum", ex, foo) assert sys.areEqual(resfoo, r0+r1) resbar = sys.syn_elem("diff", ex, bar) assert sys.areEqual(resbar, r0-r1) a1 = ila.choice("a1", a, ~a, a&b, a|b) b1 = ila.choice("b1", [b, ~b, a&b, a|b, a^b]) a2 = ila.choice("a2", a, ~a) b2 = ila.choice("b2", b, ~b) t1 = a1 & b1 t2 = a2 & b2 y = t1 | t2 resbaz = sys.syn_elem("baz", y, baz) assert sys.areEqual(resbaz, a^b) resshaz= sys.syn_elem("shaz", y, shaz) assert sys.areEqual(resshaz, ~(a^b)) c = ila.inrange("cnst", sys.const(0x00,8), sys.const(0xff,8)) z = ila.choice("func_z", r0+r1+c, r0+r1-c) resdaz = sys.syn_elem("daz", z, daz) assert sys.areEqual(resdaz, r0 + r1 + 0x44) slc0 = ila.readslice("r0slice", r0, 4) slc1 = ila.readchunk("r1chunk", r1, 4) res = ila.choice('slice', slc0 + slc1, slc0 - slc1) resrmz = sys.syn_elem("razmatazz", res, razmatazz) assert sys.areEqual(resrmz, r0[3:0]+r1[7:4]) nr0 = ila.writeslice("wr0slice", r0, slc0) resjazz = sys.syn_elem("jazz", nr0, jazz) assert sys.areEqual(resjazz, ila.concat(r0[3:0], r0[3:0])) sys.set_next('Rsum',resfoo) sys.set_next('Rdiff',resbar) sys.set_next('Rbaz',resbaz) sys.set_next('Rshaz',resshaz) sys.set_next('Rdaz',resdaz) sys.set_next('Rrazmatazz',resrmz) sys.set_next('Rjazz',resjazz) sys.generateVerilog(VerilogFile) testVerilog(VerilogFile)
def createAESILA(synstates, enable_ps): m = ila.Abstraction("aes") m.enable_parameterized_synthesis = enable_ps # I/O interface: this is where the commands come from. cmd = m.inp('cmd', 2) cmdaddr = m.inp('cmdaddr', 16) cmddata = m.inp('cmddata', 8) # response. dataout = m.reg('dataout', 8) # internal arch state. state = m.reg('aes_state', 2) opaddr = m.reg('aes_addr', 16) oplen = m.reg('aes_len', 16) keysel = m.reg('aes_keysel', 1) ctr = m.reg('aes_ctr', 128) key0 = m.reg('aes_key0', 128) key1 = m.reg('aes_key1', 128) # for the uinst. byte_cnt = m.reg('byte_cnt', 16) rd_data = m.reg('rd_data', 128) enc_data = m.reg('enc_data', 128) xram = m.mem('XRAM', 16, 8) aes = m.fun('aes', 128, [128, 128, 128]) # fetch is just looking at the input command. m.fetch_expr = ila.concat([state, cmd, cmdaddr, cmddata]) m.fetch_valid = (cmd == 1) | (cmd == 2) # decode rdcmds = [(state == i) & (cmd == 1) & (cmdaddr == addr) for addr in xrange(0xff00, 0xff40) for i in [0, 1, 2, 3]] wrcmds = [(state == 0) & (cmd == 2) & (cmdaddr == addr) for addr in xrange(0xff00, 0xff40)] nopcmds = [(state == i) & (cmd != 1) & (cmdaddr == addr) for addr in xrange(0xff00, 0xff40) for i in [1, 2, 3]] m.decode_exprs = rdcmds + wrcmds + nopcmds # read commands statebyte = ila.zero_extend(state, 8) opaddrbyte = ila.readchunk('rd_addr', opaddr, 8) oplenbyte = ila.readchunk('rd_len', oplen, 8) keyselbyte = ila.zero_extend(keysel, 8) ctrbyte = ila.readchunk('rd_ctr', ctr, 8) key0byte = ila.readchunk('rd_key0', key0, 8) key1byte = ila.readchunk('rd_key1', key1, 8) dataoutnext = ila.choice('dataout', [ statebyte, opaddrbyte, oplenbyte, keyselbyte, ctrbyte, key0byte, key1byte, m.const(0, 8) ]) m.set_next('dataout', dataoutnext) # write commands. def mb_reg_wr(name, reg): # multibyte register write. reg_wr = ila.writechunk('wr_' + name, reg, cmddata) reg_nxt = ila.choice('nxt_' + name, [reg_wr, reg]) m.set_next(name, reg_nxt) mb_reg_wr('aes_addr', opaddr) mb_reg_wr('aes_len', oplen) mb_reg_wr('aes_ctr', ctr) mb_reg_wr('aes_key0', key0) mb_reg_wr('aes_key1', key1) # bit-level registers def bit_reg_wr(name, reg, sz): # bitwise register write assert reg.type.bitwidth == sz reg_wr = cmddata[sz - 1:0] reg_nxt = ila.choice('nxt_' + name, [reg_wr, reg]) m.set_next(name, reg_nxt) bit_reg_wr('aes_keysel', keysel, 1) # state state_next = ila.choice('state_next', [ m.const(0, 2), m.const(1, 2), m.const(2, 2), m.const(3, 2), ila.ite(cmddata == 1, m.const(1, 2), state), ila.ite(byte_cnt + 16 < oplen, m.const(1, 2), m.const(0, 2)) ]) m.set_next('aes_state', state_next) # these are for the uinst # byte_cnt byte_cnt_inc = byte_cnt + 16 byte_cnt_rst = ila.ite(cmddata == 1, m.const(0, 16), byte_cnt) byte_cnt_nxt = ila.choice( 'byte_cnt_nxt', [m.const(0, 16), byte_cnt_inc, byte_cnt_rst, byte_cnt]) m.set_next('byte_cnt', byte_cnt_nxt) # rd_data rdblock = ila.loadblk(xram, opaddr + byte_cnt, 16) rd_data_nxt = ila.choice('rd_data_nxt', rdblock, rd_data) m.set_next('rd_data', rd_data_nxt) # enc_data aes_key = ila.ite(keysel == 0, key0, key1) aes_enc_data = ila.appfun(aes, [ctr, aes_key, rd_data]) enc_data_nxt = ila.ite(state == 2, aes_enc_data, enc_data) m.set_next('enc_data', enc_data_nxt) # xram write xram_w_aes = ila.storeblk(xram, opaddr + byte_cnt, enc_data) xram_nxt = ila.choice('xram_nxt', xram, xram_w_aes) m.set_next('XRAM', xram_nxt) # synthesize. timefile = open('aes-times-%s.txt' % ('en' if enable_ps else 'dis'), 'wt') sim = lambda s: AES().simulate(s) for s in synstates: st = time.clock() m.synthesize(s, sim) t_elapsed = time.clock() - st print >> timefile, s print >> timefile, '%.2f' % (t_elapsed) ast = m.get_next(s) m.exportOne(ast, 'asts/%s_%s' % (s, 'en' if enable_ps else 'dis')) m.generateSimToDir('sim')
def createShaIla(): m = ila.Abstraction("sha") m.enable_parameterized_synthesis = 0 # I/O interface cmd = m.inp('cmd', 2) cmdaddr = m.inp('cmdaddr', 16) cmddata = m.inp('cmddata', 8) # response dataout = m.reg('dataout', 8) # arch states state = m.reg('sha_state', 3) rdaddr = m.reg('sha_rdaddr', 16) wraddr = m.reg('sha_wraddr', 16) oplen = m.reg('sha_len', 16) xram = m.mem('XRAM', 16, 8) # child-ILA states bytes_read = m.reg('sha_bytes_read', 16) rd_data = m.reg('sha_rd_data', 512) hs_data = m.reg('sha_hs_data', 160) sha = m.fun('sha', 160, [512]) # fetch m.fetch_expr = ila.concat([state, cmd, cmdaddr, cmddata]) m.fetch_valid = (cmd == 1) | (cmd == 2) # read commands. statebyte = ila.zero_extend(state, 8) rdaddrbyte = ila.readchunk('rd_addr', rdaddr, 8) wraddrbyte = ila.readchunk('wr_addr', wraddr, 8) oplenbyte = ila.readchunk('op_len', oplen, 8) dataoutnext = ila.choice( 'dataout', [statebyte, rdaddrbyte, wraddrbyte, oplenbyte, m.const(0, 8)]) m.set_next('dataout', dataoutnext) # write commands. def mb_reg_wr(name, reg): reg_wr = ila.writechunk('wr_' + name, reg, cmddata) reg_nxt = ila.choice('nxt_' + name, [reg_wr, reg]) m.set_next(name, reg_nxt) mb_reg_wr('sha_rdaddr', rdaddr) mb_reg_wr('sha_wraddr', wraddr) mb_reg_wr('sha_len', oplen) # state state_choice = ila.choice('state_choice', [ m.const(0, 3), m.const(1, 3), m.const(2, 3), m.const(3, 3), m.const(4, 3) ]) rd_nxt = ila.ite(bytes_read < oplen, m.const(1, 3), m.const(4, 3)) state_nxt = ila.choice('state_nxt', [ rd_nxt, state_choice, ila.ite(cmddata == 1, m.const(1, 3), state), state ]) m.set_next('sha_state', state_nxt) # bytes_read bytes_read_inc = bytes_read + 64 bytes_read_rst = ila.ite(cmddata == 1, m.const(0, 16), bytes_read) bytes_read_nxt = ila.choice( 'bytes_read_nxt', [m.const(0, 16), bytes_read_inc, bytes_read_rst, bytes_read]) m.set_next('sha_bytes_read', bytes_read_nxt) # rd_data rdblock_little = ila.loadblk(xram, rdaddr + bytes_read, 64) rdblock_big = ila.loadblk_big(xram, rdaddr + bytes_read, 64) rd_data_nxt = ila.choice('rd_data_nxt', [rdblock_big, rdblock_little, rd_data]) m.set_next('sha_rd_data', rd_data_nxt) # hs_data sha_hs_data = ila.appfun(sha, [rd_data]) hs_data_nxt = ila.choice('sh_data_nxt', sha_hs_data, hs_data) m.set_next('sha_hs_data', hs_data_nxt) # xram xram_w_sha_little = ila.storeblk(xram, wraddr, hs_data) xram_w_sha_big = ila.storeblk_big(xram, wraddr, hs_data) xram_nxt = ila.choice('xram_nxt', [xram_w_sha_little, xram_w_sha_big, xram]) m.set_next('XRAM', xram_nxt) return m
def createAESILA(enable_ps): m = ila.Abstraction("aes") m.enable_parameterized_synthesis = enable_ps # I/O interface: this is where the commands come from. cmd = m.inp('cmd', 2) cmdaddr = m.inp('cmdaddr', 16) cmddata = m.inp('cmddata', 8) # internal arch state. state = m.reg('aes_state', 2) opaddr = m.reg('aes_addr', 16) oplen = m.reg('aes_len', 16) ctr = m.reg('aes_ctr', 128) key0 = m.reg('aes_key0', 128) # for the uinst. xram = m.mem('XRAM', 16, 8) aes = m.fun('aes', 128, [128, 128, 128]) # fetch is just looking at the input command. m.fetch_expr = ila.concat([cmd, cmdaddr, cmddata ]) # actually, the equivelant instruction m.fetch_valid = (cmd == 2) # when write to some addresses # decode wrcmds = [(cmd == 2) & (cmdaddr == addr) for addr in xrange(0xff00, 0xff30)] # m.decode_exprs = wrcmds um = m.add_microabstraction('aes_compute', state != 0) # write commands. def mb_reg_wr(name, reg): # multibyte register write. reg_wr = ila.writechunk('wr_' + name, reg, cmddata) reg_nxt = ila.choice('nxt_' + name, [reg_wr, reg]) m.set_next(name, reg_nxt) mb_reg_wr('aes_addr', opaddr) mb_reg_wr('aes_len', oplen) mb_reg_wr('aes_ctr', ctr) mb_reg_wr('aes_key0', key0) # state state_next = ila.choice( 'state_next', [state, ila.ite(cmddata == 1, m.const(1, 2), state)]) m.set_next('aes_state', state_next) # xram m.set_next('XRAM', xram) ################################ # Micro-ILA ################################ # read data rd_data = um.reg('rd_data', 128) enc_data = um.reg('enc_data', 128) byte_cnt = um.reg('byte_cnt', 4) oped_byte_cnt = um.reg('oped_byte_cnt', 16) blk_cnt = um.reg('blk_cnt', 16) aes_time = um.reg('aes_time', 5) uaes_ctr = um.reg('uaes_ctr', 128) # change 1 um.set_init('byte_cnt', um.const(0, 4)) um.set_init('blk_cnt', um.const(0, 16)) um.set_init('oped_byte_cnt', um.const(0, 16)) um.set_init('aes_time', um.const(0, 5)) um.set_init('uaes_ctr', m.getreg('aes_ctr')) # change 2 uxram = m.getmem('XRAM') byte_cnt_16b = ila.zero_extend(byte_cnt, 16) um.fetch_expr = state um.decode_exprs = [(state == i) & (byte_cnt == j) for j in xrange(16) for i in [1, 2, 3]] # Decode Expressionss # byte_cnt byte_cnt_inc = byte_cnt + 1 byte_cnt_nxt = ila.choice( 'byte_cnt_nxt', [m.const(0, 4), byte_cnt_inc, byte_cnt]) # 0, +1, NC um.set_next('byte_cnt', byte_cnt_nxt) # oped_byte_cnt oped_byte_cnt_inc = oped_byte_cnt + 16 oped_byte_cnt_nxt = ila.choice( 'oped_byte_cnt_nxt', [m.const(0, 16), oped_byte_cnt_inc, oped_byte_cnt]) # 0, +16, NC um.set_next('oped_byte_cnt', oped_byte_cnt_nxt) # blk_cnt blk_cnt_inc = blk_cnt + 16 more_blocks = (oped_byte_cnt_inc < oplen) blk_cnt_nxt = ila.choice('blk_cnt_nxt', [ m.const(0, 16), blk_cnt, blk_cnt_inc, ila.ite(more_blocks, blk_cnt_inc, blk_cnt) ]) um.set_next('blk_cnt', blk_cnt_nxt) aes_time_inc = aes_time + 1 aes_time_ov = aes_time == m.const(31, 5) aes_time_nxt_c = ila.ite(aes_time_ov, aes_time, aes_time_inc) aes_time_nxt = ila.choice( "aes_timeC", m.const(0, 5), aes_time_nxt_c, ila.ite(more_blocks, m.const(0, 5), aes_time_nxt_c)) aes_time_enough = aes_time > m.const(10, 5) um.set_next('aes_time', aes_time_nxt) # change 3 um.set_next( 'uaes_ctr', ila.choice( 'uaes_ctr_nxt', uaes_ctr, ila.ite( more_blocks, uaes_ctr + ila.inrange('addvalue', um.const(1, 128), um.const(128, 128)), uaes_ctr), ctr)) # ustate ustate = um.getreg('aes_state') ustate_nxt = ila.choice('ustate_next', [ m.const(0, 2), m.const(1, 2), m.const(2, 2), m.const(3, 2), ustate, ila.ite(more_blocks, m.const(1, 2), m.const(0, 2)), ila.ite(aes_time_enough, m.const(3, 2), m.const(2, 2)) ]) # change 4 um.set_next('aes_state', ustate_nxt) # rd_data rdblock = ila.writechunk("rd_data_chunk", rd_data, ila.load(uxram, opaddr + blk_cnt + byte_cnt_16b)) # rd_data_nxt = ila.choice('rd_data_nxt', rdblock, rd_data) um.set_next('rd_data', rd_data_nxt) # enc_data aes_key = key0 aes_ctr = ila.choice('ctr', uaes_ctr, ctr + ila.zero_extend(blk_cnt, 128)) aes_enc_data = ila.appfun(aes, [aes_ctr, aes_key, rd_data]) enc_data_nxt = ila.ite(state == 2, aes_enc_data, enc_data) um.set_next('enc_data', enc_data_nxt) #print um.get_next('enc_data') # xram write xram_w_data = ila.readchunk('enc_data_chunk', enc_data, 8) xram_w_addr = opaddr + blk_cnt + byte_cnt_16b xram_w_aes = ila.store(uxram, xram_w_addr, xram_w_data) xram_nxt = ila.choice('xram_nxt', uxram, xram_w_aes) um.set_next('XRAM', xram_nxt) return m, um