def per_job(job): def get_substs(mode="CLKDIVF", div="2.0", gsr="ENABLED"): if mode == "NONE": comment = "//" else: comment = "" return dict(site=loc, comment=comment, div=div, gsr=gsr) cfg, loc, rc = job cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "clkdiv.ncl" nonrouting.fuzz_enum_setting(cfg, "{}.DIV".format(loc), ["2.0", "3.5"], lambda x: get_substs(div=x), empty_bitfile) nonrouting.fuzz_enum_setting(cfg, "{}.GSR".format(loc), ["ENABLED", "DISABLED"], lambda x: get_substs(gsr=x), empty_bitfile) idx = loc[-1] nets = [ "{}_JCDIVX_CLKDIV{}".format(rc, idx), "{}_CLKI_CLKDIV{}".format(rc, idx), "{}_JRST_CLKDIV{}".format(rc, idx), "{}_JALIGNWD_CLKDIV{}".format(rc, idx), "{}_CLKI{}".format(rc, idx), ] cfg.ncl = "clkdiv_routing.ncl" interconnect.fuzz_interconnect_with_netnames(cfg, nets, bidir=True)
def main(args): pytrellis.load_database("../../../database") cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "osc.ncl" if args.e: nonrouting.fuzz_enum_setting(cfg, "OSCH.STDBY", ["0", "1"], lambda x: get_substs(stdby=x), empty_bitfile) nonrouting.fuzz_enum_setting(cfg, "OSCH.MODE", ["NONE", "OSCH"], lambda x: get_substs(mode=x), empty_bitfile) if args.f: nonrouting.fuzz_enum_setting(cfg, "OSCH.NOM_FREQ", ["{}".format(i) for i in [ 2.08, 2.15, 2.22, 2.29, 2.38, 2.46, 2.56, 2.66, 2.77, 2.89, 3.02, 3.17, 3.33, 3.50, 3.69, 3.91, 4.16, 4.29, 4.43, 4.59, 4.75, 4.93, 5.12, 5.32, 5.54, 5.78, 6.05, 6.33, 6.65, 7.00, 7.39, 7.82, 8.31, 8.58, 8.87, 9.17, 9.50, 9.85, 10.23, 10.64, 11.08, 11.57, 12.09, 12.67, 13.30, 14.00, 14.78, 15.65, 15.65, 16.63, 17.73, 19.00, 20.46, 22.17, 24.18, 26.60, 29.56, 33.25, 38.00, 44.33, 53.20, 66.50, 88.67, 133.00 ]], lambda x: get_substs(nom_freq=x), empty_bitfile) if args.r: cfg_r.setup() interconnect.fuzz_interconnect_with_netnames( cfg_r, ["R1C4_JOSC_OSC", "R1C4_JSTDBY_OSC"], bidir=True, netdir_override={"R1C4_JOSC_OSC" : "driver", "R1C4_JSTDBY_OSC" : "sink"})
def main(): # left_end and right_end are 1200HC-specific. However, the results # also readily apply to 2000HC devices because they also have a # CENTER_EBR_CIB tile (without qualifiers). def left_end(x): return 8 if x % 2 == 0 else 7 def right_end(x): if x == 0 or x == 4: return 18 elif x == 1 or x == 5: return 19 else: return 17 pytrellis.load_database("../../../database") for job in jobs: cfg = job["cfg"] cfg.setup() netnames = [] netnames += [job["left_net"].format(left_end(x), x) for x in range(8)] netnames += [ job["right_net"].format(right_end(x), x) for x in range(8) ] interconnect.fuzz_interconnect_with_netnames( config=cfg, netnames=netnames, netname_filter_union=False)
def main(args): pytrellis.load_database("../../../database") for job in [jobs[i] for i in args.ids]: cfg, netnames = job cfg.setup() interconnect.fuzz_interconnect_with_netnames(config=cfg, netnames=netnames, netname_filter_union=False)
def main(): pytrellis.load_database("../../../database") for job in jobs: cfg = job["cfg"] cfg.setup() netnames = get_sinks(job) interconnect.fuzz_interconnect_with_netnames(config=cfg, netnames=netnames, netname_filter_union=False, full_mux_style=True)
def main(): pytrellis.load_database("../../../database") for job in jobs: cfg = job["cfg"] cfg.setup() netnames = [job["sink_net"].format(x) for x in range(16)] interconnect.fuzz_interconnect_with_netnames(config=cfg, netnames=netnames, netname_filter_union=False)
def per_job(job): cfg, loc, rc = job cfg.setup() def get_substs(mode="DDRDLLA", program={}): if mode == "NONE": comment = "//" else: comment = "" program = ",".join( ["{}={}".format(k, v) for k, v in program.items()]) return dict(site=loc, comment=comment, program=program) empty_bitfile = cfg.build_design(cfg.ncl, {}) if cfg.job.endswith("25k"): cfg.ncl = "ddrdll_25k.ncl" else: cfg.ncl = "ddrdll.ncl" nonrouting.fuzz_enum_setting( cfg, "DDRDLL.MODE", ["NONE", "DDRDLLA"], lambda x: get_substs(mode=x, program=dict(GSR="ENABLED", FORCE_MAX_DELAY =("YES" if x.endswith("YES") else "NO"))), empty_bitfile, False, ignore_cover=["DDRDLLA_NO", "DDRDLLA_YES"]) nonrouting.fuzz_enum_setting(cfg, "DDRDLL.GSR".format(loc), ["ENABLED", "DISABLED"], lambda x: get_substs(program=dict(GSR=x)), empty_bitfile, False) nonrouting.fuzz_enum_setting( cfg, "DDRDLL.FORCE_MAX_DELAY".format(loc), ["NO", "YES"], lambda x: get_substs(program=dict(FORCE_MAX_DELAY=x)), empty_bitfile, False) nets = [ "{}_JCIBCLK0".format(rc), "{}_JDDRDLLCLK".format(rc), "{}_JCLK_DDRDLL".format(rc), "{}_JDIVOSC_DDRDLL".format(rc), "{}_JLOCK_DDRDLL".format(rc), "{}_DDRDEL_DDRDLL".format(rc), "{}_JFREEZE_DDRDLL".format(rc), "{}_JUDDCNTLN_DDRDLL".format(rc), "{}_JRST_DDRDLL".format(rc), ] for i in range(8): nets.append("{}_JDCNTL{}_DDRDLL".format(rc, i)) if cfg.job.endswith("25k"): cfg.ncl = "ddrdll_routing_25k.ncl" else: cfg.ncl = "ddrdll_routing.ncl" interconnect.fuzz_interconnect_with_netnames(cfg, nets, bidir=True)
def main(): pytrellis.load_database("../../../database") cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "cclk.ncl" nonrouting.fuzz_enum_setting(cfg, "CCLK.MODE", ["NONE", "USRMCLK"], lambda x: get_substs(mode=x), empty_bitfile) cfg.ncl = "cclk_routing.ncl" interconnect.fuzz_interconnect_with_netnames( cfg, ["R71C0_JPADDT_CCLK", "R71C0_JPADDO_CCLK", "R71C0_JPADDI_CCLK"], bidir=True)
def main(): pytrellis.load_database("../../../database") cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "dtr.ncl" nonrouting.fuzz_enum_setting(cfg, "DTR.MODE", ["NONE", "DTR"], lambda x: get_substs(mode=x), empty_bitfile) cfg.ncl = "dtr_routing.ncl" interconnect.fuzz_interconnect_with_netnames( cfg, ["R70C22_JSTARTPULSE_DTR"] + ["R70C22_JDTROUT{}_DTR".format(i) for i in range(8)], bidir=True)
def main(args): pytrellis.load_database("../../../database") for job in [jobs[i] for i in args.ids]: cfg = job["cfg"] cfg.setup() interconnect.fuzz_interconnect_with_netnames( config=cfg, netnames=job["netnames"], netname_filter_union=False, netdir_override=job["overrides"], nonlocal_prefix=job["prefix"], fc_predicate=job["fc_filter"])
def main(): pytrellis.load_database("../../../database") cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "osc.ncl" nonrouting.fuzz_enum_setting(cfg, "OSC.MODE", ["NONE", "OSCG"], lambda x: get_substs(mode=x), empty_bitfile) nonrouting.fuzz_enum_setting(cfg, "OSC.DIV", ["{}".format(i) for i in range(2, 128)], lambda x: get_substs(div=x), empty_bitfile) cfg.ncl = "osc_routing.ncl" interconnect.fuzz_interconnect_with_netnames(cfg, ["R70C4_JOSC_OSC"], bidir=True)
def main(args): pytrellis.load_database("../../../database") for job in [jobs[i] for i in args.ids]: cfg = job["cfg"] cfg.setup() if args.i: # Fuzz basic routing, ignore fixed connections to/from I/O pads. interconnect.fuzz_interconnect(config=cfg, location=job["pos"], netname_predicate=job["nn_filter"], netdir_override=defaultdict(lambda : str("ignore")), fc_predicate=fc_filter, netname_filter_union=False, enable_span1_fix=True) if args.m and job["missing_nets"]: interconnect.fuzz_interconnect_with_netnames(config=cfg, netnames=job["missing_nets"], fc_predicate=fc_filter, netname_filter_union=False, bidir=True, netdir_override=defaultdict(lambda : str("ignore"))) if args.p and job["bank"]: # I/O connections in the left/right tiles exist as-if a column "0" # or one past maximum is physically present. if job["bank"].startswith("R"): ab_only = job["bank"].endswith("S") io_nets = mk_nets.io_conns((job["pos"][0], job["pos"][1] + 1), job["bank"], ab_only) elif job["bank"].startswith("L"): ab_only = job["bank"].endswith("S") io_nets = mk_nets.io_conns((job["pos"][0], job["pos"][1] - 1), job["bank"], ab_only) else: io_nets = mk_nets.io_conns((job["pos"][0], job["pos"][1]), job["bank"]) io_list = [io[0] for io in io_nets] override_dict = {io[0]: io[1] for io in io_nets} print(override_dict) interconnect.fuzz_interconnect_with_netnames(config=cfg, netnames=io_list, fc_predicate=fc_filter, netname_filter_union=False, bidir=True, netdir_override=override_dict)
def per_job(job): def get_substs(mode="PCSCLKDIV", program=None): if mode == "NONE": comment = "//" else: comment = "" if program is not None: program = ":::" + ",".join( ["{}={}".format(k, v) for k, v in program.items()]) else: program = ":#ON" return dict(loc=loc, comment=comment, program=program) cfg, loc, rc = job cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "pcsclkdiv.ncl" nonrouting.fuzz_enum_setting( cfg, "{}.MODE".format(loc), ["NONE", "PCSCLKDIV"], lambda x: get_substs(mode=x, program={"GSR": "ENABLED"}), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "{}.GSR".format(loc), ["DISABLED", "ENABLED"], lambda x: get_substs(program={"GSR": x}), empty_bitfile, False) cfg.ncl = "pcsclkdiv_routing.ncl" nets = [ "{}_JRST_{}".format(rc, loc), "{}_JSEL2_{}".format(rc, loc), "{}_JSEL1_{}".format(rc, loc), "{}_JSEL0_{}".format(rc, loc), "{}_CDIV1_{}".format(rc, loc), "{}_CDIVX_{}".format(rc, loc), "{}_CLKI_{}".format(rc, loc), "{}_PCSCDIVI{}".format(rc, loc[-1]), "{}_JPCSCDIVCIB{}".format(rc, loc[-1]), ] interconnect.fuzz_interconnect_with_netnames( cfg, nets, bidir=True, )
def main(): pytrellis.load_database("../../../database") cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "extref.ncl" nonrouting.fuzz_enum_setting( cfg, "EXTREF.MODE", ["NONE", "EXTREFB"], lambda x: get_substs(mode=x, program={ "REFCK_PWDNB": "0b0", "REFCK_RTERM": "0b0", "REFCK_DCBIAS_EN": "0b0" }), empty_bitfile, False) nonrouting.fuzz_word_setting( cfg, "EXTREF.REFCK_PWDNB", 1, lambda x: get_substs(program={"REFCK_PWDNB": tobinstr(x, 1)}), empty_bitfile) nonrouting.fuzz_word_setting( cfg, "EXTREF.REFCK_RTERM", 1, lambda x: get_substs(program={"REFCK_RTERM": tobinstr(x, 1)}), empty_bitfile) nonrouting.fuzz_word_setting( cfg, "EXTREF.REFCK_DCBIAS_EN", 1, lambda x: get_substs(program={"REFCK_DCBIAS_EN": tobinstr(x, 1)}), empty_bitfile) cfg.ncl = "extref_routing.ncl" interconnect.fuzz_interconnect_with_netnames(cfg, [ "R71C42_REFCLKP_EXTREF", "R71C42_INPUT_REFP_APIO", "R71C42_OUTPUT_REFP_APIO", "R71C42_CLK_REFP_APIO", "R71C42_REFCLKN_EXTREF", "R71C42_INPUT_REFN_APIO", "R71C42_OUTPUT_REFN_APIO", "R71C42_CLK_REFN_APIO", "R71C42_JREFCLKO_EXTREF", "R71C42_EXTREFCLK", "R71C42_JTXREFCLKCIB", "R71C42_JCH1RXREFCLKCIB", "R71C42_JCH0RXREFCLKCIB", "R71C42_CH0_RX_REFCLK", "R71C42_CH1_RX_REFCLK", "R71C42_D_REFCLKI", "R71C42_RXREFCLK0", "R71C42_RXREFCLK1", "R71C42_JTXREFCLK" ], bidir=True)
def main(): pytrellis.load_database("../../../database") cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "gsr.ncl" nonrouting.fuzz_enum_setting(cfg, "GSR.GSRMODE", ["NONE", "ACTIVE_LOW", "ACTIVE_HIGH"], lambda x: get_substs(gsrmode=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "GSR.SYNCMODE", ["NONE", "ASYNC", "SYNC"], lambda x: get_substs(syncmode=x), empty_bitfile, False) for rcfg, rc, prefix in [ (FuzzConfig(job="GSR", family="ECP5", device="LFE5U-25F", ncl="gsr_routing_25k.ncl", tiles=["MIB_R50C4:EFB0_PICB0"]), "R49C4", "25K_"), (FuzzConfig(job="GSR", family="ECP5", device="LFE5U-45F", ncl="gsr_routing.ncl", tiles=["MIB_R71C4:EFB0_PICB0"]), "R70C4", "45K_"), (FuzzConfig(job="GSR", family="ECP5", device="LFE5U-85F", ncl="gsr_routing_85k.ncl", tiles=["MIB_R95C4:EFB0_PICB0"]), "R94C4", "85K_"), ]: rcfg.setup() interconnect.fuzz_interconnect_with_netnames( rcfg, ["{}_JGSR_GSR".format(rc), "{}_JCLK_GSR".format(rc)], bidir=True, nonlocal_prefix=prefix)
def main(): pytrellis.load_database("../../../database") cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "jtag.ncl" nonrouting.fuzz_enum_setting(cfg, "JTAG.MODE", ["NONE", "JTAGG"], lambda x: get_substs(mode=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "JTAG.ER1", ["DISABLED", "ENABLED"], lambda x: get_substs(er1=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "JTAG.ER2", ["DISABLED", "ENABLED"], lambda x: get_substs(er2=x), empty_bitfile, False) cfg.ncl = "jtag_routing.ncl" interconnect.fuzz_interconnect_with_netnames(cfg, [ "R70C4_JJTDO1_JTAG", "R70C4_JJTDO2_JTAG", "R70C4_JTCK_JTAG", "R70C4_JTMS_JTAG", "R70C4_JTDI_JTAG", "R70C4_JJTDI_JTAG", "R70C4_JJTCK_JTAG", "R70C4_JJRTI1_JTAG", "R70C4_JJRTI2_JTAG", "R70C4_JJSHIFT_JTAG", "R70C4_JJUPDATE_JTAG", "R70C4_JJRSTN_JTAG", "R70C4_JJCE1_JTAG", "R70C4_JJCE2_JTAG", "R70C4_JTDO_JTAG" ], bidir=True)
def per_job(job): def get_substs(mode="DQSBUFM", program={}, ddrdel="DDRDEL", read="NO", rdloadn="NO", wrloadn="NO", pause="NO"): if mode == "NONE": comment = "//" else: comment = "" program = ",".join( ["{}={}".format(k, v) for k, v in program.items()]) ties = [] if ddrdel != "DDRDEL": ties.append("DDRDEL={}".format(ddrdel)) if read != "YES": ties.append("READ0=0") ties.append("READ1=0") if rdloadn != "YES": ties.append("RDLOADN=0") if wrloadn != "YES": ties.append("WRLOADN=0") if pause != "YES": ties.append("PAUSE=0") if len(ties) > 0: program += ":{}".format(",".join(ties)) return dict(site=loc, comment=comment, program=program) cfg, loc, rc = job cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "dqsbuf.ncl" nonrouting.fuzz_enum_setting( cfg, "DQS.MODE", ["NONE", "DQSBUFM"], lambda x: get_substs(mode=x, program=dict(GSR="ENABLED")), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "DQS.GSR".format(loc), ["ENABLED", "DISABLED"], lambda x: get_substs(program=dict(GSR=x)), empty_bitfile) nonrouting.fuzz_enum_setting( cfg, "DQS.DQS_LI_DEL_ADJ".format(loc), ["PLUS", "MINUS"], lambda x: get_substs(program=dict( DQS_LI_DEL_ADJ=x, DQS_LI_DEL_VAL=(1 if x == "PLUS" else 255))), empty_bitfile) nonrouting.fuzz_enum_setting( cfg, "DQS.DQS_LO_DEL_ADJ".format(loc), ["PLUS", "MINUS"], lambda x: get_substs(program=dict( DQS_LO_DEL_ADJ=x, DQS_LO_DEL_VAL=(1 if x == "PLUS" else 255))), empty_bitfile) nonrouting.fuzz_word_setting( cfg, "DQS.DQS_LI_DEL_VAL".format(loc), 8, lambda x: get_substs(program=dict(DQS_LI_DEL_VAL=todecstr(x))), empty_bitfile) nonrouting.fuzz_word_setting( cfg, "DQS.DQS_LO_DEL_VAL".format(loc), 8, lambda x: get_substs(program=dict(DQS_LO_DEL_VAL=todecstr(x))), empty_bitfile) nonrouting.fuzz_enum_setting(cfg, "DQS.DDRDEL".format(loc), ["DDRDEL", "0"], lambda x: get_substs(ddrdel=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "DQS.READ_USED".format(loc), ["NO", "YES"], lambda x: get_substs(read=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "DQS.RDLOADN_USED".format(loc), ["NO", "YES"], lambda x: get_substs(rdloadn=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "DQS.WRLOADN_USED".format(loc), ["NO", "YES"], lambda x: get_substs(wrloadn=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "DQS.PAUSE_USED".format(loc), ["NO", "YES"], lambda x: get_substs(pause=x), empty_bitfile, False) nets = [ "{}_DQSECLK".format(rc), "{}_JRDDIRECTION_DQS".format(rc), "{}_JRDMOVE_DQS".format(rc), "{}_JRDLOADN_DQS".format(rc), "{}_JWRDIRECTION_DQS".format(rc), "{}_JWRMOVE_DQS".format(rc), "{}_JWRLOADN_DQS".format(rc), "{}_JRST_DQS".format(rc), "{}_JSCLK_DQS".format(rc), "{}_JDQSI_DQS".format(rc), "{}_JREAD0_DQS".format(rc), "{}_JREAD1_DQS".format(rc), "{}_JRDCFLAG_DQS".format(rc), "{}_JWRCFLAG_DQS".format(rc), "{}_JBURSTDET_DQS".format(rc), "{}_JDATAVALID_DQS".format(rc), "{}_JPAUSE_DQS".format(rc), "{}_DDRDEL_DQS".format(rc), "{}_ECLK_DQS".format(rc), "{}_JDQSR90_DQS".format(rc), "{}_JDQSW270_DQS".format(rc), "{}_JDQSW_DQS".format(rc), "{}_DDRDEL".format(rc), ] for i in range(8): nets.append("{}_JDYNDELAY{}_DQS".format(rc, i)) for i in range(3): nets.append("{}_RDPNTR{}_DQS".format(rc, i)) nets.append("{}_WRPNTR{}_DQS".format(rc, i)) nets.append("{}_JREADCLKSEL{}_DQS".format(rc, i)) for i in range(3): nets.append("{}_JREAD{}_DQS".format(rc, i)) cfg.ncl = "dqsbuf_routing.ncl" interconnect.fuzz_interconnect_with_netnames(cfg, nets, bidir=True)
def per_job(job): cfg, locs = job cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) for loc, rc in locs: if loc == "DLLDEL_10": cfg.tiles = list(reversed(cfg.tiles)) def get_substs(mode="DLLDELD", program={}, ddrdel="DDRDEL", loadn="NO"): if mode == "NONE": comment = "//" else: comment = "" program = ",".join( ["{}={}".format(k, v) for k, v in program.items()]) ties = [] if ddrdel != "DDRDEL": ties.append("DDRDEL={}".format(ddrdel)) if loadn != "YES": ties.append("LOADN=0") if len(ties) > 0: program += ":{}".format(",".join(ties)) return dict(site=loc, comment=comment, program=program) cfg.ncl = "dlldel.ncl" nonrouting.fuzz_enum_setting( cfg, "{}.MODE".format(loc), ["NONE", "DLLDELD"], lambda x: get_substs(mode=x, program=dict(DEL_ADJ="PLUS")), empty_bitfile, False) nonrouting.fuzz_enum_setting( cfg, "{}.DEL_ADJ".format(loc), ["PLUS", "MINUS"], lambda x: get_substs(program=dict( DEL_ADJ=x, DEL_VAL=(1 if x == "PLUS" else 255))), empty_bitfile) nonrouting.fuzz_word_setting( cfg, "{}.DEL_VAL".format(loc), 8, lambda x: get_substs(program=dict(DEL_VAL=todecstr(x))), empty_bitfile) nonrouting.fuzz_enum_setting(cfg, "{}.DDRDEL".format(loc), ["DDRDEL", "0"], lambda x: get_substs(ddrdel=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "{}.LOADN_USED".format(loc), ["NO", "YES"], lambda x: get_substs(loadn=x), empty_bitfile, False) nets = [ "{}_JA_DLLDEL".format(rc), "{}_DDRDEL_DLLDEL".format(rc), "{}_DLLDEL".format(rc), "{}_DDRDEL".format(rc), "{}_JCFLAG_DLLDEL".format(rc), "{}_JLOADN_DLLDEL".format(rc), "{}_JMOVE_DLLDEL".format(rc), "{}_JDIRECTION_DLLDEL".format(rc), "{}_Z_DLLDEL".format(rc), "{}_JINCK".format(rc), ] cfg.ncl = "dlldel_routing.ncl" interconnect.fuzz_interconnect_with_netnames(cfg, nets, bidir=True)