def bench_color_trans(): tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) @instance def tbstim(): yield pulse_reset(reset, clock) rgb.data_valid.next = True for i in range(samples): # rgb signal assignment in the dut rgb.red.next = in_out_data.inputs['red'][i] rgb.green.next = in_out_data.inputs['green'][i] rgb.blue.next = in_out_data.inputs['blue'][i] if ycbcr.data_valid == 1: for ycbcr_act, val in zip( ('y', 'cb', 'cr'), (int(ycbcr.y), int(ycbcr.cb), int(ycbcr.cr))): in_out_data.actual_outputs[ycbcr_act].append(val) yield clock.posedge print_results(in_out_data.inputs, in_out_data.expected_outputs, in_out_data.actual_outputs) raise StopSimulation return tbdut, tbclk, tbstim
def bench_color_trans(): tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) @instance def tbstim(): yield pulse_reset(reset, clock) rgb.data_valid.next = True for i in range(samples): # rgb signal assignment in the dut rgb.red.next = in_out_data.inputs['red'][i] rgb.green.next = in_out_data.inputs['green'][i] rgb.blue.next = in_out_data.inputs['blue'][i] if ycbcr.data_valid == 1: for ycbcr_act, val in zip(('y', 'cb', 'cr'), (int(ycbcr.y), int(ycbcr.cb), int(ycbcr.cr))): in_out_data.actual_outputs[ycbcr_act].append(val) yield clock.posedge print_results(in_out_data.inputs, in_out_data.expected_outputs, in_out_data.actual_outputs) raise StopSimulation return tbdut, tbclk, tbstim
def bench_color_trans(): tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) @instance def tbstim(): yield reset.negedge rgb.data_valid.next = True for i in range(samples): # rgb signal assignment in the dut rgb.red.next = in_r[i] rgb.green.next = in_g[i] rgb.blue.next = in_b[i] if ycbcr.data_valid == 1: # expected_outputs signal assignment y_s.next = exp_y[i - 3] cb_s.next = exp_cb[i - 3] cr_s.next = exp_cr[i - 3] yield delay(1) print("Expected outputs ===>Y:%d Cb:%d Cr:%d" % (y_s, cb_s, cr_s)) print("Actual outputs ===>Y:%d Cb:%d Cr:%d" % (ycbcr.y, ycbcr.cb, ycbcr.cr)) print("----------------------------") yield clock.posedge raise StopSimulation return tbdut, tbclk, tbstim, tbrst
def bench_color_trans(): tbdut = rgb2ycbcr(rgb, ycbcr, clock, reset, num_fractional_bits) tbclk = clock_driver(clock) tbrst = reset_on_start(reset, clock) @instance def tbstim(): yield reset.negedge rgb.data_valid.next = True for i in range(samples): # rgb signal assignment in the dut rgb.red.next = in_r[i] rgb.green.next = in_g[i] rgb.blue.next = in_b[i] if ycbcr.data_valid == 1: # expected_outputs signal assignment y_s.next = exp_y[i-3] cb_s.next = exp_cb[i-3] cr_s.next = exp_cr[i-3] yield delay(1) print("Expected outputs ===>Y:%d Cb:%d Cr:%d" % (y_s, cb_s, cr_s)) print("Actual outputs ===>Y:%d Cb:%d Cr:%d" % (ycbcr.y, ycbcr.cb, ycbcr.cr)) print("----------------------------") yield clock.posedge raise StopSimulation return tbdut, tbclk, tbstim, tbrst