def test_zig_zag():
"""Zig Zag Scan MyHDL Test
In this test is verified the correct behavior of the zig zag module
"""
samples, output_bits, N = 5, 10, 8
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
inputs = outputs_2d(output_bits, N)
outputs = outputs_2d(output_bits, N)
in_out_data = InputsAndOutputs(samples, N, output_bits)
in_out_data.initialize()
@block
def bench_zig_zag():
tdut = zig_zag(inputs, outputs, clock, reset, N)
tbclock = clock_driver(clock)
@instance
def tbstim():
yield pulse_reset(reset, clock)
inputs.data_valid.next = True
for i in range(samples):
for j in range(N**2):
inputs.out_sigs[j].next = in_out_data.inputs[i][j]
yield clock.posedge
@instance
def monitor():
outputs_count = 0
yield outputs.data_valid.posedge
yield delay(1)
while(outputs_count != samples):
out_print(in_out_data.outputs[outputs_count],
outputs.out_sigs, N)
yield clock.posedge
yield delay(1)
outputs_count += 1
raise StopSimulation
return tdut, tbclock, tbstim, monitor
run_testbench(bench_zig_zag)
def test_zig_zag():
"""Zig Zag Scan MyHDL Test
In this test is verified the correct behavior of the zig zag module
"""
samples, output_bits, N = 5, 10, 8
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
inputs = outputs_2d(output_bits, N)
outputs = outputs_2d(output_bits, N)
in_out_data = InputsAndOutputs(samples, N, output_bits)
in_out_data.initialize()
@block
def bench_zig_zag():
tdut = zig_zag(inputs, outputs, clock, reset, N)
tbclock = clock_driver(clock)
@instance
def tbstim():
yield pulse_reset(reset, clock)
inputs.data_valid.next = True
for i in range(samples):
for j in range(N**2):
inputs.out_sigs[j].next = in_out_data.inputs[i][j]
yield clock.posedge
@instance
def monitor():
outputs_count = 0
yield outputs.data_valid.posedge
yield delay(1)
while (outputs_count != samples):
out_print(in_out_data.outputs[outputs_count], outputs.out_sigs,
N)
yield clock.posedge
yield delay(1)
outputs_count += 1
raise StopSimulation
return tdut, tbclock, tbstim, monitor
run_testbench(bench_zig_zag)
def test_dct_2d():
"""2D-DCT MyHDL Test
In this test is verified the correct behavior of the 2d-dct module
"""
samples, fract_bits, output_bits, stage_1_prec, N = 5, 14, 10, 10, 8
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
inputs = input_interface()
outputs = outputs_2d(output_bits, N)
in_out_data = InputsAndOutputs(samples, N)
in_out_data.initialize()
@myhdl.block
def bench_dct_2d():
tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, stage_1_prec,
output_bits, N)
tbclock = clock_driver(clock)
@instance
def tbstim():
yield pulse_reset(reset, clock)
inputs.data_valid.next = True
for i in range(samples):
for j in in_out_data.inputs[i]:
for k in j:
inputs.data_in.next = k
yield clock.posedge
@instance
def monitor():
outputs_count = 0
while outputs_count != samples:
yield clock.posedge
yield delay(1)
if outputs.data_valid:
out_print(in_out_data.outputs[outputs_count],
outputs.out_sigs, N)
outputs_count += 1
raise StopSimulation
return tdut, tbclock, tbstim, monitor
run_testbench(bench_dct_2d)
def test_zig_zag_conversion():
"""Convertible Zig Zag Module Test
This is the convertible testbench which ensures that the overall
design is convertible and verified for its correct behavior"""
samples, output_bits, N = 5, 10, 8
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
inputs = outputs_2d(output_bits, N)
outputs = outputs_2d(output_bits, N)
in_out_data = InputsAndOutputs(samples, N, output_bits)
in_out_data.initialize()
inputs_rom, expected_outputs_rom = in_out_data.get_rom_tables()
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
@block
def bench_zig_zag():
tdut = zig_zag(inputs, outputs, clock, reset, N)
tbclock = clock_driver(clock)
tbrst = reset_on_start(reset, clock)
print_sig = [
Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)
]
print_sig_1 = [
Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)
]
in_sigs = [
Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)
]
@instance
def tbstim():
inputs.data_valid.next = True
for i in range(samples):
for j in range(N**2):
in_sigs[j].next = inputs_rom[i * (N**2) + j]
yield clock.posedge
print_assign = assign_array(print_sig_1, outputs.out_sigs)
input_assign = assign_array(inputs.out_sigs, in_sigs)
@instance
def monitor():
outputs_count = 0
yield outputs.data_valid.posedge
yield delay(1)
while (outputs_count != samples):
for i in range(N**2):
print_sig[i].next = expected_outputs_rom[outputs_count *
(N**2) + i]
yield delay(1)
print("Expected Outputs")
for i in range(N**2):
print("%d " % print_sig[i])
print("Actual Outputs")
for i in range(N**2):
print("%d " % print_sig_1[i])
print("------------------------------")
outputs_count += 1
yield clock.posedge
raise StopSimulation
return tdut, tbclock, tbstim, monitor, print_assign, input_assign, tbrst
assert bench_zig_zag().verify_convert() == 0
def test_dct_2d_conversion():
samples, fract_bits, output_bits, stage_1_prec, N = 5, 14, 10, 10, 8
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
inputs = input_interface()
outputs = outputs_2d(output_bits, N)
in_out_data = InputsAndOutputs(samples, N)
in_out_data.initialize()
inputs_rom, expected_outputs_rom = in_out_data.get_rom_tables()
@myhdl.block
def bench_dct_2d():
tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, output_bits,
stage_1_prec, N)
tbclk = clock_driver(clock)
tbrst = reset_on_start(reset, clock)
print_sig = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)]
print_sig_1 = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)]
@instance
def tbstim():
yield reset.negedge
inputs.data_valid.next =True
for i in range(samples * (N**2)):
inputs.data_in.next = inputs_rom[i]
yield clock.posedge
print_assign = outputs.assignment_2(print_sig_1)
@instance
def monitor():
outputs_count = 0
while outputs_count != samples:
yield clock.posedge
if outputs.data_valid:
for i in range(N**2):
print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i]
yield delay(1)
print("Expected Outputs")
for i in range(N**2):
print("%d " % print_sig[i])
print("Actual Outputs")
for i in range(N**2):
print("%d " % print_sig_1[i])
print("------------------------------")
outputs_count += 1
raise StopSimulation
return tdut, tbclk, tbstim, monitor, tbrst, print_assign
# verify and convert with GHDL
verify.simulator = 'ghdl'
assert bench_dct_2d().verify_convert() == 0
# verify and convert with iverilog
verify.simulator = 'iverilog'
assert bench_dct_2d().verify_convert() == 0
def test_dct_2d_conversion():
"""Convertible 2D-DCT Test
This is the convertible testbench which ensures that the overall
design is convertible and verified for its correct behavior"""
samples, fract_bits, output_bits, stage_1_prec, N = 5, 14, 10, 10, 8
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
inputs = input_interface()
outputs = outputs_2d(output_bits, N)
in_out_data = InputsAndOutputs(samples, N)
in_out_data.initialize()
inputs_rom, expected_outputs_rom = in_out_data.get_rom_tables()
@myhdl.block
def bench_dct_2d():
tdut = dct_2d(inputs, outputs, clock, reset, fract_bits, output_bits,
stage_1_prec, N)
tbclk = clock_driver(clock)
tbrst = reset_on_start(reset, clock)
print_sig = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)]
print_sig_1 = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)]
@instance
def tbstim():
yield reset.negedge
inputs.data_valid.next =True
for i in range(samples * (N**2)):
inputs.data_in.next = inputs_rom[i]
yield clock.posedge
print_assign = assign_array(print_sig_1, outputs.out_sigs)
@instance
def monitor():
outputs_count = 0
while outputs_count != samples:
yield clock.posedge
if outputs.data_valid:
for i in range(N**2):
print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i]
yield delay(1)
print("Expected Outputs")
for i in range(N**2):
print("%d " % print_sig[i])
print("Actual Outputs")
for i in range(N**2):
print("%d " % print_sig_1[i])
print("------------------------------")
outputs_count += 1
raise StopSimulation
return tdut, tbclk, tbstim, monitor, tbrst, print_assign
assert bench_dct_2d().verify_convert() == 0
def test_zig_zag_conversion():
"""Convertible Zig Zag Module Test
This is the convertible testbench which ensures that the overall
design is convertible and verified for its correct behavior"""
samples, output_bits, N = 5, 10, 8
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
inputs = outputs_2d(output_bits, N)
outputs = outputs_2d(output_bits, N)
in_out_data = InputsAndOutputs(samples, N, output_bits)
in_out_data.initialize()
inputs_rom, expected_outputs_rom = in_out_data.get_rom_tables()
clock = Signal(bool(0))
reset = ResetSignal(1, active=True, async=True)
@block
def bench_zig_zag():
tdut = zig_zag(inputs, outputs, clock, reset, N)
tbclock = clock_driver(clock)
tbrst = reset_on_start(reset, clock)
print_sig = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)]
print_sig_1 = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)]
in_sigs = [Signal(intbv(0, min=-2**output_bits, max=2**output_bits))
for _ in range(N**2)]
@instance
def tbstim():
inputs.data_valid.next = True
for i in range(samples):
for j in range(N**2):
in_sigs[j].next = inputs_rom[i*(N**2) + j]
yield clock.posedge
print_assign = assign_array(print_sig_1, outputs.out_sigs)
input_assign = assign_array(inputs.out_sigs, in_sigs)
@instance
def monitor():
outputs_count = 0
yield outputs.data_valid.posedge
yield delay(1)
while(outputs_count != samples):
for i in range(N**2):
print_sig[i].next = expected_outputs_rom[outputs_count * (N**2) + i]
yield delay(1)
print("Expected Outputs")
for i in range(N**2):
print("%d " % print_sig[i])
print("Actual Outputs")
for i in range(N**2):
print("%d " % print_sig_1[i])
print("------------------------------")
outputs_count += 1
yield clock.posedge
raise StopSimulation
return tdut, tbclock, tbstim, monitor, print_assign, input_assign, tbrst
assert bench_zig_zag().verify_convert() == 0
def frontend_top_level_v2(inputs, outputs, clock, reset, N=8):
"""Frontend Part of the JPEG Encoder
This part combines the color space conversion, 2D-DCT and zig-zag scan modules.
It takes serially each input pixel (Red, Green, Blue) and when it computes the first block
it takes another two times the same block in order to compute the other components. First
outputs the Y block, then the Cb block and last the Cr block. The processing of this part
is continuous and it never stops.
Inputs:
red, green, blue, data_valid, clock, reset
Outputs:
data_out, data_valid
"""
"""Color Space Conversion"""
rgb2ycbcr_out = YCbCr_v2()
inputs_reg = RGB()
color_space_converter = rgb2ycbcr_v2(inputs_reg, rgb2ycbcr_out, clock,
reset)
"""2D-DCT Transformation"""
dct_2d_input = input_interface()
dct_2d_output = outputs_2d()
dct_2d_inst = dct_2d(dct_2d_input, dct_2d_output, clock, reset)
"""Zig-Zag Module"""
zig_zag_out = outputs_2d()
zig_zag_inst = zig_zag(dct_2d_output, zig_zag_out, clock, reset)
"""Intermediate signals"""
input_counter = Signal(intbv(0, min=0, max=64))
color_mode = Signal(intbv(0, min=0, max=3))
output_counter = Signal(intbv(0, min=0, max=64))
start_out = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def input_reg():
inputs_reg.red.next = inputs.red
inputs_reg.green.next = inputs.green
inputs_reg.blue.next = inputs.blue
inputs_reg.data_valid.next = inputs.data_valid
inputs_reg.color_mode.next = color_mode
@always_seq(clock.posedge, reset=reset)
def color_space_to_dct():
"""signal assignment from color_space_conversion module to dct_2d inputs"""
if rgb2ycbcr_out.data_valid:
dct_2d_input.data_in.next = rgb2ycbcr_out.data_out
dct_2d_input.data_valid.next = rgb2ycbcr_out.data_valid
@always_seq(clock.posedge, reset=reset)
def first_control_signals_update():
"""Is used to update the control signal color_mode for the first mux of the rgb2ycbcr
output to 2d dct"""
if inputs.data_valid:
if input_counter == 63:
input_counter.next = 0
if color_mode == 2:
color_mode.next = 0
else:
color_mode.next = color_mode + 1
else:
input_counter.next = input_counter + 1
@always_comb
def set_start_out():
if zig_zag_out.data_valid:
start_out.next = True
@always_seq(clock.posedge, reset=reset)
def data_valid_assign():
if zig_zag_out.data_valid:
outputs.data_valid.next = zig_zag_out.data_valid
@always_seq(clock.posedge, reset=reset)
def zig_zag_to_output_mux():
"""signal assignment from zig zag to output"""
if start_out:
outputs.data_out.next = zig_zag_out.out_sigs[output_counter]
@always_seq(clock.posedge, reset=reset)
def output_counter_reset():
if start_out:
if output_counter == 63:
output_counter.next = 0
else:
output_counter.next = output_counter + 1
return (color_space_converter, zig_zag_inst, dct_2d_inst,
color_space_to_dct, zig_zag_to_output_mux,
first_control_signals_update, set_start_out, output_counter_reset,
input_reg, data_valid_assign)
def frontend_top_level_v2(inputs, outputs, clock, reset, N=8):
"""Frontend Part of the JPEG Encoder
This part combines the color space conversion, 2D-DCT and zig-zag scan modules.
It takes serially each input pixel (Red, Green, Blue) and when it computes the first block
it takes another two times the same block in order to compute the other components. First
outputs the Y block, then the Cb block and last the Cr block. The processing of this part
is continuous and it never stops.
Inputs:
red, green, blue, data_valid, clock, reset
Outputs:
data_out, data_valid
"""
"""Color Space Conversion"""
rgb2ycbcr_out = YCbCr_v2()
inputs_reg = RGB()
color_space_converter = rgb2ycbcr_v2(inputs_reg, rgb2ycbcr_out, clock, reset)
"""2D-DCT Transformation"""
dct_2d_input = input_interface()
dct_2d_output = outputs_2d()
dct_2d_inst = dct_2d(dct_2d_input, dct_2d_output, clock, reset)
"""Zig-Zag Module"""
zig_zag_out = outputs_2d()
zig_zag_inst = zig_zag(dct_2d_output, zig_zag_out, clock, reset)
"""Intermediate signals"""
input_counter = Signal(intbv(0, min=0, max=64))
color_mode = Signal(intbv(0, min=0, max=3))
output_counter = Signal(intbv(0, min=0, max=64))
start_out = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def input_reg():
inputs_reg.red.next = inputs.red
inputs_reg.green.next = inputs.green
inputs_reg.blue.next = inputs.blue
inputs_reg.data_valid.next = inputs.data_valid
inputs_reg.color_mode.next = color_mode
@always_seq(clock.posedge, reset=reset)
def color_space_to_dct():
"""signal assignment from color_space_conversion module to dct_2d inputs"""
if rgb2ycbcr_out.data_valid:
dct_2d_input.data_in.next = rgb2ycbcr_out.data_out
dct_2d_input.data_valid.next = rgb2ycbcr_out.data_valid
@always_seq(clock.posedge, reset=reset)
def first_control_signals_update():
"""Is used to update the control signal color_mode for the first mux of the rgb2ycbcr
output to 2d dct"""
if inputs.data_valid:
if input_counter == 63:
input_counter.next = 0
if color_mode == 2:
color_mode.next = 0
else:
color_mode.next = color_mode + 1
else:
input_counter.next = input_counter + 1
@always_comb
def set_start_out():
if zig_zag_out.data_valid:
start_out.next = True
@always_seq(clock.posedge, reset=reset)
def data_valid_assign():
if zig_zag_out.data_valid:
outputs.data_valid.next = zig_zag_out.data_valid
@always_seq(clock.posedge, reset=reset)
def zig_zag_to_output_mux():
"""signal assignment from zig zag to output"""
if start_out:
outputs.data_out.next = zig_zag_out.out_sigs[output_counter]
@always_seq(clock.posedge, reset=reset)
def output_counter_reset():
if start_out:
if output_counter == 63:
output_counter.next = 0
else:
output_counter.next = output_counter + 1
return (color_space_converter, zig_zag_inst, dct_2d_inst, color_space_to_dct,
zig_zag_to_output_mux, first_control_signals_update, set_start_out,
output_counter_reset, input_reg, data_valid_assign)