예제 #1
0
def quant_top_block_process(
        clock, control_unit, color, output_interface,
        input_interface, input_val, rom, max_addr, buffer_sel):
    """Processing the block of pixels here"""

    assert isinstance(input_interface, QuantIODataStream)
    assert isinstance(output_interface, QuantIODataStream)
    assert isinstance(control_unit, QuantCtrl)

    # select which component to be processes
    control_unit.color_component.next = color
    yield clock.posedge

    # select the table for quantization
    if control_unit.color_component < 2:
        table = 0
    else:
        table = 1

    # calculate the reference values for the input
    list_ouput_ref = []
    for i in range(max_addr):
        result = divider_ref(input_val[i], rom[i + (max_addr*table)])
        list_ouput_ref.append(int(result))

    # start processing of block
    yield toggle_signal(control_unit.start, clock)

    # send 64 inputs into the module
    # store 64 inputs into the buffer
    for i in range(max_addr):
        input_interface.data.next = input_val[i]
        input_interface.addr.next = buffer_sel*64 + i
        yield clock.posedge

    # output data from the buffer and print them
    for i in range(max_addr):
        output_interface.addr.next = i
        if i >= 2:
            print (" output data is %d" % (output_interface.data))
            #assert list_ouput_ref.pop(0) == output_interface.data
        yield clock.posedge

    # print left outputs
    print (" output data is %d" % (output_interface.data))
    #assert list_ouput_ref.pop(0) == output_interface.data
    yield clock.posedge

    # print left outputs
    print (" output data is %d" % (output_interface.data))
예제 #2
0
def quant_top_block_process(clock, control_unit, color, output_interface,
                            input_interface, input_val, rom, max_addr,
                            buffer_sel):
    """Processing the block of pixels here"""

    assert isinstance(input_interface, QuantIODataStream)
    assert isinstance(output_interface, QuantIODataStream)
    assert isinstance(control_unit, QuantCtrl)

    # select which component to be processes
    control_unit.color_component.next = color
    yield clock.posedge

    # select the table for quantization
    if control_unit.color_component < 2:
        table = 0
    else:
        table = 1

    # calculate the reference values for the input
    list_ouput_ref = []
    for i in range(max_addr):
        result = divider_ref(input_val[i], rom[i + (max_addr * table)])
        list_ouput_ref.append(int(result))

    # start processing of block
    yield toggle_signal(control_unit.start, clock)

    # send 64 inputs into the module
    # store 64 inputs into the buffer
    for i in range(max_addr):
        input_interface.data.next = input_val[i]
        input_interface.addr.next = buffer_sel * 64 + i
        yield clock.posedge

    # output data from the buffer and print them
    for i in range(max_addr):
        output_interface.addr.next = i
        if i >= 2:
            print(" output data is %d" % (output_interface.data))
            #assert list_ouput_ref.pop(0) == output_interface.data
        yield clock.posedge

    # print left outputs
    print(" output data is %d" % (output_interface.data))
    #assert list_ouput_ref.pop(0) == output_interface.data
    yield clock.posedge

    # print left outputs
    print(" output data is %d" % (output_interface.data))
예제 #3
0
def quant_block_process(
        clock, color_component, color, input_q, rom,
        input_interface, output_interface, max_cnt):
    """Processing the block of pixels here"""

    assert isinstance(input_interface, QuantDataStream)
    assert isinstance(output_interface, QuantDataStream)

    # select Y1 or Y2 or Cb or Cr
    color_component.next = color
    yield clock.posedge

    # select the table for quantization
    if color_component < 2:
        table = 0
    else:
        table = 1

    # calculate the reference values for the input
    list_ouput_ref = []
    for i in range(max_cnt):
        result = divider_ref(input_q[i], rom[i + (max_cnt*table)])
        list_ouput_ref.append(int(result))

    # assert input valid signal
    input_interface.data.next = True

    # send 64 input samples into the quantizer core
    for i in range(max_cnt):
        input_interface.data.next = input_q[i]
        input_interface.valid.next = True
        yield clock.posedge
        input_interface.valid.next = False
        # print the outputs
        if output_interface.valid:
            print ("output is %d" % output_interface.data)
            assert list_ouput_ref.pop(0) == output_interface.data

    # de-assert data_valid signal
    input_interface.valid.next = False
    yield clock.posedge

    # print some more outputs
    for i in range(5):
        if output_interface.valid:
            print ("output is %d" % output_interface.data)
            assert list_ouput_ref.pop(0) == output_interface.data
        yield clock.posedge
예제 #4
0
def quant_block_process(clock, color_component, color, input_q, rom,
                        input_interface, output_interface, max_cnt):
    """Processing the block of pixels here"""

    assert isinstance(input_interface, QuantDataStream)
    assert isinstance(output_interface, QuantDataStream)

    # select Y1 or Y2 or Cb or Cr
    color_component.next = color
    yield clock.posedge

    # select the table for quantization
    if color_component < 2:
        table = 0
    else:
        table = 1

    # calculate the reference values for the input
    list_ouput_ref = []
    for i in range(max_cnt):
        result = divider_ref(input_q[i], rom[i + (max_cnt * table)])
        list_ouput_ref.append(int(result))

    # assert input valid signal
    input_interface.data.next = True

    # send 64 input samples into the quantizer core
    for i in range(max_cnt):
        input_interface.data.next = input_q[i]
        input_interface.valid.next = True
        yield clock.posedge
        input_interface.valid.next = False
        # print the outputs
        if output_interface.valid:
            print("output is %d" % output_interface.data)
            assert list_ouput_ref.pop(0) == output_interface.data

    # de-assert data_valid signal
    input_interface.valid.next = False
    yield clock.posedge

    # print some more outputs
    for i in range(5):
        if output_interface.valid:
            print("output is %d" % output_interface.data)
            assert list_ouput_ref.pop(0) == output_interface.data
        yield clock.posedge
예제 #5
0
        def tbstim():
            """Test cases are given here"""

            # reset signal
            yield pulse_reset(reset, clock)

            list_output = []
            list_output_ref = []

            # all the possible tests from -2048 to 2048 given here
            for dividend_temp in range(-2**(width_data), 2**(width_data), 1):
                for divisor_temp in range(0, 256, 1):
                    dividend.next = dividend_temp
                    divisor.next = divisor_temp
                    result = divider_ref(dividend_temp, divisor_temp)
                    list_output_ref.append(result)
                    yield clock.posedge
                    list_output.append(int(quotient))

            yield clock.posedge
            list_output.append(int(quotient))
            yield clock.posedge
            list_output.append(int(quotient))
            yield clock.posedge
            list_output.append(int(quotient))
            yield clock.posedge
            list_output.append(int(quotient))

            # pop the zeroes stored in the list because of pipelining
            list_output.pop(0)
            list_output.pop(0)
            list_output.pop(0)
            list_output.pop(0)

            # compare reference design divider output with that of HDL divider
            for item1, item2 in zip(list_output, list_output_ref):
                print("quotient %d quotient_ref %d" % (item1, item2))
                assert item1 == item2

            raise StopSimulation
예제 #6
0
        def tbstim():
            """Test cases are given here"""

            # reset signal
            yield pulse_reset(reset, clock)

            list_output = []
            list_output_ref = []

            # all the possible tests from -2048 to 2048 given here
            for dividend_temp in range(-2**(width_data), 2**(width_data), 1):
                for divisor_temp in range(0, 256, 1):
                    dividend.next = dividend_temp
                    divisor.next = divisor_temp
                    result = divider_ref(dividend_temp, divisor_temp)
                    list_output_ref.append(result)
                    yield clock.posedge
                    list_output.append(int(quotient))

            yield clock.posedge
            list_output.append(int(quotient))
            yield clock.posedge
            list_output.append(int(quotient))
            yield clock.posedge
            list_output.append(int(quotient))
            yield clock.posedge
            list_output.append(int(quotient))

            # pop the zeroes stored in the list because of pipelining
            list_output.pop(0)
            list_output.pop(0)
            list_output.pop(0)
            list_output.pop(0)

            # compare reference design divider output with that of HDL divider
            for item1, item2 in zip(list_output, list_output_ref):
                print ("quotient %d quotient_ref %d" % (item1, item2))
                assert item1 == item2

            raise StopSimulation