import pytest
import myhdl
from myhdl import (StopSimulation, block, Signal, ResetSignal, intbv,
delay, instance, always_comb, always_seq)
from myhdl.conversion import verify
from jpegenc.subblocks.common import (input_interface, output_interface,
input_1d_2nd_stage, outputs_2d)
from jpegenc.subblocks.dct import dct_2d
from jpegenc.subblocks.dct.dct_2d import dct_2d_transformation
from jpegenc.testing import sim_available, run_testbench
from jpegenc.testing import clock_driver, reset_on_start, pulse_reset
simsok = sim_available('ghdl') and sim_available('iverilog')
class InputsAndOutputs(object):
def __init__(self, samples, N):
self.N = N
self.inputs = []
self.outputs = []
self.samples = samples
def initialize(self):
dct_obj = dct_2d_transformation(self.N)
for i in range(self.samples):
random_matrix = self.random_matrix_8_8()
self.inputs.append(random_matrix)
import numpy as np
import pytest
import myhdl
from myhdl import (StopSimulation, block, Signal, ResetSignal, intbv, delay,
instance, always_comb, always_seq)
from myhdl.conversion import verify
from jpegenc.subblocks.common import outputs_2d, assign_array
from jpegenc.subblocks.zig_zag import zig_zag_scan, zig_zag
from jpegenc.testing import sim_available, run_testbench
from jpegenc.testing import clock_driver, reset_on_start, pulse_reset
from random import randrange
simsok = sim_available('ghdl')
"""default simulator"""
verify.simulator = "ghdl"
class InputsAndOutputs(object):
"""Inputs and Outputs Construction Class
This class is used to create the inputs and the derive the ouputs from the
software reference of the zig zag scan. Each element in the input list is fed in the
test module and the outputs of the module are compared with the elements in the
outputs list. These list are converted to tuples and used as ROMs in the
convertible testbench
"""
def __init__(self, samples, N, precision):
import pytest
import myhdl
from myhdl import (StopSimulation, block, Signal, ResetSignal, intbv,
delay, instance, always_comb, always_seq)
from myhdl.conversion import verify
from jpegenc.subblocks.common import (input_interface, outputs_2d, assign,
assign_array)
from jpegenc.subblocks.dct import dct_2d
from jpegenc.subblocks.dct.dct_2d import dct_2d_transformation
from jpegenc.testing import sim_available, run_testbench
from jpegenc.testing import clock_driver, reset_on_start, pulse_reset
simsok = sim_available('ghdl')
"""default simulator"""
verify.simulator = "ghdl"
class InputsAndOutputs(object):
"""Inputs and Outputs Construction Class
This class is used to create the inputs and the derive the ouputs from the
software reference of the 2d-dct. Each element in the input list is fed in the
test module and the outputs of the module are compared with the elements in the
outputs list. These list are converted to tuples and used as ROMs in the
convertible testbench
"""