from string import Template import os def settings_path(): os.environ["STILDPV_HOME"] = "/cad/Synopsys/TetraMax/E-2010.12-SP2/linux/stildpv/" if __name__ == "__main__": target = "b10" stil_f = target + ".stil" si_f = target + ".test_si" output_f = target + ".xfill_stil" os.chdir(".temp/") # よくわからないファイルが出るので作業ディレクトリの変更 pattern = SortMinTransition.extract_pattern(stil_f) f_pattern = [] with open(si_f, "r") as f: for line in f.readlines(): print(line) f_pattern.append(line.split(" ")[1][:-1]) for i in range(len(f_pattern)): pattern[i]["test_si"] = f_pattern[i] output = SortMinTransition.make_initial(stil_f) output.extend(SortMinTransition.pattern_to_file(pattern)) output.extend(SortMinTransition.make_after(stil_f)) # print(output) with open(output_f, "w") as f:
try: os.mkdir(target) except: pass; # vgファイルから組み合わせ回路を抜き出し,vgファイルに戻す Verilog.convert_verilog_to_json(target + '.vg', output_f= target + '.json') Verilog.extract_comb_circuit_from_verilog_json(target + '.json', target + '.json') Verilog.convert_json_to_verilog(target + '.json', output_f=target + '_comb.vg') before_num = -1 # 開始するパターン数の指定 start_pattern = 545 pattern_num = 0 # scan_inの抽出 for pattern in SortMinTransition.extract_pattern(target + '.stil'): already_fault_stuck = [] script = [] pattern_num += 1 if pattern_num < start_pattern: continue input_pattern = pattern['test_si'].replace('N', 'x') try: os.remove(target + '_comb.stil') except: pass try: os.remove(target + '_test.v') except: pass