def tb(state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht, muxaddrsel, we_1, dout, left_i, sam_i, right_i):
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i, clk, res_o, update_o)
instance_Odd_Even_Fsm = Odd_Even_Fsm (state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht, muxaddrsel, we_1, dout, left_i, sam_i, right_i)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr, addr_in, muxsel_i, muxaddrsel, addr_left, addr_sam, addr_rht)
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
muxsel_i.next = 0
rst_fsm.next = 0
yield clk.posedge
for i in range(4):
yield clk.posedge
rst_fsm.next = 1
yield clk.posedge
for i in range(4):
yield clk.posedge
print ("%d muxsel_i %d rst_fsm %d") % (now(), muxsel_i, rst_fsm)
for i in range(10000):
yield clk.posedge
print ("%d ") % (now())
raise StopSimulation
return instances()
def top_odd_even(state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x,
z, xfifo, zfifo, flgs_i, update_i, res_o, update_o,
end_of_col, empty_r, full_r, enr_r, enw_r, dataout_r,
datain_r, empty_ro, full_ro, enr_ro, enw_ro, dataout_ro,
datain_ro, addr_in, del_ctn):
instance_Odd_Even_Fsm = Odd_Even_Fsm(state, clk, rst_fsm, addr_left,
muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i,
right_i, do_first, x, z, flgs_i,
update_i, res_o, update_o, end_of_col,
addr_in, xfifo, enr_r, enw_r, del_ctn)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr,
addr_in, muxsel_i, muxaddrsel, addr_left,
addr_sam, addr_rht, zfifo)
instance_signed2twoscomplement = signed2twoscomplement(clk, x, z)
instance_signed2twoscomplementfifo = signed2twoscomplement(
clk, xfifo, zfifo)
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i,
clk, res_o, update_o)
instance_pc_in = fifo(clk, empty_r, full_r, enr_r, enw_r, dataout_r,
datain_r)
instance_pc_out = fifo(clk, empty_ro, full_ro, enr_ro, enw_ro, dataout_ro,
datain_ro)
#instance_pd_read = pc_read(clk, data_in, toLift_Step, we_in, addr_in, muxsel_i, datactn_in, datactn, pc_data_in, pc_data_rdy )
return instances()
def top_lift_step(clk, dout, din, data_in, toLift_Step, z, we_1, we, we_in,
addr, addr_in, muxsel_i, x, res_o, left_i, right_i, sam_i,
flgs_i, update_i, update_o, rst_fsm, datactn_in, datactn,
pc_data_in, pc_data_rdy, muxaddrsel, addr_left, addr_sam,
addr_rht):
'''toLift_Step used for mapping datatodut from usb hostio
datatodut is an alias of toSub_s
datactn used for mapping datactn from usb hostio
datactn is an alias of toSub_s'''
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i,
clk, res_o, update_o)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr,
addr_in, muxsel_i, muxaddrsel, addr_left,
addr_sam, addr_rht)
instance_Odd_Even_Fsm = Odd_Even_Fsm(state, clk, rst_fsm, addr_left,
muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i,
right_i)
instance_signed2twoscomplement = signed2twoscomplement(clk, x, z)
instance_pc_read = pc_read(clk, data_in, toLift_Step, we_in, addr_in,
muxsel_i, datactn_in, datactn, pc_data_in,
pc_data_rdy)
return instances()
def top_lift_step(clk, dout, din, data_in, toLift_Step, z,we_1, we, we_in, addr, addr_in, muxsel_i, x, res_o, left_i, right_i, sam_i,flgs_i, update_i, update_o, rst_fsm, datactn_in, datactn, pc_data_in, pc_data_rdy , muxaddrsel, addr_left, addr_sam, addr_rht ): '''toLift_Step used for mapping datatodut from usb hostio datatodut is an alias of toSub_s datactn used for mapping datactn from usb hostio datactn is an alias of toSub_s''' instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i, clk, res_o, update_o) instance_ram = ram(dout, din, addr, we, clk) instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr, addr_in, muxsel_i, muxaddrsel, addr_left, addr_sam, addr_rht) instance_Odd_Even_Fsm = Odd_Even_Fsm( state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht, muxaddrsel, we_1, dout, left_i, sam_i, right_i ) instance_signed2twoscomplement = signed2twoscomplement(clk, x, z) instance_pc_read = pc_read(clk, data_in, toLift_Step, we_in, addr_in, muxsel_i, datactn_in, datactn, pc_data_in, pc_data_rdy ) return instances()
def top_odd_even(state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x, z, xfifo,
zfifo, flgs_i, update_i, res_o, update_o, end_of_col, empty_r, full_r,
enr_r, enw_r, dataout_r, datain_r , empty_ro, full_ro, enr_ro, enw_ro,
dataout_ro, datain_ro, addr_in, del_ctn):
instance_Odd_Even_Fsm = Odd_Even_Fsm (state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht, muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x, z, flgs_i, update_i, res_o, update_o, end_of_col, addr_in, xfifo, enr_r, enw_r, del_ctn)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr, addr_in, muxsel_i, muxaddrsel, addr_left, addr_sam, addr_rht,zfifo)
instance_signed2twoscomplement = signed2twoscomplement(clk, x, z)
instance_signed2twoscomplementfifo = signed2twoscomplement(clk, xfifo, zfifo)
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i, clk, res_o, update_o)
instance_pc_in = fifo(clk, empty_r, full_r, enr_r, enw_r, dataout_r, datain_r)
instance_pc_out = fifo(clk, empty_ro, full_ro, enr_ro, enw_ro, dataout_ro, datain_ro)
#instance_pd_read = pc_read(clk, data_in, toLift_Step, we_in, addr_in, muxsel_i, datactn_in, datactn, pc_data_in, pc_data_rdy )
return instances()
def tb(state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x, z,xfifo,
zfifo, flgs_i, update_i, res_o, update_o, end_of_col, empty_r, full_r,
enr_r, enw_r, dataout_r, datain_r, empty_ro, full_ro, enr_ro, enw_ro,
dataout_ro, datain_ro, addr_in, del_ctn ):
instance_Odd_Even_Fsm = Odd_Even_Fsm (state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht, muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x, z, flgs_i, update_i, res_o, update_o, end_of_col, addr_in, xfifo, enr_r, enw_r, del_ctn)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr, addr_in, muxsel_i, muxaddrsel, addr_left, addr_sam, addr_rht,zfifo)
instance_signed2twoscomplement = signed2twoscomplement(clk, x, z)
instance_signed2twoscomplementfifo = signed2twoscomplement(clk, xfifo, zfifo)
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i, clk, res_o, update_o)
instance_pc_in = fifo(clk, empty_r, full_r, enr_r, enw_r, dataout_r, datain_r)
instance_pc_out = fifo(clk, empty_ro, full_ro, enr_ro, enw_ro, dataout_ro, datain_ro)
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
rst_fsm.next = 0
yield clk.posedge
muxsel_i.next = 0
yield clk.posedge
enr_r.next = 0
yield clk.posedge
enw_r.next = 0
yield clk.posedge
datain_r.next = m[0][0]
yield clk.posedge
enw_r.next = 1
yield clk.posedge
for j in range(1,255):
k = 0
if (full_r == 0):
datain_r.next = m[j][k]
yield clk.posedge
#print ("%d %d %d %d %d") % (now(), j, enw_r, full_r, m[j][k])
enw_r.next = 0
yield clk.posedge
muxsel_i.next = 0
yield clk.posedge
rst_fsm.next = 1
yield clk.posedge
print ("%d muxsel_i %d rst_fsm %d") % (now(), muxsel_i, rst_fsm)
while (end_of_col == 0):
print ("time %d flgs %d left %d sam %d right %d ") % (now(), flgs_i, left_i, sam_i, right_i)
print ("time %d addr %d din %d we %d ") % (now(), addr, din, we)
yield clk.posedge
print ("%d ") % (now())
print "end of col"
muxsel_i.next = 1
yield clk.posedge
rst_fsm.next = 0
yield clk.posedge
addr_in.next = 0
yield clk.posedge
we_in.next = 0
m[0][k] = dout
datain_ro.next= m[0][k]
yield clk.posedge
print ("%d data to ram %d %d") % (now(), datain_ro, addr_in)
addr_in.next = addr_in + 1
yield clk.posedge
enw_ro.next = 1
yield clk.posedge
for j in range(1,254):
m[0][k] = dout
datain_ro.next= m[j][k]
yield clk.posedge
addr_in.next = addr_in + 1
print ("%d data to ram %d %d") % (now(), datain_ro, addr_in)
yield clk.posedge
enw_ro.next = 1
yield clk.posedge
raise StopSimulation
return instances()
def testbench():
res_o = Signal(intbv(0, min=-(2**(W0)), max=(2**(W0))))
left_i = Signal(intbv(0)[W0:])
right_i = Signal(intbv(0)[W0:])
sam_i = Signal(intbv(0)[W0:])
flgs_i = Signal(intbv(0)[4:])
clk = Signal(bool(0))
update_i = Signal(bool(0))
update_o = Signal(bool(0))
lift_step_1 = lift_step(left_i, sam_i, right_i, flgs_i, update_i, clk,
res_o, update_o)
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
update_i.next = 1
left_i.next = 120
right_i.next = 121
sam_i.next = 122
flgs_i.next = 7
yield clk.posedge
update_i.next = 0
yield clk.posedge
for i in range(3):
yield clk.posedge
update_i.next = 1
left_i.next = 120
right_i.next = 121
sam_i.next = 122
flgs_i.next = 5
yield clk.posedge
update_i.next = 0
yield clk.posedge
for i in range(3):
yield clk.posedge
update_i.next = 1
left_i.next = 10
right_i.next = 11
sam_i.next = 12
flgs_i.next = 6
yield clk.posedge
update_i.next = 0
yield clk.posedge
for i in range(3):
yield clk.posedge
update_i.next = 1
left_i.next = 10
right_i.next = 11
sam_i.next = 12
flgs_i.next = 4
yield clk.posedge
update_i.next = 0
yield clk.posedge
for i in range(3):
yield clk.posedge
update_i.next = 1
left_i.next = 10
right_i.next = 11
sam_i.next = 2
flgs_i.next = 7
yield clk.posedge
update_i.next = 0
yield clk.posedge
for i in range(3):
yield clk.posedge
update_i.next = 1
left_i.next = 10
right_i.next = 11
sam_i.next = 22
flgs_i.next = 5
yield clk.posedge
update_i.next = 0
yield clk.posedge
for i in range(3):
yield clk.posedge
update_i.next = 1
left_i.next = 10
right_i.next = 11
sam_i.next = 17
flgs_i.next = 6
yield clk.posedge
update_i.next = 0
yield clk.posedge
for i in range(3):
yield clk.posedge
update_i.next = 1
left_i.next = 10
right_i.next = 11
sam_i.next = 7
flgs_i.next = 4
yield clk.posedge
update_i.next = 0
yield clk.posedge
for i in range(3):
yield clk.posedge
raise StopSimulation()
return lift_step_1, clkgen, stimulus
def tb(clk, dout, din, data_in, toLift_Step, z, we_1, we, we_in, addr_1, addr, addr_in, muxsel_i, x, res_o, left_i, right_i, sam_i, flgs_i, update_i, update_o, rst_fsm, datactn_in, datactn, pc_data_in, pc_data_rdy):
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i, clk, res_o, update_o)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr, addr_in, muxsel_i, muxaddrsel, addr_left, addr_sam, addr_rht)
instance_signed2twoscomplement = signed2twoscomplement(clk, x, z)
instance_pc_read = pc_read(clk, data_in, toLift_Step, we_in, addr_in, muxsel_i, datactn_in, datactn, pc_data_in, pc_data_rdy )
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
dummy = 100000
muxsel_i.next = 0
while(muxsel_i == 0):
print( "%d wait for data ") % (now() )
yield clk.posedge
dummy = dummy - 1
if ( dummy == 0):
muxsel_i.next = 1
yield clk.posedge
i = 0
j = 0
print( "%d at start ") % (now() )
while(muxsel_i == 1):
toLift_Step.next = m[j][i]
yield clk.posedge
print( "%d addr %d, data %d") % (now(), addr_in , data_in)
#yield clk.posedge
j = j + 1
print ("%d pc_read done") % (now())
we_1.next = 0
flgs_i.next = 7
yield clk.posedge
for i in range(w):
for j in range(1, h-1,2):
we_1.next = 0
yield clk.posedge
flgs_i.next = 7
yield clk.posedge
addr_1.next = j - 1
yield clk.posedge
left_i.next = dout
yield clk.posedge
addr_1.next = j + 1
yield clk.posedge
right_i.next = dout
yield clk.posedge
addr_1.next = j
yield clk.posedge
sam_i.next = dout
yield clk.posedge
we_1.next = 1
yield clk.posedge
print( "time %d ") % (now())
print( "left %d sam %d right %d") % (left_i, sam_i, right_i)
update_i.next = 1
yield clk.posedge
update_i.next = 0
yield clk.posedge
x.next = res_o[W0:]
yield clk.posedge
#m[j][i] = z
print( "time %d") % (now())
print( "j %d i %d z %d") % (j, i, z)
yield clk.posedge
flgs_i.next = 6
for i in range(w):
for j in range(2, h, 2):
addr_1.next = j
yield clk.posedge
left_i.next = m[j - 1][i]
yield clk.posedge
right_i.next = m[j + 1][i]
yield clk.posedge
sam_i.next = m[j][i]
yield clk.posedge
print( "time %d ") % (now())
print( "left %d sam %d right %d") % (left_i, sam_i, right_i)
update_i.next = 1
yield clk.posedge
update_i.next = 0
yield clk.posedge
x.next = res_o[W0:]
yield clk.posedge
m[j][i] = z
yield clk.posedge
raise StopSimulation
return instances()
def testbench(state, clk, rst_fsm, addr_left, muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i, right_i, do_first, x, z,
xfifo, zfifo, flgs_i, update_i, res_o, update_o, end_of_col,
empty_r, full_r, enr_r, enw_r, dataout_r, datain_r, empty_ro,
full_ro, enr_ro, enw_ro, dataout_ro, datain_ro, addr_in,
del_ctn):
instance_Odd_Even_Fsm = Odd_Even_Fsm(state, clk, rst_fsm, addr_left,
muxsel_i, addr_sam, addr_rht,
muxaddrsel, we_1, dout, left_i, sam_i,
right_i, do_first, x, z, flgs_i,
update_i, res_o, update_o, end_of_col,
addr_in, xfifo, enr_r, enw_r, del_ctn)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr,
addr_in, muxsel_i, muxaddrsel, addr_left,
addr_sam, addr_rht, zfifo)
instance_signed2twoscomplement = signed2twoscomplement(clk, x, z)
instance_signed2twoscomplementfifo = signed2twoscomplement(
clk, xfifo, zfifo)
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i,
clk, res_o, update_o)
instance_pc_in = fifo(clk, empty_r, full_r, enr_r, enw_r, dataout_r,
datain_r)
instance_pc_out = fifo(clk, empty_ro, full_ro, enr_ro, enw_ro, dataout_ro,
datain_ro)
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
rst_fsm.next = 0
yield clk.posedge
muxsel_i.next = 0
yield clk.posedge
enr_r.next = 0
yield clk.posedge
enw_r.next = 0
yield clk.posedge
datain_r.next = m[0][0]
yield clk.posedge
enw_r.next = 1
yield clk.posedge
for j in range(1, 255):
k = 0
if (full_r == 0):
datain_r.next = m[j][k]
yield clk.posedge
#print ("%d %d %d %d %d") % (now(), j, enw_r, full_r, m[j][k])
enw_r.next = 0
yield clk.posedge
muxsel_i.next = 0
yield clk.posedge
rst_fsm.next = 1
yield clk.posedge
print("%d muxsel_i %d rst_fsm %d") % (now(), muxsel_i, rst_fsm)
while (end_of_col == 0):
print("time %d flgs %d left %d sam %d right %d ") % (
now(), flgs_i, left_i, sam_i, right_i)
print("time %d addr %d din %d we %d ") % (now(), addr, din, we)
yield clk.posedge
print("%d ") % (now())
print "end of col"
muxsel_i.next = 1
yield clk.posedge
rst_fsm.next = 0
yield clk.posedge
addr_in.next = 0
yield clk.posedge
we_in.next = 0
m[0][k] = dout
datain_ro.next = m[0][k]
yield clk.posedge
print("%d data to ram %d %d") % (now(), datain_ro, addr_in)
addr_in.next = addr_in + 1
yield clk.posedge
enw_ro.next = 1
yield clk.posedge
for j in range(1, 254):
m[0][k] = dout
datain_ro.next = m[j][k]
yield clk.posedge
addr_in.next = addr_in + 1
print("%d data to ram %d %d") % (now(), datain_ro, addr_in)
yield clk.posedge
enw_ro.next = 1
yield clk.posedge
raise StopSimulation
return instances()
def testbench(clk, dout, din, data_in, toLift_Step, z, we_1, we, we_in, addr_1,
addr, addr_in, muxsel_i, x, res_o, left_i, right_i, sam_i,
flgs_i, update_i, update_o, rst_fsm, datactn_in, datactn,
pc_data_in, pc_data_rdy):
instance_lift_step = lift_step(left_i, sam_i, right_i, flgs_i, update_i,
clk, res_o, update_o)
instance_ram = ram(dout, din, addr, we, clk)
instance_mux_data = mux_data(z, din, data_in, we_1, we, we_in, addr,
addr_in, muxsel_i, muxaddrsel, addr_left,
addr_sam, addr_rht, zfifo)
instance_signed2twoscomplement = signed2twoscomplement(clk, x, z)
instance_pc_read = pc_read(clk, data_in, toLift_Step, we_in, addr_in,
muxsel_i, datactn_in, datactn, pc_data_in,
pc_data_rdy)
@always(delay(10))
def clkgen():
clk.next = not clk
@instance
def stimulus():
dummy = 100000
muxsel_i.next = 0
while (muxsel_i == 0):
print("%d wait for data ") % (now())
yield clk.posedge
dummy = dummy - 1
if (dummy == 0):
muxsel_i.next = 1
yield clk.posedge
i = 0
j = 0
print("%d at start ") % (now())
while (muxsel_i == 1):
toLift_Step.next = m[j][i]
yield clk.posedge
print("%d addr %d, data %d") % (now(), addr_in, data_in)
#yield clk.posedge
j = j + 1
print("%d pc_read done") % (now())
we_1.next = 0
flgs_i.next = 7
yield clk.posedge
for i in range(w):
for j in range(1, h - 1, 2):
we_1.next = 0
yield clk.posedge
flgs_i.next = 7
yield clk.posedge
addr_1.next = j - 1
yield clk.posedge
left_i.next = dout
yield clk.posedge
addr_1.next = j + 1
yield clk.posedge
right_i.next = dout
yield clk.posedge
addr_1.next = j
yield clk.posedge
sam_i.next = dout
yield clk.posedge
we_1.next = 1
yield clk.posedge
print("time %d ") % (now())
print("left %d sam %d right %d") % (left_i, sam_i, right_i)
update_i.next = 1
yield clk.posedge
update_i.next = 0
yield clk.posedge
x.next = res_o[W0:]
yield clk.posedge
#m[j][i] = z
print("time %d") % (now())
print("j %d i %d z %d") % (j, i, z)
yield clk.posedge
flgs_i.next = 6
for i in range(w):
for j in range(2, h, 2):
addr_1.next = j
yield clk.posedge
left_i.next = m[j - 1][i]
yield clk.posedge
right_i.next = m[j + 1][i]
yield clk.posedge
sam_i.next = m[j][i]
yield clk.posedge
print("time %d ") % (now())
print("left %d sam %d right %d") % (left_i, sam_i, right_i)
update_i.next = 1
yield clk.posedge
update_i.next = 0
yield clk.posedge
x.next = res_o[W0:]
yield clk.posedge
m[j][i] = z
yield clk.posedge
raise StopSimulation
return instances()