def __init__(self,
user_data_width,
native_data_width,
mem_depth,
separate_rw=True,
read_latency=0):
self.separate_rw = separate_rw
if separate_rw:
self.write_user_port = LiteDRAMNativeWritePort(
address_width=32, data_width=user_data_width)
self.write_crossbar_port = LiteDRAMNativeWritePort(
address_width=32, data_width=native_data_width)
self.read_user_port = LiteDRAMNativeReadPort(
address_width=32, data_width=user_data_width)
self.read_crossbar_port = LiteDRAMNativeReadPort(
address_width=32, data_width=native_data_width)
self.write_driver = NativePortDriver(self.write_user_port)
self.read_driver = NativePortDriver(self.read_user_port)
else:
self.write_user_port = LiteDRAMNativePort(
mode="both", address_width=32, data_width=user_data_width)
self.write_crossbar_port = LiteDRAMNativePort(
mode="both", address_width=32, data_width=native_data_width)
self.write_driver = NativePortDriver(self.write_user_port)
self.read_user_port = self.write_user_port
self.read_crossbar_port = self.write_crossbar_port
self.read_driver = self.write_driver
self.driver_generators = [
self.write_driver.write_data_handler(),
self.read_driver.read_data_handler(latency=read_latency)
]
# Memory
self.memory = DRAMMemory(native_data_width, mem_depth)
def __init__(self, user_data_width, native_data_width, mem_depth):
self.write_user_port = LiteDRAMNativeWritePort(address_width=32, data_width=user_data_width)
self.write_crossbar_port = LiteDRAMNativeWritePort(address_width=32, data_width=native_data_width)
self.read_user_port = LiteDRAMNativeReadPort( address_width=32, data_width=user_data_width)
self.read_crossbar_port = LiteDRAMNativeReadPort( address_width=32, data_width=native_data_width)
# Memory
self.memory = DRAMMemory(native_data_width, mem_depth)
def test_fifo_default_thresholds(self):
# Verify FIFO with default threshold.
# Defaults: read_threshold=0, write_threshold=depth
read_threshold, write_threshold = (0, 128)
write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
fifo = LiteDRAMFIFO(data_width=32,
base=0,
depth=write_threshold,
write_port=write_port,
read_port=read_port)
def generator():
yield write_port.cmd.ready.eq(1)
yield write_port.wdata.ready.eq(1)
for i in range(write_threshold):
yield fifo.sink.valid.eq(1)
yield fifo.sink.data.eq(0)
yield
while (yield fifo.sink.ready) == 0:
yield
yield
checker = self.fifo_ctrl_flag_checker(fifo.ctrl, write_threshold,
read_threshold)
run_simulation(fifo, [generator(), checker])
def __init__(self):
self.port = LiteDRAMNativeWritePort(address_width=32,
data_width=32)
ctrl = _LiteDRAMFIFOCtrl(base=8, depth=depth)
self.submodules.ctrl = ctrl
writer = _LiteDRAMFIFOWriter(data_width=32,
port=self.port,
ctrl=ctrl)
self.submodules.writer = writer
self.memory = DRAMMemory(32, 128)
assert 8 + sequence_len <= len(self.memory.mem)
def __init__(self, user_data_width, native_data_width):
# write port and converter
self.write_user_port = LiteDRAMNativeWritePort(
address_width=32, data_width=user_data_width)
self.write_crossbar_port = LiteDRAMNativeWritePort(
address_width=32, data_width=native_data_width)
write_converter = LiteDRAMNativePortConverter(self.write_user_port,
self.write_crossbar_port)
self.submodules += write_converter
# read port and converter
self.read_user_port = LiteDRAMNativeReadPort(
address_width=32, data_width=user_data_width)
self.read_crossbar_port = LiteDRAMNativeReadPort(
address_width=32, data_width=native_data_width)
read_converter = LiteDRAMNativePortConverter(self.read_user_port,
self.read_crossbar_port)
self.submodules += read_converter
# memory
self.memory = DRAMMemory(native_data_width, 128)
def __init__(self):
self.write_port = LiteDRAMNativeWritePort(address_width=32,
data_width=32)
self.read_port = LiteDRAMNativeReadPort(address_width=32,
data_width=32)
self.submodules.fifo = LiteDRAMFIFO(data_width=32,
depth=32,
base=16,
write_port=self.write_port,
read_port=self.read_port,
read_threshold=8,
write_threshold=32 - 8)
self.memory = DRAMMemory(32, 128)
def __init__(self, base, depth, data_width=8, address_width=32):
self.write_port = LiteDRAMNativeWritePort(address_width=32,
data_width=data_width)
self.read_port = LiteDRAMNativeReadPort(address_width=32,
data_width=data_width)
self.submodules.fifo = LiteDRAMFIFO(
data_width=data_width,
base=base,
depth=depth,
write_port=self.write_port,
read_port=self.read_port,
)
margin = 8
self.memory = DRAMMemory(data_width, base + depth + margin)
def __init__(self):
# ports
self.write_port = LiteDRAMNativeWritePort(address_width=32,
data_width=32)
self.read_port = LiteDRAMNativeReadPort(address_width=32,
data_width=32)
# fifo
self.submodules.fifo = LiteDRAMFIFO(data_width=32,
depth=64,
base=0,
write_port=self.write_port,
read_port=self.read_port,
read_threshold=8,
write_threshold=64 - 8)
# memory
self.memory = DRAMMemory(32, 256)