def __init__(self,
sys_clk_freq=int(125e6),
integrated_rom_size=0x8000,
**kwargs):
platform = genesys2.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41J256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=False, **kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore -----------------------------------------------------------------_----------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="diamond",
integrated_rom_size=0x8000,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
**kwargs)
# crg
crg = _CRG(platform, sys_clk_freq)
self.submodules.crg = crg
# sdram
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41J256M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self,
uart="crossover",
sys_clk_freq=int(125e6),
with_bist=False,
with_analyzer=False):
platform = genesys2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteDRAM bench on Genesys2",
ident_version=True,
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
uart_name=uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
with_bist=with_bist)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial",
clk_freq=100e6,
baudrate=115200,
cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
with_hw_init_reset=False)
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv="analyzer.csv")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
sys_clk_freq=int(200e6),
with_pcie=False,
pcie_lanes=4,
**kwargs):
platform = quad_hdmi_recorder.Platform()
# SoCCore ----------------------------------------------------------------------------------
kwargs["uart_name"] = "crossover"
SoCCore.__init__(
self,
platform,
sys_clk_freq,
ident="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# JTAGBone --------------------------------------------------------------------------------
self.add_jtagbone()
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USDDRPHY(
pads=PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
memtype="DDR3",
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# PCIe -------------------------------------------------------------------------------------
# FIXME: Does not seem to be working when also enabling DRAM. Has been tested succesfully by
# disabling DRAM with --integrated-main-ram-size=0x100.
if with_pcie:
data_width = {
4: 128,
8: 256,
}[pcie_lanes]
self.submodules.pcie_phy = USPCIEPHY(
platform,
platform.request(f"pcie_x{pcie_lanes}"),
speed="gen3",
data_width=data_width,
bar0_size=0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# False Paths (FIXME: Improve integration).
platform.toolchain.pre_placement_commands.append(
"set_false_path -from [get_clocks sys_clk] -to [get_clocks pcie_clk_1]"
)
platform.toolchain.pre_placement_commands.append(
"set_false_path -from [get_clocks pcie_clk_1] -to [get_clocks sys_clk]"
)
def __init__(self,
sys_clk_freq=int(125e6),
with_ethernet=False,
with_etherbone=False,
**kwargs):
platform = genesys2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
cmd_latency=1)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="trellis",
with_ethernet=False,
with_led_chaser=True,
with_pmod_gpio=False,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Trellis Board",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
if with_pmod_gpio:
platform.add_extension(trellisboard.raw_pmod_io("pmoda"))
self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="trellis",
with_ethernet=False,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Trellis Board",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(12)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
self.add_ram("firmware_ram", 0x20000000, 0x10000)
def __init__(self, **kwargs):
platform = genesys2.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=125*1000000,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
# sdram
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT41J256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
with_led_chaser=True,
**kwargs):
platform = genesys2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Genesys2",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, uart="crossover", sys_clk_freq=int(125e6)):
platform = genesys2.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size = 0x8000,
integrated_rom_mode = "rw",
csr_data_width = 32,
uart_name = uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"]
)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
with_hw_init_reset = False)
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41J256M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self,
sys_clk_freq=int(50e6),
toolchain="trellis",
with_video_colorbars=False,
with_video_terminal=True,
with_video_framebuffer=False,
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
**kwargs):
platform = rcs_arctic_tern_bmc_card.Platform(toolchain=toolchain)
#bios_flash_offset = 0x400000
# Set CPU variant / reset address
#kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
kwargs["integrated_rom_size"] = 0x10000
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(
self,
platform,
irq_n_irqs=16,
clk_freq=sys_clk_freq,
ident="LiteX SoC on Arctic Tern (BMC card carrier)",
#integrated_main_ram_size = 0x40000,
#integrated_main_ram_size = 0,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41J256M16(
sys_clk_freq, "1:2"
), # Not MT41J256M16, but the AS4C256M16D3C in use has similar specifications
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks", 0),
pads=self.platform.request("eth", 0),
tx_delay=0e-9,
rx_delay=0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Video Output -----------------------------------------------------------------------------
if with_video_colorbars or with_video_terminal or with_video_framebuffer:
dvo_pads = platform.request("dvo")
self.submodules.videophy = VideoGenericPHY(
dvo_pads, clock_domain="dvo", with_clk_ddr_output=False)
if with_video_terminal:
#self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="dvo")
#self.add_video_terminal(phy=self.videophy, timings="1920x1200@60Hz", clock_domain="dvo")
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="dvo")
elif with_video_framebuffer:
#self.add_video_framebuffer(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="dvo")
#self.add_video_framebuffer(phy=self.videophy, timings="1920x1200@60Hz", clock_domain="dvo")
self.add_video_framebuffer(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="dvo")
else:
self.add_video_colorbars(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="dvo")
def __init__(self, platform, ddram="ddram_32", with_cpu=False):
clk_freq = int(125e6)
SoCSDRAM.__init__(self, platform, clk_freq,
cpu_type="lm32" if with_cpu else None,
integrated_rom_size=0x8000 if with_cpu else 0,
integrated_sram_size=0x8000 if with_cpu else 0,
csr_data_width=8 if with_cpu else 32,
l2_size=128,
with_uart=with_cpu, uart_stub=False,
ident="Sayma AMC SDRAM Test Design " + _build_version(),
with_timer=with_cpu
)
self.submodules.crg = _CRG(platform)
if not with_cpu:
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"),
clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.crg.cd_sys.clk.attr.add("keep")
platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
# firmware
firmware_ram_size = 0x10000
firmware_filename = "firmware/firmware.bin"
self.submodules.firmware_ram = firmware.FirmwareROM(firmware_ram_size, firmware_filename)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
# sdram
self.submodules.ddrphy = kusddrphy.KUSDDRPHY(platform.request(ddram))
sdram_module = MT41J256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# sdram bist
if not with_cpu:
generator_user_port = self.sdram.crossbar.get_port(mode="write")
self.submodules.generator = LiteDRAMBISTGenerator(
generator_user_port, random=True)
checker_user_port = self.sdram.crossbar.get_port(mode="read")
self.submodules.checker = LiteDRAMBISTChecker(
checker_user_port, random=True)
# leds
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += [
platform.request("user_led", 0).eq(led_counter[26]),
platform.request("user_led", 1).eq(led_counter[27]),
platform.request("user_led", 2).eq(led_counter[28]),
platform.request("user_led", 3).eq(led_counter[29])
]
# analyzer
if not with_cpu:
dfi_phase_groups = []
for i in range(4):
dfi_phase_group = [
self.ddrphy.dfi.phases[i].address,
self.ddrphy.dfi.phases[i].bank,
self.ddrphy.dfi.phases[i].ras_n,
self.ddrphy.dfi.phases[i].cas_n,
self.ddrphy.dfi.phases[i].we_n,
self.ddrphy.dfi.phases[i].cs_n,
self.ddrphy.dfi.phases[i].cke,
self.ddrphy.dfi.phases[i].odt,
self.ddrphy.dfi.phases[i].reset_n,
self.ddrphy.dfi.phases[i].wrdata_en,
self.ddrphy.dfi.phases[i].wrdata_mask,
self.ddrphy.dfi.phases[i].wrdata,
self.ddrphy.dfi.phases[i].rddata,
self.ddrphy.dfi.phases[i].rddata_valid
]
dfi_phase_groups.append(dfi_phase_group)
analyzer_signals = {
0 : dfi_phase_groups[0],
1 : dfi_phase_groups[1],
2 : dfi_phase_groups[2],
3 : dfi_phase_groups[3]
}
if not with_cpu:
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 64)
def __init__(self,
sys_clk_freq=int(75e6),
cpu_count=1,
with_ethernet=False,
**kwargs):
VexRiscvSMP.litedram_width = 128
VexRiscvSMP.ibus_width = 64
VexRiscvSMP.dbus_width = 64
VexRiscvSMP.coherent_dma = True
platform = trellisboard.Platform(toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
kwargs["integrated_rom_size"] = 0x10000
kwargs["csr_data_width"] = 8
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_cls=VexRiscvSMP,
cpu_variant="default",
**kwargs)
self.add_constant("config_cpu_count", cpu_count) # for dts generation
# PLIC ------------------------------------------------------------------------------------
self.bus.add_slave("plic",
self.cpu.plicbus,
region=SoCRegion(origin=0xf0C00000,
size=0x400000,
cached=False))
# CLINT ------------------------------------------------------------------------------------
self.bus.add_slave("clint",
self.cpu.cbus,
region=SoCRegion(origin=0xf0010000,
size=0x10000,
cached=False))
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(pads=PHYPadsReducer(
platform.request("ddram"), [0, 1]),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True,
controller_settings=ControllerSettings(
cmd_buffer_buffered=False,
with_auto_precharge=False))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self,
sys_clk_freq=int(75e6),
toolchain="trellis",
with_ethernet=False,
with_video_terminal=False,
with_video_framebuffer=False,
with_led_chaser=True,
with_pmod_gpio=False,
**kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Trellis Board",
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:2"),
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_ethernet(phy=self.ethphy)
# HDMI -------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
# PHY + TP410 I2C initialization.
hdmi_pads = platform.request("hdmi")
self.submodules.videophy = VideoDVIPHY(hdmi_pads,
clock_domain="init")
self.submodules.videoi2c = I2CMaster(hdmi_pads)
self.videoi2c.add_init(
addr=0x38,
init=[(0x08, 0x35
) # CTL_1_MODE: Normal operation, 24-bit, HSYNC/VSYNC.
])
# Video Terminal/Framebuffer.
if with_video_terminal:
self.add_video_terminal(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy,
timings="640x480@75Hz",
clock_domain="init")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
# GPIOs ------------------------------------------------------------------------------------
if with_pmod_gpio:
platform.add_extension(trellisboard.raw_pmod_io("pmoda"))
self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
def __init__(self,
sys_clk_freq=int(125e6),
cpu_count=1,
with_ethernet=False,
**kwargs):
VexRiscvSMP.litedram_width = 128
VexRiscvSMP.ibus_width = 64
VexRiscvSMP.dbus_width = 64
VexRiscvSMP.coherent_dma = True
platform = genesys2.Platform()
# SoCCore ----------------------------------------------------------------------------------
kwargs["integrated_rom_size"] = 0x10000
kwargs["csr_data_width"] = 8
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_cls=VexRiscvSMP,
cpu_variant="default",
**kwargs)
self.add_constant("config_cpu_count", cpu_count) # for dts generation
# PLIC ------------------------------------------------------------------------------------
self.bus.add_slave("plic",
self.cpu.plicbus,
region=SoCRegion(origin=0xf0C00000,
size=0x400000,
cached=False))
# CLINT ------------------------------------------------------------------------------------
self.bus.add_slave("clint",
self.cpu.cbus,
region=SoCRegion(origin=0xf0010000,
size=0x10000,
cached=False))
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
pads=PHYPadsReducer(platform.request("ddram"), [1, 2]),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
cmd_latency=1)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41J256M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True,
controller_settings=ControllerSettings(
cmd_buffer_buffered=False,
with_auto_precharge=False))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# JTAG ---------------------------------------------------------------------------------
self.submodules.jtag = S7JTAG()
self.comb += self.cpu.jtag_clk.eq(self.jtag.tck)
self.comb += self.cpu.jtag_enable.eq(1)
self.comb += self.cpu.jtag_capture.eq(self.jtag.capture)
self.comb += self.cpu.jtag_shift.eq(self.jtag.shift)
self.comb += self.cpu.jtag_update.eq(self.jtag.update)
self.comb += self.cpu.jtag_reset.eq(self.jtag.reset)
self.comb += self.cpu.jtag_tdi.eq(self.jtag.tdi)
self.comb += self.jtag.tdo.eq(self.cpu.jtag_tdo)
def __init__(self, platform):
clk_freq = int(125e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
cpu_type="lm32",
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
csr_data_width=8,
l2_size=128,
with_uart=True,
ident="Sayma Full Test Design ",
ident_version=True,
with_timer=True)
self.submodules.crg = _CRG(platform)
self.crg.cd_sys.clk.attr.add("keep")
# amc <--> rtm usr_uart / aux_uart redirection
aux_uart_pads = platform.request("serial", 1)
self.comb += [
aux_uart_pads.tx.eq(platform.request("usr_uart_p")),
platform.request("usr_uart_n").eq(aux_uart_pads.rx)
]
# firmware
firmware_ram_size = 0x10000
self.submodules.firmware_ram = wishbone.SRAM(firmware_ram_size)
self.register_mem("firmware_ram", self.mem_map["firmware_ram"],
self.firmware_ram.bus, firmware_ram_size)
# sdram
self.submodules.ddrphy = kusddrphy.KUSDDRPHY(
platform.request("ddram_64"))
self.add_constant("DDRPHY_WLEVEL", None)
self.add_constant("KUSDDRPHY", None)
sdram_module = MT41J256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# amc rtm link
serwb_phy = SERWBPHY(platform.device,
platform.request("serwb"),
mode="master")
self.submodules.serwb_phy = serwb_phy
# wishbone slave
serwb_core = SERWBCore(serwb_phy,
clk_freq,
mode="slave",
with_scrambling=False)
self.submodules += serwb_core
self.register_mem("serwb", self.mem_map["serwb"],
serwb_core.etherbone.wishbone.bus, 8192)
# leds
led_counter = Signal(32)
self.sync += led_counter.eq(led_counter + 1)
self.comb += [
platform.request("user_led", 0).eq(led_counter[26]),
platform.request("user_led", 1).eq(led_counter[27]),
platform.request("user_led", 2).eq(led_counter[28]),
platform.request("user_led", 3).eq(led_counter[29])
]
