def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs): platform = mercury_xu5.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Mercury XU5", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6) self.add_sdram("sdram", phy=self.ddrphy, module=MT40A256M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = mercury_xu5.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6, cmd_latency=0) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) self.add_sdram("sdram", phy=self.ddrphy, module=MT40A256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True)
def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = zcu104.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6, cmd_latency = 1) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MTA4ATF51264HZ(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) self.submodules.i2c = I2CMaster(platform.request("i2c")) self.add_csr("i2c") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = Cat(*[platform.request("user_led", i) for i in range(4)]), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = zcu104.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on ZCU104", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6) self.add_sdram("sdram", phy = self.ddrphy, module = MTA4ATF51264HZ(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = vcu118.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on VCU118", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6) self.add_sdram("sdram", phy=self.ddrphy, module=EDY4016A(sys_clk_freq, "1:4"), size=0x40000000, l2_cache_size=kwargs.get("l2_size", 8192)) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_led_chaser=True, with_pcie=False, **kwargs): platform = adi_adrv2crr_fmc.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on ADI ADRV2CRR-FMC", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform, sys_clk_freq, ddram_channel) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( pads = platform.request("ddram", ddram_channel), memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 400e6) self.add_sdram("sdram", phy = self.ddrphy, module = MT40A512M16(sys_clk_freq, "1:4"), size = 0x40000000, l2_cache_size = kwargs.get("l2_size", 8192) ) # PCIe ------------------------------------------------------------------------------------- if with_pcie: assert self.csr_data_width == 32 self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), speed = "gen3", data_width = 128, bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) # Fan -------------------------------------------------------------------------------------- # Full speed is _really_ loud and with this demo bitstream which is almost # empty, we can slow it way down and still keep the FPGA < 10C above ambient self.submodules.fan = PWM( default_enable = 1, default_period = 2500, default_width = 500 ) self.comb += platform.request("fan").pwm_n.eq(~self.fan.pwm) # SYSMON ----------------------------------------------------------------------------------- self.submodules.sysmon = ZynqUSPSystemMonitor() # JTAG ------------------------------------------------------------------------------------- self.add_jtagbone()
def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_pcie=False, with_led_chaser=False, with_hbm=False, **kwargs): platform = alveo_u280.Platform() if with_hbm: assert 225e6 <= sys_clk_freq <= 450e6 # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Alveo U280 (ES1)", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel, with_hbm) if with_hbm: # JTAGBone -------------------------------------------------------------------------------- self.add_jtagbone(chain=2) # Chain 1 already used by HBM2 debug probes. # Add HBM Core. self.submodules.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(HBMIP(platform)) # Connect four of the HBM's AXI interfaces to the main bus of the SoC. for i in range(4): axi_hbm = hbm.axi[i] axi_lite_hbm = AXILiteInterface(data_width=256, address_width=33) self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm) self.bus.add_slave(f"hbm{i}", axi_lite_hbm, SoCRegion(origin=0x4000_0000 + 0x1000_0000*i, size=0x1000_0000)) # 256MB. else: # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram", ddram_channel), memtype = "DDR4", cmd_latency = 1, # seems to work better with cmd_latency=1 sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 600e6, is_rdimm = True) self.add_sdram("sdram", phy = self.ddrphy, module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"), size = 0x40000000, l2_cache_size = kwargs.get("l2_size", 8192) ) # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ self.add_ram("firmware_ram", 0x20000000, 0x8000) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("gpio_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), channel=0, with_bist=False, with_analyzer=False): platform = xcu1525.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident="LiteDRAM bench on XCU1525", ident_version=True, integrated_rom_size=0x10000, integrated_rom_mode="rw", uart_name=uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, channel) # DDR4 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request( "ddram", channel), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6) self.add_sdram("sdram", phy=self.ddrphy, module=MT40A512M8(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=0x40000000, with_bist=with_bist) # Workaround for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") # UARTBone --------------------------------------------------------------------------------- if uart != "serial": self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") # Analyzer --------------------------------------------------------------------------------- if with_analyzer: from litescope import LiteScopeAnalyzer analyzer_signals = [self.ddrphy.dfi] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, depth=256, clock_domain="sys", csr_csv="analyzer.csv") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), channel=0, with_bist=False): platform = xcu1525.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x10000, integrated_rom_mode="rw", csr_data_width=32, uart_name=uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, channel) self.add_csr("crg") # DDR4 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request( "ddram", channel), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6) self.add_csr("ddrphy") self.add_sdram( "sdram", phy=self.ddrphy, module=MT40A512M8(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=0x40000000, with_bist=with_bist, ) # Workaround for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") # UARTBone --------------------------------------------------------------------------------- if uart != "serial": self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_pcie=False, **kwargs): platform = alveo_u280.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alveo U280", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( platform.request("ddram", ddram_channel), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6, is_rdimm=True) self.add_sdram("sdram", phy=self.ddrphy, module=MTA18ASF2G72PZ(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ self.add_ram("firmware_ram", 0x20000000, 0x8000) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("gpio_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = alveo_u250.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alveo U250", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6, cmd_latency=1, is_rdimm=True) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MTA18ASF2G72PZ(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ self.add_ram("firmware_ram", 0x20000000, 0x8000) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(3)]), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = mercury_xu5.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Mercury XU5", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6, cmd_latency=1) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT40A256M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(3)]), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_led_chaser=True, with_pcie=False, with_sata=False, **kwargs): platform = xcu1525.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on XCU1525", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( pads=platform.request("ddram", ddram_channel), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6) self.add_sdram("sdram", phy=self.ddrphy, module=MT40A512M8(sys_clk_freq, "1:4"), size=0x40000000, l2_cache_size=kwargs.get("l2_size", 8192)) # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter ( "qsfp2sata", 0, Subsignal("tx_p", Pins("N9")), Subsignal("tx_n", Pins("N8")), Subsignal("rx_p", Pins("N4")), Subsignal("rx_n", Pins("N3")), ), ] platform.add_extension(_sata_io) # RefClk, Generate 150MHz from PLL. self.clock_domains.cd_sata_refclk = ClockDomain() self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6) sata_refclk = ClockSignal("sata_refclk") # PHY self.submodules.sata_phy = LiteSATAPHY( platform.device, refclk=sata_refclk, pads=platform.request("qsfp2sata"), gen="gen2", clk_freq=sys_clk_freq, data_width=16) # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(200e6), disable_sdram=False, **kwargs): platform = ted_tfoil.Platform() SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on tfoil", ident_version=True, **kwargs) self.submodules.crg = _CRG(platform, sys_clk_freq) if not disable_sdram: if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=400e6) self.add_sdram("sdram", phy=self.ddrphy, module=MT40A1G8(sys_clk_freq, "1:4"), size=0x40000000, l2_cache_size=kwargs.get("l2_size", 8192)) self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) i2c_master_pads = [ platform.request("i2c_tca9555", 0), platform.request("i2c_tca9555", 1), platform.request("i2c_tca9555", 2), platform.request("i2c_tca9555", 3), platform.request("i2c_tca9555", 4), platform.request("i2c_tca9555", 5), platform.request("i2c_tca9555", 6), platform.request("i2c_tca9548", 0), platform.request("i2c_tca9548", 1), platform.request("i2c_tca9548", 2), platform.request("i2c_tca9548", 3), platform.request("i2c_si5341", 0), platform.request("i2c_si5341", 1), ] self.submodules.i2c = I2CMasterMP(platform, i2c_master_pads) self.submodules.sb_tca9548 = GPIOOut( pads=platform.request_all("tca9548_reset_n")) sb_si5341_o_pads = Cat([ platform.request("si5341_in_sel_0", 0), platform.request("si5341_in_sel_0", 1), platform.request("si5341_syncb", 0), platform.request("si5341_syncb", 1), platform.request("si5341_rstb", 0), platform.request("si5341_rstb", 1), ]) sb_si5341_i_pads = Cat([ platform.request("si5341_lolb", 0), platform.request("si5341_lolb", 1), ]) self.submodules.sb_si5341_o = GPIOOut(pads=sb_si5341_o_pads) self.submodules.sb_si5341_i = GPIOIn(pads=sb_si5341_i_pads) self._add_aurora(platform)
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs): platform = alveo_u250.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alveo U250", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6, cmd_latency=1, is_rdimm=True) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MTA18ASF2G72PZ(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------ self.add_ram("firmware_ram", 0x20000000, 0x8000) # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint( self.pcie_phy, max_pending_requests=8) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") self.add_constant("DMA_CHANNELS", 1) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_pcie=False, **kwargs): platform = xcu1525.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on XCU1525", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USPDDRPHY( pads=platform.request("ddram", ddram_channel), memtype="DDR4", sys_clk_freq=sys_clk_freq, iodelay_clk_freq=500e6, cmd_latency=1) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT40A512M8(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") # PCIe ------------------------------------------------------------------------------------- if with_pcie: # PHY self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) self.add_csr("pcie_phy") # Endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint( self.pcie_phy, max_pending_requests=8) # Wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, base_address=self.mem_map["csr"]) self.add_wb_master(self.pcie_bridge.wishbone) # DMA0 self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_buffering=True, buffering_depth=1024, with_loopback=True) self.add_csr("pcie_dma0") self.add_constant("DMA_CHANNELS", 1) # MSI self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def get_ddrphy(self): return usddrphy.USPDDRPHY(pads=self.platform.request("ddram"), memtype="DDR4", sys_clk_freq=self.sys_clk_freq, iodelay_clk_freq=500e6)