def __init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): BaseSoC.__init__(self, platform, cpu_type=None, csr_data_width=32, l2_size=32) # ethernet mac/udp/ip stack self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) # etherbone bridge self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 1234)) self.add_wb_master(self.cpu_or_bridge.wishbone.bus) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(25e6)) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(25e6)) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): BaseSoC.__init__(self, platform, cpu_type=None, csr_data_width=32) # Ethernet PHY and UDP/IP stack self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) # Etherbone bridge self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 20000)) self.add_wb_master(self.cpu_or_bridge.master.bus) self.specials += [ Keep(self.ethphy.crg.cd_eth_rx.clk), Keep(self.ethphy.crg.cd_eth_tx.clk) ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, **kwargs): BaseSoc.__init__(self, **kwargs) # ethernet PHY and UDP/IP stack mac_address = 0x10e2d5001000 ip_address = "192.168.1.50" self.submodules.ethphy = LiteEthPHY( self.platform.request("eth_clocks"), self.platform.request("eth"), self.clk_freq, # avoid huge reset delay in simulation with_hw_init_reset="synth" in argv) self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq) # MAC = wishbone slave = to let the CPU talk over ethernet # self.submodules.ethmac = LiteEthMAC( # phy=self.ethphy, dw=32, interface="wishbone", # endianness="little", with_preamble_crc=False # ) # self.add_wb_slave( # mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus # ) # self.add_memory_region( # "ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000 # ) # Etherbone = wishbone master = read and write registers remotely self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus)
def __init__(self, D, dst_ip="192.168.1.100"): ''' D must be >= phy datapath width send UDP packets with content 08 07 06 05 04 03 02 01 for n_words - 1 times 64 bit sequence number ''' self.source = source = stream.Endpoint(eth_udp_user_description(D * 8)) ### seq = Signal(64) timer = Signal(32) cur_word = Signal(16, reset=1) self.period = CSRStorage(32, reset=0x1FFFFFFF) self.dst_ip = CSRStorage( 32, reset=convert_ip(dst_ip), description='Destination IP address for UDP stream') self.dst_port = CSRStorage(16, reset=1337, description='Destination port number') self.n_words = CSRStorage( 16, reset=4, description='Number of D-bit words in the paket') self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.fsm.act( "IDLE", NextValue(timer, timer + 1), If((self.period.storage > 0) & (timer >= self.period.storage), NextValue(timer, 0), NextState("SEND"))) fsm.act( "SEND", source.valid.eq(1), source.src_port.eq(self.dst_port.storage), source.dst_port.eq(self.dst_port.storage), source.ip_address.eq(self.dst_ip.storage), source.length.eq(self.n_words.storage * D), # payload length If( cur_word == 1, source.data.eq(seq), ).Else(source.data.eq(0x0807060504030201)), If( cur_word >= self.n_words.storage, source.last.eq(1), # last_be indicates that this byte is the first one # which is no longer valid # if all bytes are valid in the last cycle, # set last=1 and last_be=0 source.last_be.eq(0x80), If( source.ready, NextValue(cur_word, 1), NextValue(seq, seq + 1), NextState("IDLE"), ), ).Else(If(source.ready, NextValue(cur_word, cur_word + 1))), )
def __init__(self, platform, with_ethernet=True, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): clk_freq = int(133e6) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="Daisho USB3.0 Test Design", with_timer=False) self.submodules.crg = _CRG(platform) # uart <--> wishbone self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 7.5) # ethernet PHY and UDP/IP stack if with_ethernet: self.submodules.eth_phy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.eth_core = LiteEthUDPIPCore( self.eth_phy, mac_address, convert_ip(ip_address), clk_freq) # ethernet <--> wishbone self.submodules.etherbone = LiteEthEtherbone( self.eth_core.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep") self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk, self.eth_phy.crg.cd_eth_tx.clk)
def __init__(self, platform, cpu_type=None, mac_address=0x10e2d5000000, ip_address="192.168.100.50", **kwargs): clk_freq = int(142e6) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, integrated_main_ram_size=0x8000, integrated_rom_size=0x10000, integrated_sram_size=0x8000, csr_data_width=32, with_uart=False, **kwargs) self.submodules.crg = CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # ethernet mac/udp/ip stack self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) self.add_csr("ethcore") # etherbone bridge self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 1234)) self.add_wb_master(self.cpu_or_bridge.wishbone.bus) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(125e6)) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(125e6)) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, host_ip="192.168.1.100", host_udp_port=2000): SimSoC.__init__( self, cpu_type="vexriscv", integrated_rom_size=0x10000, uart_name="sim", with_sdram=True, with_etherbone=True, etherbone_mac_address=0x10e2d5000001, etherbone_ip_address="192.168.1.50", sdram_module="MT48LC16M16", sdram_data_width=8, with_sdcard=True, ) # Sampler -------------------------------------------------------------------------------- data = Signal(8) self.sync += data.eq(data + 1) self.submodules.sampler = Sampler(data) self.add_csr("sampler") # DRAMFIFO --------------------------------------------------------------------------------- from litedram.frontend.fifo import LiteDRAMFIFO self.submodules.fifo = LiteDRAMFIFO( data_width=8, base=0x00000000, depth=0x01000000, # 16MB write_port=self.sdram.crossbar.get_port(mode="write", data_width=8), read_port=self.sdram.crossbar.get_port(mode="read", data_width=8), ) # UDPStreamer ------------------------------------------------------------------------------ from liteeth.common import convert_ip from liteeth.frontend.stream import LiteEthStream2UDPTX udp_port = self.ethcore.udp.crossbar.get_port(host_udp_port, dw=8) udp_streamer = LiteEthStream2UDPTX(ip_address=convert_ip(host_ip), udp_port=host_udp_port, fifo_depth=1024) udp_streamer = ClockDomainsRenamer("eth_tx")(udp_streamer) self.submodules += udp_streamer udp_cdc = stream.ClockDomainCrossing([("data", 8)], "sys", "eth_tx") self.submodules += udp_cdc # Sampler/FIFO/UDPStreamer flow ------------------------------------------------------------ self.comb += self.sampler.source.connect(self.fifo.sink) self.comb += self.fifo.source.connect(udp_cdc.sink) self.comb += udp_cdc.source.connect(udp_streamer.sink) self.comb += udp_streamer.source.connect(udp_port.sink)
def __init__(self, platform, mac_address=0x10e2d5000004, ip_address="10.0.11.2"): BaseSoC.__init__(self, platform, cpu_type="vexriscv", cpu_variant="debug", csr_data_width=8, l2_size=32) # ethernet mac/udp/ip stack self.submodules.ethphy = LiteEthPHYMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) # vexriscv debugging, at offset 0xf00f0000 self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu_or_bridge.debug_bus, 0x10) # Hook Etherbone up to the Wishbone bus, providing Wishbone over Ethernet. etherbone_cd = ClockDomain("etherbone") self.clock_domains += etherbone_cd self.comb += [ etherbone_cd.clk.eq(ClockSignal("sys")), etherbone_cd.rst.eq(ResetSignal("sys")) ] self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master", cd="etherbone") self.add_wb_master(self.etherbone.wishbone.bus) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(25e6)) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(25e6)) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, **kwargs): super().__init__(**kwargs) ip = "192.168.19.70" print(f"setting to {ip}") self.submodules.udp_core = LiteEthUDPIPCore(self.ethphy, 0x12345678abcd, convert_ip(ip), clk_freq=self.sys_clk_freq) self.add_csr("udp_core") self.udp_port = udp_port = self.udp_core.udp.crossbar.get_port(4321, 8) ddr_wr_port, ddr_rd_port = self.sdram.crossbar.get_port( "write"), self.sdram.crossbar.get_port("read") self.submodules.data_pipe = DataPipe(ddr_wr_port, ddr_rd_port, udp_port) self.add_csr("data_pipe")
def __init__(self, ip="192.168.19.70", **kwargs): super().__init__(with_ethernet=True, **kwargs) if kwargs.get('uart_name') == "crossover+bridge": self.uart.add_auto_tx_flush(self.sys_clk_freq) print("added_flush") self.platform.add_extension(marble.break_off_pmod) self.user_leds = self.platform.request("pmod0") self.submodules.udp_core = LiteEthUDPIPCore(self.ethphy, 0x12345678abcd, convert_ip(ip), clk_freq=self.sys_clk_freq) self.add_csr("udp_core") self.udp_port = udp_port = self.udp_core.udp.crossbar.get_port(4321, 8) ddr_wr_port, ddr_rd_port = self.sdram.crossbar.get_port("write"), self.sdram.crossbar.get_port("read") REAL_ADC = True if REAL_ADC: self.add_zest() adc_dw = self.zest.dw adc_source = self.zest.source self.submodules.async_fifo = async_fifo = ClockDomainsRenamer( {"write": "adc", "read": "sys"} )(AsyncFIFO([("data", adc_dw)], depth=8, buffered=True)) self.comb += [ async_fifo.sink.data.eq(self.zest.source.data), async_fifo.sink.valid.eq(self.zest.source.valid), async_fifo.source.ready.eq(1) ] self.adc_source = adc_source = async_fifo.source else: adc_dw = 64 self.submodules.adcs = adcs = ADCStream(1, adc_dw) self.adc_source = adc_source = adcs.source self.submodules.data_pipe = DataPipe(ddr_wr_port, ddr_rd_port, udp_port, adc_source, adc_dw) self.add_csr("data_pipe") self.add_rom("bootrom", origin=0x20000000, size=2**14, contents=get_mem_data("firmware/app.bin", endianness="little")) self.add_constant("ROM_BOOT_ADDRESS", 0x20000000)
def __init__(self, **kwargs): HelloLtc.__init__(self, **kwargs) p = self.platform # ethernet PHY and UDP/IP stack mac_address = 0x01E625688D7C ip_address = "192.168.1.50" self.submodules.ethphy = LiteEthPHY( p.request("eth_clocks"), p.request("eth"), self.clk_freq, # avoid huge reset delay in simulation with_hw_init_reset="synth" in argv ) self.submodules.core = LiteEthUDPIPCore( self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq ) # Etherbone = wishbone master = read and write registers remotely self.submodules.etherbone = LiteEthEtherbone( self.core.udp, 1234, mode="master" ) self.add_wb_master(self.etherbone.wishbone.bus)
def __init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): clk_freq = int(1e9/platform.default_clk_period) SoCMini.__init__(self, platform, clk_freq, ident="Daisho USB3.0 Test Design", ident_version=True) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # uart <--> wishbone self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) # ethernet PHY and UDP/IP stack self.submodules.eth_phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq) self.submodules.eth_core = LiteEthUDPIPCore(self.eth_phy, mac_address, convert_ip(ip_address), clk_freq) # ethernet <--> wishbone self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.crg.cd_sys.clk.attr.add("keep") self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep") self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 6.0) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk, self.eth_phy.crg.cd_eth_tx.clk)
def trigger_hardware(n_points, cap_ip, cap_port, csr_csv=None): wb = RemoteClient(csr_csv=csr_csv) wb.open() # Try communication a few times before giving up try_list = range(0, 3) for i in try_list: try: print(f"Tryout {i}") fifo_size = wb.regs.data_pipe_fifo_size.read() print(f"Fifo size was set to {fifo_size}") if n_points != fifo_size: print(f"Setting fifo size to {n_points}") wb.regs.data_pipe_fifo_size.write(n_points) print(f"fifo size set to {wb.regs.data_pipe_fifo_size.read()}") print(wb.regs.data_pipe_dst_ip.write(convert_ip(cap_ip))) print(wb.regs.data_pipe_dst_port.write(cap_port)) print(wb.regs.data_pipe_fifo_read.write(0)) print(wb.regs.data_pipe_fifo_load.write(1)) triggered_at = time.time() print(wb.regs.data_pipe_fifo_load.read()) while wb.regs.data_pipe_fifo_full.read() != 1: pass full_at = time.time() print(f"triggered at {triggered_at}") print(f"full at {full_at}. Now sending read command") wb.regs.data_pipe_fifo_read.write(1) except socket.timeout as e: # Last try if i == try_list[-1]: raise e else: continue else: break
def __init__(self, variant="minimal", with_sampler=False, with_analyzer=False, host_ip="192.168.1.100", host_udp_port=2000): platform = arty.Platform() # BenchSoC --------------------------------------------------------------------------------- bench_kwargs = { "minimal": dict(cpu_variant="minimal", integrated_main_ram_size=0x1000), "standard": dict(), }[variant] BaseSoC.__init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x10000, integrated_rom_mode="rw", **bench_kwargs) # SDCard on PMODD with Digilent's Pmod MicroSD --------------------------------------------- self.platform.add_extension(arty._sdcard_pmod_io) self.add_sdcard("sdcard") if with_sampler or with_analyzer: # Etherbone ---------------------------------------------------------------------------- from liteeth.phy.mii import LiteEthPHYMII self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) if with_sampler: # PMODB Sampler (connected to PmodTPH2 with Pmode Cable Kit) --------------------------- _la_pmod_ios = [("la_pmod", 0, Pins("pmoda:0 pmoda:1 pmoda:2 pmoda:3", "pmoda:4 pmoda:5 pmoda:6 pmoda:7"), IOStandard("LVCMOS33"))] self.platform.add_extension(_la_pmod_ios) self.submodules.sampler = Sampler(self.platform.request("la_pmod")) self.add_csr("sampler") # DRAMFIFO ----------------------------------------------------------------------------- from litedram.frontend.fifo import LiteDRAMFIFO self.submodules.fifo = LiteDRAMFIFO( data_width=8, base=0x00000000, depth=0x01000000, # 16MB write_port=self.sdram.crossbar.get_port(mode="write", data_width=8), read_port=self.sdram.crossbar.get_port(mode="read", data_width=8), ) # UDPStreamer -------------------------------------------------------------------------- from liteeth.common import convert_ip from liteeth.frontend.stream import LiteEthStream2UDPTX udp_port = self.ethcore.udp.crossbar.get_port(host_udp_port, dw=8) udp_streamer = LiteEthStream2UDPTX(ip_address=convert_ip(host_ip), udp_port=host_udp_port, fifo_depth=1024) udp_streamer = ClockDomainsRenamer("eth_tx")(udp_streamer) self.submodules += udp_streamer udp_cdc = stream.ClockDomainCrossing([("data", 8)], "sys", "eth_tx") self.submodules += udp_cdc # Sampler/FIFO/UDPStreamer flow ------------------------------------------------------------- self.comb += self.sampler.source.connect(self.fifo.sink) self.comb += self.fifo.source.connect(udp_cdc.sink) self.comb += udp_cdc.source.connect(udp_streamer.sink) self.comb += udp_streamer.source.connect(udp_port.sink) if with_analyzer: from litescope import LiteScopeAnalyzer analyzer_signals = [ self.sdphy.sdpads, self.sdphy.cmdw.sink, self.sdphy.cmdr.sink, self.sdphy.cmdr.source, self.sdphy.dataw.sink, self.sdphy.dataw.stop, self.sdphy.dataw.crc.source, self.sdphy.dataw.status.status, self.sdphy.datar.sink, self.sdphy.datar.source, self.sdphy.clocker.ce, self.sdphy.clocker.stop, ] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, depth=2048, clock_domain="sys", csr_csv="analyzer.csv") self.add_csr("analyzer")
csr_csv="analyzer.csv") self.add_csr("analyzer") # ------------------- # Testbench # ------------------- from litex.soc.interconnect.stream_sim import * from litex.gen.sim import * from liteeth.core import LiteEthUDPIPCore import sys sys.path.append('/home/michael/fpga_wsp/hello_petsys/') from model import phy, mac, arp, ip, icmp, dumps local_ip = convert_ip('192.168.1.9') local_mac = 0x001000000100 dst_ip = convert_ip('192.168.1.10') dst_mac = 0x012345654321 class DUT(Module): def __init__(self): D = 8 # Datapath width [bytes] self.clock_domains.cd_sys = ClockDomain() self.clock_domains.eth_tx = ClockDomain() self.clock_domains.eth_rx = ClockDomain() self.clk_freq = 100000
def __init__(self, ddr_wr_port, ddr_rd_port, udp_port, adc_source, adc_dw): SIZE = 1024 * 1024 self.fifo_full = CSRStatus(reset=0) self.fifo_error = CSRStatus(reset=0) self.fifo_load = CSRStorage(reset=0) self.fifo_read = CSRStorage(reset=0) self.fifo_size = CSRStorage(32, reset=SIZE) self.dst_ip = CSRStorage(32, reset=convert_ip("192.168.1.114")) self.dst_port = CSRStorage(16, reset=7778) self.fifo_counter = fifo_counter = Signal(24) self.load_fifo = load_fifo = Signal() dw = ddr_wr_port.data_width print( f"Write port: A ({ddr_wr_port.address_width})/ D ({ddr_wr_port.data_width})" ) print( f"Read port: A ({ddr_rd_port.address_width})/ D ({ddr_rd_port.data_width})" ) print(f"dw: {dw}; adc_dw: {adc_dw}") self.submodules.dram_fifo = dram_fifo = LiteDRAMFIFO( data_width=dw, base=0, depth=SIZE * (dw // 8), # liteDRAM expects this in bytes write_port=ddr_wr_port, read_port=ddr_rd_port, ) self.adc_data = adc_data = Signal(dw) DW_RATIO = dw // adc_dw log_dw_ratio = log2_int(DW_RATIO) word_count = Signal(log_dw_ratio) word_count_d = Signal(log_dw_ratio) self.sync += [ If(adc_source.valid, adc_data.eq(Cat(adc_data[adc_dw:], adc_source.data)), word_count.eq(word_count + 1)), word_count_d.eq(word_count), ] self.comb += [ dram_fifo.sink.valid.eq((word_count == 0) & (word_count_d != 0) & load_fifo), dram_fifo.sink.data.eq(adc_data) ] fifo_size = Signal(32) self.sync += [ fifo_size.eq(self.fifo_size.storage), If(self.fifo_load.re & self.fifo_load.storage, fifo_counter.eq(0), load_fifo.eq(1)), If(load_fifo & adc_source.valid, self.fifo_full.status.eq(0), self.fifo_error.status.eq(~dram_fifo.dram_fifo.ctrl.writable), fifo_counter.eq(fifo_counter + 1)), If((fifo_counter == fifo_size - 1) & adc_source.valid, load_fifo.eq(0), self.fifo_full.status.eq(1)), ] # fifo --> stride converter self.submodules.stride_converter = sc = stream.Converter( dw, udp_port.dw) self.read_from_dram_fifo = read_from_dram_fifo = Signal() self.comb += [dram_fifo.source.connect(sc.sink)] self.receive_count = receive_count = Signal(24) self.sync += [ If(dram_fifo.source.valid & dram_fifo.source.ready, receive_count.eq(receive_count + 1)).Elif( read_from_dram_fifo == 0, receive_count.eq(0)) ] # --> udp fragmenter --> self.submodules.udp_fragmenter = udp_fragmenter = UDPFragmenter( udp_port.dw) self.sync += read_from_dram_fifo.eq(self.fifo_read.storage) self.comb += If( read_from_dram_fifo, # TODO: There is a bug somewhere in the converter, # its source.last somehow gets set, no idea why. That signal is of no real use # for the fragmenter anyways, so we live without it sc.source.connect(udp_fragmenter.sink, omit={'total_size', 'last'})) # TODO: 8 should be adcstream data width // 8 self.comb += udp_fragmenter.sink.length.eq( fifo_size << log2_int(adc_dw // 8)) self.comb += udp_fragmenter.source.connect(udp_port.sink) self.comb += [ # param udp_port.sink.src_port.eq(4321), udp_port.sink.dst_port.eq(self.dst_port.storage), udp_port.sink.ip_address.eq(self.dst_ip.storage), # udp_port.sink.ip_address.eq(convert_ip("192.168.88.101")), # payload udp_port.sink.error.eq(0) ]
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50", with_analyzer=False, **kwargs): platform = Platform() sys_clk_freq = int(1e9/platform.default_clk_period) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, ident="LiteX Simulation", ident_version=True, with_uart=False, **kwargs) # crg self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # serial self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # sdram if with_sdram: sdram_module = IS42S16160(sys_clk_freq, "1:1") phy_settings = PhySettings( memtype="SDR", dfi_databits=1*16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram( self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_refresh=False)) # reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) assert not (with_ethernet and with_etherbone) # FIXME: fix simulator with 2 ethernet interfaces # ethernet if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac) self.submodules.ethmac = ethmac self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) # etherbone if with_etherbone: # eth phy self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME # eth core etherbonecore = LiteEthUDPIPCore(self.etherbonephy, etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq) if with_ethernet: etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore) self.submodules.etherbonecore = etherbonecore # etherbone self.submodules.etherbone = LiteEthEtherbone(self.etherbonecore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # analyzer if with_analyzer: analyzer_signals = [ # FIXME: find interesting signals to probe self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self, ddr_wr_port, ddr_rd_port, udp_port): SIZE = 1024 * 1024 SIZE = 1024 self.fifo_full = CSRStatus(reset=0) self.fifo_error = CSRStatus(reset=0) self.fifo_load = CSRStorage( reset=0) # Load the coefficients in memory to the ROI Summer self.fifo_read = CSRStorage(reset=0) self.fifo_size = CSRStorage(32, reset=SIZE) self.dst_ip = CSRStorage(32, reset=convert_ip("192.168.1.114")) self.dst_port = CSRStorage(16, reset=7778) dw = 64 print( f"Write port: A ({ddr_wr_port.address_width})/ D ({ddr_wr_port.data_width})" ) print( f"Read port: A ({ddr_rd_port.address_width})/ D ({ddr_rd_port.data_width})" ) self.submodules.dram_fifo = dram_fifo = LiteDRAMFIFO( data_width=dw, base=0, depth=SIZE, write_port=ddr_wr_port, read_port=ddr_rd_port, with_bypass=True, ) # self.mf = mf = Signal(reset=0) # mf == More Fragments # self.fragment_offset = fragment_offset = Signal(13, reset=0) # self.identification = identification = Signal(16, reset=0) self.submodules.adcs = adcs = ADCStream(1, dw) self.fifo_counter = fifo_counter = Signal(24) self.load_fifo = load_fifo = Signal() # adc --> buffer_fifo self.submodules.buffer_fifo = buffer_fifo = stream.SyncFIFO( stream.EndpointDescription([("data", dw)]), 256, buffered=True) # buffer_fifo --> dram_fifo fifo_size = Signal(32) self.sync += [ fifo_size.eq(self.fifo_size.storage), If(self.fifo_load.re & self.fifo_load.storage, fifo_counter.eq(0), load_fifo.eq(1)), If(load_fifo & adcs.source.valid, self.fifo_full.status.eq(0), self.fifo_error.status.eq(~dram_fifo.dram_fifo.ctrl.writable), fifo_counter.eq(fifo_counter + 1)), If((fifo_counter == fifo_size - 1) & adcs.source.valid, load_fifo.eq(0), self.fifo_full.status.eq(1)), ] self.comb += [ buffer_fifo.sink.data.eq(adcs.source.data), buffer_fifo.sink.valid.eq(adcs.source.valid & load_fifo), buffer_fifo.source.connect(dram_fifo.sink), ] # fifo --> stride converter self.submodules.stride_converter = sc = stream.Converter( dw, udp_port.dw) self.read_from_dram_fifo = read_from_dram_fifo = Signal() self.comb += [dram_fifo.source.connect(sc.sink)] self.receive_count = receive_count = Signal(24) self.sync += [ If(dram_fifo.source.valid & dram_fifo.source.ready, receive_count.eq(receive_count + 1)).Elif( read_from_dram_fifo == 0, receive_count.eq(0)) ] # --> udp fragmenter --> self.submodules.udp_fragmenter = udp_fragmenter = UDPFragmenter( udp_port.dw) self.sync += read_from_dram_fifo.eq(self.fifo_read.storage) self.comb += If( read_from_dram_fifo, # TODO: There is a bug somewhere in the converter, # its source.last somehow gets set, no idea why. That signal is of no real use # for the fragmenter anyways, so we live without it sc.source.connect(udp_fragmenter.sink, omit={'total_size', 'last'})) # TODO: 8 should be adcstream data width // 8 self.comb += udp_fragmenter.sink.length.eq(fifo_size << log2_int(dw // 8)) self.comb += udp_fragmenter.source.connect(udp_port.sink) self.comb += [ # param udp_port.sink.src_port.eq(4321), udp_port.sink.dst_port.eq(self.dst_port.storage), udp_port.sink.ip_address.eq(self.dst_ip.storage), # udp_port.sink.ip_address.eq(convert_ip("192.168.88.101")), # payload udp_port.sink.error.eq(0) ] # debug self.first_sample, self.last_sample = Signal(16), Signal(16) self.sync += [ If(fifo_counter == 1, self.first_sample.eq(adcs.source.data[:16])), If(fifo_counter == SIZE - 2, self.last_sample.eq(adcs.source.data[:16])), ]
def __init__(self, with_sdram=False, with_ethernet=False, with_etherbone=False, etherbone_mac_address=0x10e2d5000000, etherbone_ip_address="192.168.1.50", with_analyzer=False, **kwargs): platform = Platform() sys_clk_freq = int(1e6) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, ident="LiteX Simulation", ident_version=True, with_uart=False, **kwargs) # crg self.submodules.crg = CRG(platform.request("sys_clk")) # serial self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) self.submodules.uart = uart.UART(self.uart_phy) # sdram if with_sdram: sdram_module = MT48LC16M16(100e6, "1:1") # use 100MHz timings phy_settings = PhySettings( memtype="SDR", dfi_databits=16, nphases=1, rdphase=0, wrphase=0, rdcmdphase=0, wrcmdphase=0, cl=2, read_latency=4, write_latency=0 ) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.register_sdram( self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings) # reduce memtest size for simulation speedup self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024) assert not (with_ethernet and with_etherbone) # FIXME: fix simulator with 2 ethernet interfaces # ethernet if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) if with_etherbone: ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac) self.submodules.ethmac = ethmac self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) # etherbone if with_etherbone: # eth phy self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME # eth core etherbonecore = LiteEthUDPIPCore(self.etherbonephy, etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq) if with_ethernet: etherbonecore = ClockDomainsRenamer({"eth_tx": "etherbonephy_eth_tx", "eth_rx": "etherbonephy_eth_rx"})(etherbonecore) self.submodules.etherbonecore = etherbonecore # etherbone self.submodules.etherbone = LiteEthEtherbone(self.etherbonecore.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # analyzer if with_analyzer: analyzer_signals = [ # FIXME: find interesting signals to probe self.cpu.ibus, self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def __init__(self, sys_clk_freq=int(100e6), with_etherbone=True, eth_ip="192.168.1.50", with_video_terminal=False, with_video_framebuffer=False, **kwargs): platform = sds1104xe.Platform() # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "crossover" # Defaults to Crossover UART. SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Siglent SDS1104X-E", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_etherbone) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( pads=PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K64M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # Etherbone -------------------------------------------------------------------------------- if with_etherbone: # FIXME: Simplify LiteEth Hybrid MAC integration. from liteeth.common import convert_ip from liteeth.mac import LiteEthMAC from liteeth.core.arp import LiteEthARP from liteeth.core.ip import LiteEthIP from liteeth.core.udp import LiteEthUDP from liteeth.core.icmp import LiteEthICMP from liteeth.core import LiteEthUDPIPCore from liteeth.frontend.etherbone import LiteEthEtherbone # Ethernet PHY self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) etherbone_ip_address = convert_ip("192.168.1.51") etherbone_mac_address = 0x10e2d5000001 # Ethernet MAC self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8, interface="hybrid", endianness=self.cpu.endianness, hw_mac=etherbone_mac_address) # Software Interface. self.add_memory_region("ethmac", getattr(self.mem_map, "ethmac", None), 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) # Hardware Interface. self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8) self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8) self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8) self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8) self.add_constant( "ETH_PHY_NO_RESET" ) # Disable reset from BIOS to avoid disabling Hardware Interface. # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Timing constraints eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk eth_tx_clk = self.ethphy.crg.cd_eth_tx.clk self.platform.add_period_constraint(eth_rx_clk, 1e9 / self.ethphy.rx_clk_freq) self.platform.add_period_constraint(eth_tx_clk, 1e9 / self.ethphy.tx_clk_freq) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) # Video ------------------------------------------------------------------------------------ video_timings = ("800x480@60Hz", { "pix_clk": 33.3e6, "h_active": 800, "h_blanking": 256, "h_sync_offset": 210, "h_sync_width": 1, "v_active": 480, "v_blanking": 45, "v_sync_offset": 22, "v_sync_width": 1, }) if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("lcd"), clock_domain="dvi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings=video_timings, clock_domain="dvi") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings=video_timings, clock_domain="dvi")
def __init__(self, sys_clk_freq=int(100e6), with_etherbone=True, eth_ip="192.168.1.50", **kwargs): platform = sds1104xe.Platform() # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "crossover" # Defaults to Crossover UART. SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Siglent SDS1104X-E", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT41K64M16(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Etherbone -------------------------------------------------------------------------------- if with_etherbone: # FIXME: Simplify LiteEth Hybrid MAC integration. from liteeth.common import convert_ip from liteeth.mac import LiteEthMAC from liteeth.core.arp import LiteEthARP from liteeth.core.ip import LiteEthIP from liteeth.core.udp import LiteEthUDP from liteeth.core.icmp import LiteEthICMP from liteeth.core import LiteEthUDPIPCore from liteeth.frontend.etherbone import LiteEthEtherbone # Ethernet PHY ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.submodules += ethphy etherbone_ip_address = convert_ip("192.168.1.51") etherbone_mac_address = 0x10e2d5000001 # Ethernet MAC self.submodules.ethmac = LiteEthMAC(phy=ethphy, dw=8, interface="hybrid", endianness=self.cpu.endianness, hw_mac=etherbone_mac_address) # Software Interface. self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) # Hardware Interface. self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8) self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8) self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8) self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8) # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Timing constraints eth_rx_clk = ethphy.crg.cd_eth_rx.clk eth_tx_clk = ethphy.crg.cd_eth_tx.clk self.platform.add_period_constraint(eth_rx_clk, 1e9 / ethphy.rx_clk_freq) self.platform.add_period_constraint(eth_tx_clk, 1e9 / ethphy.tx_clk_freq) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
def add_xgmii(self): self.submodules.xgmii = XilinxXGMII(self.crg.cd_sys, self.platform) self.add_csr('xgmii') self.platform.add_period_constraint(self.xgmii.cd_clkmgt.clk, 1e9/156.25e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.xgmii.cd_clkmgt.clk) self.submodules.xgmiiphy = LiteEthPHYXGMII(self.xgmii.pads, self.xgmii.pads) # Keeping this away from sys_clk domain, and strictly leaving it in 156.25e6 self.submodules.teng_udp_core = ClockDomainsRenamer("clkmgt")(LiteEthUDPIPCore(self.xgmiiphy, 0xaa1233445566, convert_ip("10.1.0.3"), self.sys_clk_freq, dw=64)) self.add_csr("xgmiiphy") self.udp_port = udp_port = self.teng_udp_core.udp.crossbar.get_port(3000, 64) send_pkt = Signal(reset=0) always_xmit = True if always_xmit: send_pkt_counter_d = Signal() self.sync.clkmgt += [ send_pkt_counter_d.eq(self.counter[26]), send_pkt.eq(send_pkt_counter_d ^ self.counter[26]) ] sink_counter = Signal(16) SINK_LENGTH = 64 # 8 words shift = log2_int(64 // 8) # bits required to represent bytes per word words_per_packet = SINK_LENGTH >> shift # Note the clkmgt domain self.sync.clkmgt += [ If(send_pkt, sink_counter.eq(words_per_packet)), If((sink_counter > 0) & (udp_port.sink.ready == 1), sink_counter.eq(sink_counter - 1) ).Else( udp_port.sink.valid.eq(0), udp_port.sink.last.eq(0) ), udp_port.sink.valid.eq(sink_counter > 0), udp_port.sink.last.eq(sink_counter == 1), If(sink_counter == 1, udp_port.sink.last_be.eq(0x80) ).Else( udp_port.sink.last_be.eq(0x0) ) ] self.comb += self.user_leds[1].eq(udp_port.sink.valid) self.comb += [ # param udp_port.sink.src_port.eq(3000), udp_port.sink.dst_port.eq(7778), udp_port.sink.ip_address.eq(convert_ip("10.1.0.4")), udp_port.sink.length.eq(SINK_LENGTH), # payload udp_port.sink.data.eq(Cat(0xc0ffeec1ffee, sink_counter)), udp_port.sink.error.eq(0) ] self.add_csr("teng_udp_core")
def __init__(self, platform, with_sdram=True, with_ethernet=False, with_etherbone=True, with_sdcard=True, with_pcie=False, with_hdmi_in0=False, with_hdmi_out0=False, with_hdmi_in1=False, with_hdmi_out1=False, with_interboard_communication=False): assert not (with_pcie and with_interboard_communication) sys_clk_freq = int(100e6) sd_freq = int(100e6) SoCSDRAM.__init__(self, platform, sys_clk_freq, #cpu_type="vexriscv", l2_size=32, cpu_type=None, l2_size=32, #csr_data_width=8, csr_address_width=14, csr_data_width=32, csr_address_width=14, integrated_rom_size=0x8000, integrated_sram_size=0x4000, integrated_main_ram_size=0x8000 if not with_sdram else 0, ident="NeTV2 LiteX Test SoC", ident_version=True, reserve_nmi_interrupt=False) # crg self.submodules.crg = CRG(platform, sys_clk_freq) # dnax self.submodules.dna = dna.DNA() # xadc self.submodules.xadc = xadc.XADC() # icap self.submodules.icap = ICAP(platform) # flash self.submodules.flash = Flash(platform.request("flash"), div=math.ceil(sys_clk_freq/25e6)) # sdram if with_sdram: self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq, iodelay_clk_freq=200e6) sdram_module = MT41J128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # ethernet if with_ethernet: self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.crg.cd_eth.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.crg.cd_eth.clk) # etherbone if with_etherbone: self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, 0x10e2d5000000, convert_ip("192.168.1.50"), sys_clk_freq) self.add_cpu(LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")) self.add_wb_master(self.cpu.wishbone.bus) #self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") #self.add_wb_master(self.etherbone.wishbone.bus) self.crg.cd_eth.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.crg.cd_eth.clk) # sdcard self.submodules.sdclk = SDClockerS7() self.submodules.sdphy = SDPHY(platform.request("sdcard"), platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdtimer = Timer() self.submodules.bist_generator = BISTBlockGenerator(random=True) self.submodules.bist_checker = BISTBlockChecker(random=True) self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq) self.platform.add_period_constraint(self.sdclk.cd_sd.clk, 1e9/sd_freq) self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, 1e9/sd_freq) self.crg.cd_sys.clk.attr.add("keep") self.sdclk.cd_sd.clk.attr.add("keep") self.sdclk.cd_sd_fb.clk.attr.add("keep") self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.sdclk.cd_sd.clk, self.sdclk.cd_sd_fb.clk) # pcie if with_pcie: # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2")) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True) # pcie wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x80000000) self.add_wb_master(self.pcie_bridge.wishbone) # pcie dma self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # interboard communication if with_interboard_communication: self.clock_domains.cd_refclk = ClockDomain() self.submodules.refclk_pll = refclk_pll = S7PLL() refclk_pll.register_clkin(platform.lookup_request("clk50"), 50e6) refclk_pll.create_clkout(self.cd_refclk, 125e6) platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]") # qpll qpll = GTPQuadPLL(ClockSignal("refclk"), 125e6, 1.25e9) print(qpll) self.submodules += qpll # gtp gtp = GTP(qpll, platform.request("interboard_comm_tx"), platform.request("interboard_comm_rx"), sys_clk_freq, clock_aligner=True, internal_loopback=False) self.submodules += gtp counter = Signal(32) self.sync.tx += counter.eq(counter + 1) # send counter to other-board self.comb += [ gtp.encoder.k[0].eq(1), gtp.encoder.d[0].eq((5 << 5) | 28), gtp.encoder.k[1].eq(0), gtp.encoder.d[1].eq(counter[26:]) ] # receive counter and display it on leds self.comb += [ platform.request("user_led", 3).eq(gtp.rx_ready), platform.request("user_led", 4).eq(gtp.decoders[1].d[0]), platform.request("user_led", 5).eq(gtp.decoders[1].d[1]) ] gtp.cd_tx.clk.attr.add("keep") gtp.cd_rx.clk.attr.add("keep") platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq) platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.tx_clk_freq) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk) # hdmi in 0 if with_hdmi_in0: hdmi_in0_pads = platform.request("hdmi_in", 0) self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq) self.submodules.hdmi_in0 = HDMIIn( hdmi_in0_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk), for clk in [self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6)) # hdmi out 0 if with_hdmi_out0: hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True) self.submodules.hdmi_out0 = VideoOut( platform.device, platform.request("hdmi_out", 0), hdmi_out0_dram_port, "ycbcr422", fifo_depth=4096) for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) # hdmi in 1 if with_hdmi_in1: hdmi_in1_pads = platform.request("hdmi_in", 1) self.submodules.hdmi_in1_freq = FreqMeter(period=sys_clk_freq) self.submodules.hdmi_in1 = HDMIIn( hdmi_in1_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7", split_mmcm=True) self.comb += self.hdmi_in1_freq.clk.eq(self.hdmi_in1.clocking.cd_pix.clk), for clk in [self.hdmi_in1.clocking.cd_pix.clk, self.hdmi_in1.clocking.cd_pix1p25x.clk, self.hdmi_in1.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 1).clk_p, period_ns(148.5e6)) # hdmi out 1 if with_hdmi_out1: hdmi_out1_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out1_pix", reverse=True) self.submodules.hdmi_out1 = VideoOut( platform.device, platform.request("hdmi_out", 1), hdmi_out1_dram_port, "ycbcr422", fifo_depth=4096) for clk in [self.hdmi_out1.driver.clocking.cd_pix.clk, self.hdmi_out1.driver.clocking.cd_pix5x.clk]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) # led blinking (sys) sys_counter = Signal(32) self.sync.sys += sys_counter.eq(sys_counter + 1) self.comb += platform.request("user_led", 0).eq(sys_counter[26]) # led blinking (pcie) if with_pcie: pcie_counter = Signal(32) self.sync.pcie += pcie_counter.eq(pcie_counter + 1) self.comb += platform.request("user_led", 1).eq(pcie_counter[26]) # led blinking (sdcard) if with_sdcard: sd_counter = Signal(32) self.sync.sd += sd_counter.eq(sd_counter + 1) self.comb += platform.request("user_led", 1).eq(sd_counter[26])